PEB2255H-V13

PEB2255H-V13 Datasheet

F A LC H E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications PEB 2255 Version

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PEB2255H-V13	PEB2255H-V13 (pdf)

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Data Sheet, DS 1, July 2000 F A LC H E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications PEB 2255 Version Datacom Never stop thinking. Edition 2000-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list . Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, DS 1, July 2000 F A LC H E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications PEB 2255 Version Datacom Never stop thinking. PEB 2255 2000-07 Previous Version: Preliminary Data Sheet DS1 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide see our webpage at PEB 2255 FALC-LH V1.3 The framer and line interface component is designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. The digital functions as well as the analog characteristics are configured via a flexible microprocessor interface. Data Sheet 2000-07 PEB 2255 FALC-LH V1.3 Organization of this Document This Data Sheet is organized as follows • Chapter 1, Introduction Gives a general description of the product and its family, lists the key features, and presents some typical applications. • Chapter 2, Pin Descriptions Lists pin locations with associated signals, categorizes signals according to function, and describes signals. • Chapter 3 to Chapter 5, Functional Description E1/T1/J1 These chapters describe the functional blocks and principle operation modes, organized into separate sections for E1 and T1/J1 operation • Chapter 6 and Chapter 7, Operational Description E1/T1/J1 Shows the operation modes and how they are to be initialized separately for E1 and T1/J1 . • Chapter 8, Signaling Controller Operating Modes Describes signaling controller functions for both E1 and T1/J1 operation. • Chapter 9 and Chapter 10, E1 Registers and T1/J1 Registers Gives a detailed description of all implemented registers and how to use them in different applications/configurations. • Chapter 11, Electrical Characteristics Specifies maximum ratings, DC and AC characteristics. • Chapter 12, Package Outlines Shows the mechanical values of the device package. • Chapter 13, Appendix Gives an example for overvoltage protection and information about application notes and other support. • Chapter 14, Glossary • Index Data Sheet Signaling access via registers RS/XS1...12 is done without reordering of ABCD bits. Signaling access via registers RS/XS1...12 is done with reordering of ABCD bits. For details see description of registers XS1...12 on page 305 and RS1...12 on page 333 Transmit Transparent Mode Valid if loop-timed mode is enabled LIM2.ELT = SYPX/XMFS define the frame/multiframe begin on the transmit system highway. The transmitter is usually synchronized on this externally sourced frame boundary and generates the FAS bits according to this framing. Any change of the transmit time slot assignment or a transmit slip subsequently produces a change of the FAS bit positions. Disconnects the control of the transmit system interface from the transmitter. The transmitter is now in a free running mode without any possibility to update the multiframe position. The framing FAS bits generated by the transmitter is not disturbed in case of changing the transmit time slot assignment or transmit slip by the transmit system highway unless register XC1 is written. Useful in loop-timed applications. For correct operation the transmit elastic buffer 2 frames, SIC1.XBS1/0= 10 has to be enabled Receive Transparent Forwarding Setting this bit all 193 bits per frame of the incoming multiframe are forwarded to pin RDO transparently. In asynchronous state the received data may be transparently switched through if bit FMR2.DAIS is set. Data Sheet 2000-07 Transmit Control 0 Read/Write Value after RESET 00H XC0 BRM MFBS SFRZ PEB 2255 FALC-LH V1.3 T1/J1 Registers 0 XCO2 XCO1 XCO0 20 Enable Bit-Robbing Marker A one in this bit marks the robbed bit positions on the system highway. RSIGM marks the receive and XSIGM marks the transmit robbed bits. For correct operation bit FMR1.SIGM must be set. Enable pure Multiframe Begin Signals Valid only if ESF or F72 format is selected. If set, signals RMFB and XMFB indicate only the multiframe begin. Additional pulses every 12 frames are disabled. Select Freeze Output Signal RFSP is output on port RFSP/FREEZS Freeze status signal is output on port RFSP/FREEZS Transmit Clock Slot Offset Initial value loaded into the transmit bit counter at the trigger edge of SCLKX when the synchronous pulse on port SYPX is active. Setting of SIC1.SXSC enforces programming the offset values in the range of 0 to 192 bits with XCO0 always cleared. Data Sheet 2000-07 PEB 2255 FALC-LH V1.3 T1/J1 Registers Transmit Control 1 Read/Write Value after RESET 00H XC1 XCOS XTO5 XTO4 XTO3 XTO2 XTO1 XTO0 21 A write access to this address resets the transmit elastic buffer to its basic starting position. Therefore, updating of the value should only be done when the is initialized or when the buffer should be centered. As a consequence a transmit slip occurs. Transmit Clock Offset Shift Valid only if SIC1.SXSC = 0 The delay T between the beginning of time slot 0 and the initial edge of SCLKX after SYPX goes active is an even number in the range of 0 to 1022 SCLKX cycles. The delay T is an odd number in the range of 1 to 1023 SCLKX cycles. Transmit Time Slot Offset Initial value loaded into the transmit bit counter at the trigger edge of SCLKX when the synchronous pulse on port SYPX is active. Setting of SIC1.SXSC enforces programming the offset values in the range of 0 to 192 bits. Receive Control 0 Read/Write Value after RESET 00H RC0 RCOS SICS CRCI XCRCI RDIS RCO2 RCO1 RCO0 22 Receive Clock Offset Valid only if SIC1.SXSC = 0 The delay T between the beginning of time slot 0 and the initial edge of SCLKR after SYPX goes active is an even number in the range of 0 to 1022 SCLKX cycles. The delay T is an odd number in the range of 1 to 1023 SCLKX cycles.

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Data Sheet, DS 1, July 2000

F A LC H E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications PEB 2255 Version

Datacom

Never stop thinking.

Edition 2000-07

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany

Infineon Technologies AG

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list .

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, DS 1, July 2000

F A LC H E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications PEB 2255 Version

Datacom

Never stop thinking.

PEB 2255
2000-07

Previous Version:

Preliminary Data Sheet DS1

For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide see our webpage at

PEB 2255 FALC-LH V1.3

The framer and line interface component is designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. The digital functions as well as the analog characteristics are configured via a flexible microprocessor interface.

Data Sheet
2000-07

PEB 2255 FALC-LH V1.3

Organization of this Document This Data Sheet is organized as follows
• Chapter 1, Introduction

Gives a general description of the product and its family, lists the key features, and presents some typical applications.
• Chapter 2, Pin Descriptions Lists pin locations with associated signals, categorizes signals according to function, and describes signals.
• Chapter 3 to Chapter 5, Functional Description E1/T1/J1 These chapters describe the functional blocks and principle operation modes, organized into separate sections for E1 and T1/J1 operation
• Chapter 6 and Chapter 7, Operational Description E1/T1/J1 Shows the operation modes and how they are to be initialized separately for E1 and T1/J1 .
• Chapter 8, Signaling Controller Operating Modes Describes signaling controller functions for both E1 and T1/J1 operation.
• Chapter 9 and Chapter 10, E1 Registers and T1/J1 Registers Gives a detailed description of all implemented registers and how to use them in different applications/configurations.
• Chapter 11, Electrical Characteristics Specifies maximum ratings, DC and AC characteristics.
• Chapter 12, Package Outlines Shows the mechanical values of the device package.
• Chapter 13, Appendix Gives an example for overvoltage protection and information about application notes and other support.
• Chapter 14, Glossary
• Index

Data Sheet
Signaling access via registers RS/XS1...12 is done without reordering of ABCD bits.
Signaling access via registers RS/XS1...12 is done with reordering of ABCD bits.

For details see description of registers XS1...12 on page 305 and RS1...12 on page 333

Transmit Transparent Mode

Valid if loop-timed mode is enabled LIM2.ELT =

SYPX/XMFS define the frame/multiframe begin on the transmit system highway. The transmitter is usually synchronized on this externally sourced frame boundary and generates the FAS bits according to this framing. Any change of the transmit time slot assignment or a transmit slip subsequently produces a change of the FAS bit positions.

Disconnects the control of the transmit system interface from the transmitter. The transmitter is now in a free running mode without any possibility to update the multiframe position. The framing FAS bits generated by the transmitter is not disturbed in case of changing the transmit time slot assignment or transmit slip by the transmit system highway unless register XC1 is written. Useful in loop-timed applications. For correct operation the transmit elastic buffer 2 frames, SIC1.XBS1/0= 10 has to be enabled

Receive Transparent Forwarding

Setting this bit all 193 bits per frame of the incoming multiframe are forwarded to pin RDO transparently. In asynchronous state the received data may be transparently switched through if bit FMR2.DAIS is set.

Data Sheet
2000-07

Transmit Control 0 Read/Write Value after RESET 00H

XC0 BRM MFBS

SFRZ

PEB 2255 FALC-LH V1.3 T1/J1 Registers
0 XCO2 XCO1 XCO0 20

Enable Bit-Robbing Marker

A one in this bit marks the robbed bit positions on the system highway. RSIGM marks the receive and XSIGM marks the transmit robbed bits. For correct operation bit FMR1.SIGM must be set.

Enable pure Multiframe Begin Signals Valid only if ESF or F72 format is selected.

If set, signals RMFB and XMFB indicate only the multiframe begin. Additional pulses every 12 frames are disabled.

Select Freeze Output Signal RFSP is output on port RFSP/FREEZS Freeze status signal is output on port RFSP/FREEZS

Transmit Clock Slot Offset

Initial value loaded into the transmit bit counter at the trigger edge of SCLKX when the synchronous pulse on port SYPX is active. Setting of SIC1.SXSC enforces programming the offset values in the range of 0 to 192 bits with XCO0 always cleared.

Data Sheet
2000-07

PEB 2255 FALC-LH V1.3

T1/J1 Registers

Transmit Control 1 Read/Write Value after RESET 00H

XC1 XCOS

XTO5 XTO4 XTO3 XTO2 XTO1 XTO0 21

A write access to this address resets the transmit elastic buffer to its basic starting position. Therefore, updating of the value should only be done when the is initialized or when the buffer should be centered. As a consequence a transmit slip occurs.

Transmit Clock Offset Shift

Valid only if SIC1.SXSC = 0

The delay T between the beginning of time slot 0 and the initial edge of SCLKX after SYPX goes active is an even number in the range of 0 to 1022 SCLKX cycles.

The delay T is an odd number in the range of 1 to 1023 SCLKX cycles.

Transmit Time Slot Offset

Initial value loaded into the transmit bit counter at the trigger edge of SCLKX when the synchronous pulse on port SYPX is active. Setting of SIC1.SXSC enforces programming the offset values in the range of 0 to 192 bits.

Receive Control 0 Read/Write Value after RESET 00H

RC0 RCOS SICS CRCI XCRCI RDIS RCO2 RCO1 RCO0 22

Receive Clock Offset

Valid only if SIC1.SXSC = 0 The delay T between the beginning of time slot 0 and the initial edge of SCLKR after SYPX goes active is an even number in the range of 0 to 1022 SCLKX cycles.

The delay T is an odd number in the range of 1 to 1023 SCLKX cycles.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEB2255H-V13 Datasheet file may be downloaded here without warranties.

Datasheet ID: PEB2255H-V13 638406