IRPLPFC1

IRPLPFC1 Datasheet

IRPLPFC1 90-265VAC PFC Pre-regulator

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IRPLPFC1	IRPLPFC1 (pdf)

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Application Note AN-1179 IRPLPFC1 90-265VAC PFC Pre-regulator By Peter B. Green Table of Contents Page Introduction Power Factor and PFC Functional Design Equations Factors affecting PF and PCB Layout Considerations Bill of Test Results Safety Warning! The IRPLPFC1 power factor correction pre-regulator is based on a non-isolated Boost SMPS circuit topology. The output is nominally 420VDC. When operating the output produces potentially dangerous voltages! Additionally short circuiting or overloading the output will damage the board. The IRPLPFC1 demo board should be handled by qualified electrical engineers only! AN-1179 EVALUATION BOARD - IRPLPFC1 Introduction Many offline applications require power factor correction circuitry in order to minimize transmission line losses and stress on electrical generators and transformers created by high harmonic content and phase shift. Electronic appliances often incorporate switching power supplies SMPS which include capacitive filter circuitry followed by a bridge rectifier and bulk capacitor supplying a load. Without power factor correction circuitry a SMPS draws a high peak current close to the line voltage peak and almost no current over much of the cycle, resulting in a power factor of around with high total harmonic distortion. Power factor correction circuitry can be added to enable the appliance to draw a sinusoidal current from the AC line with negligible phase shift and very low harmonic distortion. This represents the best type of load for the power transmission grid so that power can be supplied without creating additional conductive losses in transmission lines or additional burden on transformers and generators. Costs to electricity providers are therefore reduced, which passes savings on to the consumer. The trend towards more efficient power utilization for offline appliances, power supplies and lighting converters makes high power factor and low total harmonic distortion of the line input current THDi desirable. Standards for power quality exist such as EN61000-3-2 in which specific current harmonic limits are detailed for various different applications. Compliance with class C limits is required for electronic lighting ballasts rated at 25W or above. Market preferences often require LED converters and light fixtures to offer good performance at even lower power ratings. For a product incorporating active power factor correction a THDi of less than 20% over a wide input voltage range, normally 100VAC to 305VAC is expected. In many cases THDi of less than 10% can be achieved over much or all of this voltage range. AN-1179 Important Safety Information The IRS2500 based PFC pre-regulator does not provide galvanic isolation of the output from the line input. Therefore if the system is supplied directly from a non-isolated input, an electrical shock hazard exists. The DC output voltage is high enough to produce a potentially lethal electrical shock therefore appropriate care should be taken when working on the IRPLPFC1 board. It is recommended that for laboratory evaluation that the IRPLPFC1 board be used with an isolated AC or DC input supply. The IRS2500 series Boost topology is suitable only for front end applications where isolation is either not necessary or provided elsewhere in the system. In addition since the IRPLPFC1 is a Boost converter there is no short circuit protection therefore care must be taken not to short circuit or overload the output. Power Factor and THD THD is defined as the RMS value of harmonic distortion from all components of an AC signal excluding the fundamental, expressed as a percentage of the RMS of the fundamental. In other words it quantifies the amount by which the signal deviates from a pure sinusoid; THD = ARMS − A12 A1 where A1 is the RMS amplitude of the fundamental and ARMS is the total RMS value of the complete current signal. THD of the current is often referred to as THDi to differentiate it from the voltage THD. It should be noted that THDi is not the only quantity contributing to power factor PF reduction since phase shift between current and voltage inputs are not factored into the THD calculation. Power factor is defined as the ratio of the real power, which is utilized by the load, to the apparent power which also includes reactive and distortion power. Power factor PF includes displacement power factor resulting from phase displacement created by circuit reactances and distortion power factor created by harmonics. Figure Power Vector Diagram AN-1179 The general formula for power factor is: PF = PRMS VRMS I RMS where PRMS is the real power consumed by the load. The displacement power factor is given the formula: DPF = where is the phase shift between the voltage and sinusoidal current. The following formula gives the distortion power factor: 1 + THD2 The following formula combines these to give the total power factor: PF = 1 + THD 2 where refers to the phase shift between the voltage and the fundamental component of the current and THD is expressed as a fraction. AN-1179 Figure 2 IRPLPFC1 Schematic AN-1179 PFC Functional Description Figure 2 shows the schematic for PFC pre-regulator based on a critical conduction mode Boost circuit. The IRS2500 pin out conforms to most industry standard power factor controllers and can be used as a drop in replacement for alternative parts in many applications and with minor modifications in many more. The IRPLPFC1 Boost PFC pre-regulator circuit consists of an EMI filter followed by a bridge rectifier which provides a full wave rectified voltage at the input to the Boost inductor LPFC. C3 provides an essential path for the circulating high frequency switching current. The EMI filter consisting of C1, L1, C2 and L2 provides reduction of common mode and series mode noise being conducted back onto the AC line. A series mode filter is necessary in PFC circuits operating in critical conduction mode since these produce higher current ripple than continuous mode systems. At power levels below 100W the benefits of critical conduction mode in the form of reduced switching losses outweigh the disadvantage of more filtering. In critical conduction mode CrCM also known as transition or boundary mode the PWM gate drive signal to MPFC maintains a constant on time during the line cycle apart except where additional on time is added near the zero crossing. The off time varies during the AC line cycle. Each new switching cycle begins when the energy stored in LPFC has been fully transferred to the output therefore the off time varies during the AC line cycle becoming longer at the peak. The on and off times not taking into account the additional on time modulation can be calculated by the following formulae: TON = L.IL pk 2 .Vin rms TOFF = L.IL pk .sin Vout − 2.Vin rms .sin Where ILpk is the peak current in the inductor and Boost MOSFET Q1 at the peak of the AC line cycle and is the phase angle of the instantaneous AC line voltage, which varies over the cycle. A feedback loop regulates the output voltage by adjusting the PWM on time. This takes place gradually over many line cycles so that the on time remains effectively constant over the period of a single line half cycle and therefore the input current follows the shape of the input voltage remaining sinusoidal. When the MOSFET switch Q1 is turned on, the inductor LPFC is connected between the rectified line input + and - causing the current in LPFC to increase linearly. When Q1 is turned off, LPFC is connected between the rectified line input + and the DC bus capacitor CPFC through diode DPFC. The stored energy in LPFC is transferred to the output, supplying current into CPFC.

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Application Note AN-1179

IRPLPFC1 90-265VAC PFC Pre-regulator

By Peter B. Green

Table of Contents

Page Introduction Power Factor and PFC Functional Design Equations Factors affecting PF and PCB Layout Considerations Bill of Test Results

Safety Warning!

The IRPLPFC1 power factor correction pre-regulator is based on a non-isolated Boost SMPS circuit topology. The output is nominally 420VDC. When operating the output produces potentially dangerous voltages! Additionally short circuiting or overloading the output will damage the board. The IRPLPFC1 demo board should be handled by qualified electrical engineers only!

AN-1179

EVALUATION BOARD - IRPLPFC1

Introduction

Many offline applications require power factor correction circuitry in order to minimize transmission line losses and stress on electrical generators and transformers created by high harmonic content and phase shift. Electronic appliances often incorporate switching power supplies SMPS which include capacitive filter circuitry followed by a bridge rectifier and bulk capacitor supplying a load. Without power factor correction circuitry a SMPS draws a high peak current close to the line voltage peak and almost no current over much of the cycle, resulting in a power factor of around with high total harmonic distortion. Power factor correction circuitry can be added to enable the appliance to draw a sinusoidal current from the AC line with negligible phase shift and very low harmonic distortion. This represents the best type of load for the power transmission grid so that power can be supplied without creating additional conductive losses in transmission lines or additional burden on transformers and generators. Costs to electricity providers are therefore reduced, which passes savings on to the consumer. The trend towards more efficient power utilization for offline appliances, power supplies and lighting converters makes high power factor and low total harmonic distortion of the line input current THDi desirable. Standards for power quality exist such as EN61000-3-2 in which specific current harmonic limits are detailed for various different applications. Compliance with class C limits is required for electronic lighting ballasts rated at 25W or above. Market preferences often require LED converters and light fixtures to offer good performance at even lower power ratings. For a product incorporating active power factor correction a THDi of less than 20% over a wide input voltage range, normally 100VAC to 305VAC is expected. In many cases THDi of less than 10% can be achieved over much or all of this voltage range.

AN-1179

Important Safety Information The IRS2500 based PFC pre-regulator does not provide galvanic isolation of the output from the line input. Therefore if the system is supplied directly from a non-isolated input, an electrical shock hazard exists. The DC output voltage is high enough to produce a potentially lethal electrical shock therefore appropriate care should be taken when working on the IRPLPFC1 board. It is recommended that for laboratory evaluation that the IRPLPFC1 board be used with an isolated AC or DC input supply. The IRS2500 series Boost topology is suitable only for front end applications where isolation is either not necessary or provided elsewhere in the system. In addition since the IRPLPFC1 is a Boost converter there is no short circuit protection therefore care must be taken not to short circuit or overload the output.

Power Factor and THD

THD is defined as the RMS value of harmonic distortion from all components of an AC signal excluding the fundamental, expressed as a percentage of the RMS of the fundamental. In other words it quantifies the amount by which the signal deviates from a pure sinusoid;

THD =

ARMS − A12 A1
where A1 is the RMS amplitude of the fundamental and ARMS is the total RMS value of the complete current signal. THD of the current is often referred to as THDi to differentiate it from the voltage THD. It should be noted that THDi is not the only quantity contributing to power factor PF reduction since phase shift between current and voltage inputs are not factored into the THD calculation. Power factor is defined as the ratio of the real power, which is utilized by the load, to the apparent power which also includes reactive and distortion power. Power factor PF includes displacement power factor resulting from phase displacement created by circuit reactances and distortion power factor created by harmonics.

Figure Power Vector Diagram

AN-1179

The general formula for power factor is:

PF = PRMS VRMS I RMS
where PRMS is the real power consumed by the load. The displacement power factor is given the formula:

DPF =
where is the phase shift between the voltage and sinusoidal current. The following formula gives the distortion power factor:
1 + THD2

The following formula combines these to give the total power factor:

PF = 1 + THD 2
where refers to the phase shift between the voltage and the fundamental component of the current and THD is expressed as a fraction.

AN-1179

Figure 2 IRPLPFC1 Schematic

AN-1179

PFC Functional Description

Figure 2 shows the schematic for PFC pre-regulator based on a critical conduction mode Boost circuit. The IRS2500 pin out conforms to most industry standard power factor controllers and can be used as a drop in replacement for alternative parts in many applications and with minor modifications in many more. The IRPLPFC1 Boost PFC pre-regulator circuit consists of an EMI filter followed by a bridge rectifier which provides a full wave rectified voltage at the input to the Boost inductor LPFC. C3 provides an essential path for the circulating high frequency switching current. The EMI filter consisting of C1, L1, C2 and L2 provides reduction of common mode and series mode noise being conducted back onto the AC line. A series mode filter is necessary in PFC circuits operating in critical conduction mode since these produce higher current ripple than continuous mode systems. At power levels below 100W the benefits of critical conduction mode in the form of reduced switching losses outweigh the disadvantage of more filtering. In critical conduction mode CrCM also known as transition or boundary mode the PWM gate drive signal to MPFC maintains a constant on time during the line cycle apart except where additional on time is added near the zero crossing. The off time varies during the AC line cycle. Each new switching cycle begins when the energy stored in LPFC has been fully transferred to the output therefore the off time varies during the AC line cycle becoming longer at the peak.

The on and off times not taking into account the additional on time modulation can be calculated by the following formulae:

TON = L.IL pk 2 .Vin rms

TOFF =

L.IL pk .sin

Vout − 2.Vin rms .sin

Where ILpk is the peak current in the inductor and Boost MOSFET Q1 at the peak of the AC line cycle and is the phase angle of the instantaneous AC line voltage, which varies over the cycle.

A feedback loop regulates the output voltage by adjusting the PWM on time. This takes place gradually over many line cycles so that the on time remains effectively constant over the period of a single line half cycle and therefore the input current follows the shape of the input voltage remaining sinusoidal. When the MOSFET switch Q1 is turned on, the inductor LPFC is connected between the rectified line input + and - causing the current in LPFC to increase linearly. When Q1 is turned off, LPFC is connected between the rectified line input + and the DC bus capacitor CPFC through diode DPFC. The stored energy in LPFC is transferred to the output, supplying current into CPFC.

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Datasheet ID: IRPLPFC1 638368