AN983B-BG-T-V8

AN983B-BG-T-V8 Datasheet

AN983B/BX

Part	Datasheet
AN983B-BG-T-V8	AN983B-BG-T-V8 (pdf)

Related Parts	Information
AN983BX-BG-R-V1	AN983BX-BG-R-V1
AN983BX-BG-T-V3	AN983BX-BG-T-V3
AN983BX-BG-T-V1	AN983BX-BG-T-V1
AN983BLX-BG-T-V1	AN983BLX-BG-T-V1

PDF Datasheet Preview
AN983B/BX PCI/Mini PCI-to-Ethernet LAN PQFP - 128Pin Communications Never stop thinking. Edition 2005-12-15 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. AN983B/BX, PCI/Mini PCI-to-Ethernet LAN PQFP - 128Pin Previous Version: 2.P.14 Add LED info to pin diagram 2.CSR18[25]/PWRS_clr 1 means PCI_reset rising will clear CR49[1:0]/PWRS Page85/ 2002-07 Page45/ 2002-09 Page69/ 2003-05 2005-11-30 Minor change. Included Green package information Trademarks are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation, of Linus Torvalds, of Visio Corporation, and of Adobe Systems Incorporated. Template com_a4_tmplt.fm / / 2004-08-13 AN983B/BX General Description 8 System Block Diagram 8 Features 8 Block Diagram 10 Pin Assignment Diagram 11 Pin Type and Buffer Type Abbreviations 12 Pin Description 13 Functional Descriptions 19 Initialization Flow 19 Network Packet Buffer Management 19 Descriptor Structure Types 19 The Point of Descriptor Management 21 Transmit Scheme and Transmit Early Interrupt 23 Transmit Flow 23 Transmit Pre-fetch Data Flow 23 Transmit Early interrupt Scheme 24 Receive Scheme and Receive Early Interrupt Scheme 24 Network Operation 25 MAC Operation 26 Transceiver Operation 27 Flow Control in Full Duplex Application 29 LED Display Operation 32 First Mode 3 LED Displays 32 Second Mode 4 LED Displays 32 Reset Operation 32 Reset Whole Chip 32 Reset Transceiver Only 32 Wake on LAN Function 32 The Magic Packet Format 32 The Wake on LAN Operation 32 ACPI Power Management Function 33 Power States 33 General EEPROM Format Description 35 Registers and Descriptors Description 37 AN983B/BX Configuration Registers 38 AN983B/BX Configuration Registers Descriptions 39 PCI Control/Status Registers 51 PCI Control/Status Registers Description 52 PHY Registers Accessed by CSR9 MDI/MMC/MDO/MDC 85 PHY Transceiver Registers Descriptions 86 Descriptors and Buffer Management 94 Receive Descriptor Descriptions 95 Transmit Descriptor Descriptions 99 Electrical Specifications and Timings 102 Absolute Maximum Ratings 102 DC Specifications 102 AC Specifications 103 Timing Specifications 103 Package Outlines 111 invalidate command while being bus master • Supports big or little endian byte ordering EEPROM/Boot ROM I/F • Provides write-able Flash ROM and EPROM as boot ROM with size up to 128 KB • Provides PCI to access boot ROM by byte, word, or double word • Re-write Flash boot ROM through I/O port by programming register • Provides serial interface for read/write 93C46/66 EEPROM • Automatically load device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and Minimum-Grand from the 64 byte contents of 93C46/66 after PCI reset de-asserted in PCI environment. MAC/Physical • Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T • Provides Full -duplex operation on both 100 Mbit/s and 10 Mbit/s modes • Provides Auto-negotiation NWAY function of full/half duplex operation for both 10 and 100 Mbit/s • Provides transmit wave-shaper, receives filters, and adaptive equalizer • Provides MLT-3 transceiver with DC restoration for Base-line wander compensation • Provides MAC and Transceiver TXCVR loop-back modes for diagnostic • Built in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder • Supports external transmit transformer with turn ratio 1:1 • Supports external receive transformer with turn ratio 1:1 LED Display • 3 LED displays scheme provided 100 Mbit/s on or Speed 10 off Link keeps on when link ok or Activity will be blinking with 10 Hz when receiving or transmitting but not collision FD keeps on when in Full duplex mode or Collision will be blinking with 20 Hz when colliding • 4 LED displays scheme provided 100 Mbit/s and Link keep on when link and 100 Mbit/s 10 Mbit/s and Link keep on when link and 10 Mbit/s Activity will be blinking with 10 Hz when receiving or transmitting but not collision FD keeps on when in Full duplex mode or Collision will be blinking with 20 Hz when colliding Data Sheet Miscellaneous • Provides 128-pin QFP/LQFP packages for PCI/mini-PCI interfaces • V power supply with 5 V/3.3 V I/O tolerance Block Diagram AN983B/BX Block Diagram CR/CSR/XR Registers DMA Control Power Management Control LEDs Display PCI I/F Control Boot ROM I/F Transit FIFO FIFO Control Transmit MAC Loop-back Control 100BASE-TX 10BASE-T Physical Medium I/F EEPROM I/F Receive FIFO Receive MAC Clock Generator Figure 2 Block Diagram of the AN983B/BX Data Sheet Pin Assignment Diagram AN983B/BX Pin Assignment Diagram 128 bra 12 127 bra 11/Mdc 126 bra 10/Mtxen 125 BrCS# 124 EECS 123 BrD7/ECK 122 BrD6/EDI 121 BrD5/EDO 120 BrD4/Mrxdv 119 BrD3/MrxD3 118 BrD2/MrxD2 117 BrD1/MrxD1 116 BrD0/MrxD0 115 BrWE#/Rxclk 114 BrOE#/Txclk 113 bra 9/MtxD3 112 bra 8/MtxD2 111 Vdd-3 110 bra 7/MtxD1 109 bra 6/MtxD0 108 bra 5/Mtxerr 107 Vss-3 106 bra 4 105 bra 16/LED-FD/Co 104 LED-100Lnk 103 LED-10Lnk bra 13 bra 14 bra 15 VAAR TST3

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AN983B/BX

PCI/Mini PCI-to-Ethernet LAN PQFP - 128Pin

Communications

Never stop thinking.

Edition 2005-12-15

Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

AN983B/BX, PCI/Mini PCI-to-Ethernet LAN PQFP - 128Pin

Previous Version:
2.P.14 Add LED info to pin diagram
2.CSR18[25]/PWRS_clr 1 means PCI_reset rising will clear CR49[1:0]/PWRS

Page85/ 2002-07

Page45/ 2002-09

Page69/ 2003-05
2005-11-30 Minor change. Included Green package information

Trademarks
are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation, of Linus Torvalds, of Visio Corporation, and of Adobe Systems

Incorporated.

Template com_a4_tmplt.fm / / 2004-08-13

AN983B/BX

General Description 8

System Block Diagram 8

Features 8

Block Diagram 10

Pin Assignment Diagram 11 Pin Type and Buffer Type Abbreviations 12

Pin Description 13

Functional Descriptions 19 Initialization Flow 19 Network Packet Buffer Management 19

Descriptor Structure Types 19 The Point of Descriptor Management 21 Transmit Scheme and Transmit Early Interrupt 23 Transmit Flow 23 Transmit Pre-fetch Data Flow 23 Transmit Early interrupt Scheme 24 Receive Scheme and Receive Early Interrupt Scheme 24 Network Operation 25 MAC Operation 26 Transceiver Operation 27 Flow Control in Full Duplex Application 29 LED Display Operation 32 First Mode 3 LED Displays 32 Second Mode 4 LED Displays 32 Reset Operation 32 Reset Whole Chip 32 Reset Transceiver Only 32 Wake on LAN Function 32 The Magic Packet Format 32 The Wake on LAN Operation 32 ACPI Power Management Function 33 Power States 33

General EEPROM Format Description 35

Registers and Descriptors Description 37 AN983B/BX Configuration Registers 38

AN983B/BX Configuration Registers Descriptions 39 PCI Control/Status Registers 51

PCI Control/Status Registers Description 52 PHY Registers Accessed by CSR9 MDI/MMC/MDO/MDC 85

PHY Transceiver Registers Descriptions 86 Descriptors and Buffer Management 94

Receive Descriptor Descriptions 95 Transmit Descriptor Descriptions 99

Electrical Specifications and Timings 102 Absolute Maximum Ratings 102 DC Specifications 102 AC Specifications 103 Timing Specifications 103

Package Outlines 111
invalidate command while being bus master
• Supports big or little endian byte ordering

EEPROM/Boot ROM I/F
• Provides write-able Flash ROM and EPROM as boot ROM with size up to 128 KB
• Provides PCI to access boot ROM by byte, word, or double word
• Re-write Flash boot ROM through I/O port by programming register
• Provides serial interface for read/write 93C46/66 EEPROM
• Automatically load device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and

Minimum-Grand from the 64 byte contents of 93C46/66 after PCI reset de-asserted in PCI environment.

MAC/Physical
• Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T
• Provides Full -duplex operation on both 100 Mbit/s and 10 Mbit/s modes
• Provides Auto-negotiation NWAY function of full/half duplex operation for both 10 and 100 Mbit/s
• Provides transmit wave-shaper, receives filters, and adaptive equalizer
• Provides MLT-3 transceiver with DC restoration for Base-line wander compensation
• Provides MAC and Transceiver TXCVR loop-back modes for diagnostic
• Built in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
• Supports external transmit transformer with turn ratio 1:1
• Supports external receive transformer with turn ratio 1:1

LED Display
• 3 LED displays scheme provided 100 Mbit/s on or Speed 10 off Link keeps on when link ok or Activity will be blinking with 10 Hz when receiving or transmitting but not collision FD keeps on when in Full duplex mode or Collision will be blinking with 20 Hz when colliding
• 4 LED displays scheme provided 100 Mbit/s and Link keep on when link and 100 Mbit/s 10 Mbit/s and Link keep on when link and 10 Mbit/s Activity will be blinking with 10 Hz when receiving or transmitting but not collision FD keeps on when in Full duplex mode or Collision will be blinking with 20 Hz when colliding

Data Sheet

Miscellaneous
• Provides 128-pin QFP/LQFP packages for PCI/mini-PCI interfaces
• V power supply with 5 V/3.3 V I/O tolerance

Block Diagram

AN983B/BX

Block Diagram

CR/CSR/XR Registers

DMA Control

Power Management Control

LEDs Display

PCI I/F Control

Boot ROM I/F

Transit FIFO

FIFO Control

Transmit MAC

Loop-back Control
100BASE-TX 10BASE-T Physical Medium I/F

EEPROM I/F

Receive FIFO

Receive MAC

Clock Generator

Figure 2 Block Diagram of the AN983B/BX

Data Sheet

Pin Assignment Diagram

AN983B/BX

Pin Assignment Diagram
128 bra 12 127 bra 11/Mdc 126 bra 10/Mtxen 125 BrCS# 124 EECS 123 BrD7/ECK 122 BrD6/EDI 121 BrD5/EDO 120 BrD4/Mrxdv 119 BrD3/MrxD3 118 BrD2/MrxD2 117 BrD1/MrxD1 116 BrD0/MrxD0 115 BrWE#/Rxclk 114 BrOE#/Txclk 113 bra 9/MtxD3 112 bra 8/MtxD2 111 Vdd-3 110 bra 7/MtxD1 109 bra 6/MtxD0 108 bra 5/Mtxerr 107 Vss-3 106 bra 4 105 bra 16/LED-FD/Co 104 LED-100Lnk 103 LED-10Lnk
bra 13
bra 14
bra 15

VAAR

TST3

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AN983B-BG-T-V8 Datasheet file may be downloaded here without warranties.

Datasheet ID: AN983B-BG-T-V8 637597