ADM6996LHX-AC-T-1

ADM6996LHX-AC-T-1 Datasheet

ADM6996L

Part	Datasheet
ADM6996LHX-AC-T-1	ADM6996LHX-AC-T-1 (pdf)

Related Parts	Information
ADM6996LX-AA-T-1	ADM6996LX-AA-T-1
ADM6996LX-AA-R-1	ADM6996LX-AA-R-1

PDF Datasheet Preview
An Infineon Technologies Company ADM6996L 6 port 10/100 Mb/s Single Chip Ethernet Switch Controller Data Sheet Version Infineon-ADMtek Co Ltd Information in this document is provided in connection with Infineon-ADMtek Co Ltd products. InfineonADMtek Co Ltd may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Infineon-ADMtek Co Ltd reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The products may contain design defects or errors know as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. To obtain latest documentation please contact you local Infineon-ADMtek Co Ltd sales office or visit Infineon-ADMtek Co Ltd’s website at *Third-party brands and names are the property of their respective owners. 2004 by ADMtek Incorporated All Rights Reserved. Infineon-ADMtek Co. Ltd. About this Manual General Release Intended Audience Infineon-ADMtek Co Ltd’s Customers Structure This Data sheet contains 6 chapters Chapter 1 Product Overview Chapter 2 Interface Description Chapter 3 Function Description Chapter Register Description Chapter Electrical Specification Chapter Packaging Version 02 Sep 2003 07 October 2003 17 November 2003 12 January 2004 28 April 2004 Change First release of ADM6996L Updated Section and Updated Section & Updated Section - 8 Updated Infineon-ADMtek logo Customer Support Infineon-ADMtek Co Ltd, 2F, No.2, Li-Hsin Rd., Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Sales Information Tel + 886-3-5788879 Fax + 886-3-5788871 V1.04 Infineon-ADMtek Co. Ltd. Table of Contents Chapter 1 Product Overview 1-1-1 Features 1-2 Applications 1-2 Block Diagram 1-3 1-3 Conventions 1-5 Data 1-5 Pin 1-5 Register 1-5 Chapter 2 Interface Description 2-1 Pin Diagram 2-1 Pin Description by Function 2-2 Twisted Pair 2-2 6th Port MII 2-2 LED 2-4 EEPROM/Management Interface 2-5 Power/Ground, 48 2-5 MISC 2-6 Chapter 3 Function Description 3-1 Functional Descriptions 3-1 10/100M PHY Block 3-1 100Base-X Module 3-1 100Base-X Receiver 3-2 A/D 3-2 Adaptive Equalizer and timing Recovery Module 3-2 NRZI/NRZ and Serial/Parallel 3-2 Data 3-3 Symbol Alignment 3-3 Symbol Decoding 3-3 Valid Data 3-3 Receive Errors 3-4 100Base-X Link 3-4 Carrier Sense 3-4 Bad SSD 3-4 Far-End Fault 3-5 100Base-TX Transceiver 3-5 Transmit 3-5 Twisted-Pair 3-5 10Base-T 3-5 Operation Modes 3-6 Manchester Encoder/Decoder 3-6 Transmit Driver and Receiver 3-6 Smart Squelch 3-6 Carrier 3-7 V1.04 ADM6996L Infineon-ADMtek Co. Ltd. Jabber 3-7 Link Test 3-7 Automatic Link Polarity 3-8 Clock Synthesizer 3-8 Auto 3-8 Memory Block 3-8 Switch Functional 3-9 Basic 3-9 Address Learning 3-9 Address Recognition and Packet Forwarding 3-10 Address Aging 3-10 Back off Algorithm 3-10 Inter-Packet Gap IPG 3-10 Illegal 3-11 Half Duplex Flow Control 3-11 Full Duplex Flow 3-11 Broadcast Storm 3-11 Auto TP MDIX 3-11 Port 3-12 VLAN setting & Tag/Untag & port-base VLAN 3-12 Priority Setting 3-13 LED Display 3-13 Chapter 4 Register Description 4-1 EEPROM 4-1 EEPROM Register 4-1 EEPROM Register 4-2 Signature Register, offset 4-2 Configuration Registers, offset 0x01h ~ 0x09h 4-3 Reserved Register, offset 4-3 Configuration Register, offset 4-4 Reserved Register, offset 0x0ch~0x0dh 4-4 VLAN priority Map Register, offset 0x0eh 4-4 TOS priority Map Register, offset 4-4 Packet with Priority Normal packet content 4-5 VLAN 4-5 TOS IP 4-1 Miscellaneous Configuration Register, offset 0x10h.............................. 4-1 VLAN mode select Register, offset 4-2 Miscellaneous Configuration register, offset 0x12h 4-5 VLAN mapping table registers, offset 0x22h ~ 0x13h 4-5 Reserved Register, offset 0x27h ~ 4-5 Port0, 1 PVID bit 11 ~ 4 Configuration Register, offset 0x28h 4-1 Port2, 3 PVID bit 11 ~ 4 Configuration Register, offset 0x29h 4-1 Port4, 5 PVID bit 11~4 Configuration Register, offset 0x2ah 4-1 Port6, 7 PVID bit 11~4 Configuration Register, offset 0x2bh 4-1 Port8 PVID bit 11~4 & VLAN group shift bits Configuration Register.. 4-1 V1.04 ADM6996L Infineon-ADMtek Co. Ltd. Reserved Register, offset 4-2 Reserved Register, offset 0x2eh 4-2 PHY Restart, offset 4-2 Miscellaneous Configuration Register, offset 0x30h.............................. 4-2 Bandwidth Control Register0~3, offset 4-3 Bandwidth Control Register 4~5, offset 4-3 Bandwidth Control Enable Register, offset 0x33h 4-4 EEPROM Access 4-4 Serial Register 4-6 Serial Register Description 4-7 Chip Identifier Register, offset 4-7 Port Status 0 Register, offset 0x01h 4-7 Port Status 1 Register, offset 0x02h 4-9 Cable Broken Status Register, offset 4-9 Over Flow Flag 0 Register, offset 4-10 Over Flow Flag 0 Register 0x3bh 4-10 Over Flow Flag 2 Register, offset 4-11 Serial Interface Timing 4-1 Chapter 5 Electrical 5-1 TX/FX 5-1 TP Interface 5-1 FX Interface 5-1 DC Characteristics 5-2 Absolute Maximum 5-2 Recommended Operating Conditions 5-2 DC Electrical Characteristics for 3.3V Operation 5-2 AC Characteristics 5-3 Power On 5-3 EEPROM Interface 5-3 10Base-TX MII Input Timing 5-4 10Base-TX MII Output Timing 5-4 100Base-TX MII Input Timing 5-5 100Base-TX MII Output Timing 5-5 GPSI 7-wire Input Timing 5-6 GPSI 7-wire Output Timing 5-6 Chapter 6-1 128 Pin PQFP Outside 6-1 V1.04 List of Figures Figure 1-1 ADM6996L Block Diagram 1-3 Figure 2-1 5 TP/FX PORT + 1 MII PORT 128 Pin 2-1 ADM6996L

PDF Datasheet Preview

An Infineon Technologies Company

ADM6996L
6 port 10/100 Mb/s Single Chip Ethernet Switch Controller

Data Sheet Version

Infineon-ADMtek Co Ltd

Information in this document is provided in connection with Infineon-ADMtek Co Ltd products. InfineonADMtek Co Ltd may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Infineon-ADMtek Co Ltd reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The products may contain design defects or errors know as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. To obtain latest documentation please contact you local Infineon-ADMtek Co Ltd sales office or visit Infineon-ADMtek Co Ltd’s website at *Third-party brands and names are the property of their respective owners.
2004 by ADMtek Incorporated All Rights Reserved.

Infineon-ADMtek Co. Ltd.

About this Manual General Release Intended Audience Infineon-ADMtek Co Ltd’s Customers

Structure

This Data sheet contains 6 chapters Chapter 1 Product Overview Chapter 2 Interface Description Chapter 3 Function Description Chapter Register Description Chapter Electrical Specification Chapter Packaging

Version
02 Sep 2003
07 October 2003
17 November 2003
12 January 2004
28 April 2004

Change First release of ADM6996L Updated Section and Updated Section & Updated Section - 8 Updated Infineon-ADMtek logo

Customer Support

Infineon-ADMtek Co Ltd, 2F, No.2, Li-Hsin Rd., Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C.

Sales Information

Tel + 886-3-5788879 Fax + 886-3-5788871

V1.04

Infineon-ADMtek Co. Ltd.

Table of Contents

Chapter 1 Product Overview 1-1-1 Features 1-2 Applications 1-2 Block Diagram 1-3 1-3 Conventions 1-5 Data 1-5 Pin 1-5 Register 1-5

Chapter 2 Interface Description 2-1 Pin Diagram 2-1 Pin Description by Function 2-2 Twisted Pair 2-2 6th Port MII 2-2 LED 2-4 EEPROM/Management Interface 2-5 Power/Ground, 48 2-5 MISC 2-6

Chapter 3 Function Description 3-1 Functional Descriptions 3-1 10/100M PHY Block 3-1 100Base-X Module 3-1 100Base-X Receiver 3-2 A/D 3-2 Adaptive Equalizer and timing Recovery Module 3-2 NRZI/NRZ and Serial/Parallel 3-2 Data 3-3 Symbol Alignment 3-3 Symbol Decoding 3-3 Valid Data 3-3 Receive Errors 3-4 100Base-X Link 3-4 Carrier Sense 3-4 Bad SSD 3-4 Far-End Fault 3-5 100Base-TX Transceiver 3-5 Transmit 3-5 Twisted-Pair 3-5 10Base-T 3-5 Operation Modes 3-6 Manchester Encoder/Decoder 3-6 Transmit Driver and Receiver 3-6 Smart Squelch 3-6 Carrier 3-7

V1.04

ADM6996L

Infineon-ADMtek Co. Ltd.

Jabber 3-7 Link Test 3-7 Automatic Link Polarity 3-8 Clock Synthesizer 3-8 Auto 3-8 Memory Block 3-8 Switch Functional 3-9 Basic 3-9

Address Learning 3-9 Address Recognition and Packet Forwarding 3-10 Address Aging 3-10 Back off Algorithm 3-10 Inter-Packet Gap IPG 3-10 Illegal 3-11 Half Duplex Flow Control 3-11 Full Duplex Flow 3-11 Broadcast Storm 3-11 Auto TP MDIX 3-11 Port 3-12 VLAN setting & Tag/Untag & port-base VLAN 3-12 Priority Setting 3-13 LED Display 3-13 Chapter 4 Register Description 4-1 EEPROM 4-1 EEPROM Register 4-1 EEPROM Register 4-2 Signature Register, offset 4-2 Configuration Registers, offset 0x01h ~ 0x09h 4-3 Reserved Register, offset 4-3 Configuration Register, offset 4-4 Reserved Register, offset 0x0ch~0x0dh 4-4 VLAN priority Map Register, offset 0x0eh 4-4 TOS priority Map Register, offset 4-4 Packet with Priority Normal packet content 4-5 VLAN 4-5 TOS IP 4-1 Miscellaneous Configuration Register, offset 0x10h.............................. 4-1 VLAN mode select Register, offset 4-2 Miscellaneous Configuration register, offset 0x12h 4-5 VLAN mapping table registers, offset 0x22h ~ 0x13h 4-5 Reserved Register, offset 0x27h ~ 4-5 Port0, 1 PVID bit 11 ~ 4 Configuration Register, offset 0x28h 4-1 Port2, 3 PVID bit 11 ~ 4 Configuration Register, offset 0x29h 4-1 Port4, 5 PVID bit 11~4 Configuration Register, offset 0x2ah 4-1 Port6, 7 PVID bit 11~4 Configuration Register, offset 0x2bh 4-1 Port8 PVID bit 11~4 & VLAN group shift bits Configuration Register.. 4-1

V1.04

ADM6996L

Infineon-ADMtek Co. Ltd.

Reserved Register, offset 4-2 Reserved Register, offset 0x2eh 4-2 PHY Restart, offset 4-2 Miscellaneous Configuration Register, offset 0x30h.............................. 4-2 Bandwidth Control Register0~3, offset 4-3 Bandwidth Control Register 4~5, offset 4-3 Bandwidth Control Enable Register, offset 0x33h 4-4 EEPROM Access 4-4 Serial Register 4-6 Serial Register Description 4-7 Chip Identifier Register, offset 4-7 Port Status 0 Register, offset 0x01h 4-7 Port Status 1 Register, offset 0x02h 4-9 Cable Broken Status Register, offset 4-9 Over Flow Flag 0 Register, offset 4-10 Over Flow Flag 0 Register 0x3bh 4-10 Over Flow Flag 2 Register, offset 4-11 Serial Interface Timing 4-1 Chapter 5 Electrical 5-1 TX/FX 5-1 TP Interface 5-1 FX Interface 5-1 DC Characteristics 5-2 Absolute Maximum 5-2 Recommended Operating Conditions 5-2 DC Electrical Characteristics for 3.3V Operation 5-2 AC Characteristics 5-3 Power On 5-3 EEPROM Interface 5-3 10Base-TX MII Input Timing 5-4 10Base-TX MII Output Timing 5-4 100Base-TX MII Input Timing 5-5 100Base-TX MII Output Timing 5-5 GPSI 7-wire Input Timing 5-6 GPSI 7-wire Output Timing 5-6 Chapter 6-1 128 Pin PQFP Outside 6-1

V1.04

List of Figures

Figure 1-1 ADM6996L Block Diagram 1-3 Figure 2-1 5 TP/FX PORT + 1 MII PORT 128 Pin 2-1

ADM6996L

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Datasheet ID: ADM6996LHX-AC-T-1 637590