IMPROVING Z893X1 DSP FAMILY MEMORY READ AND WRITE Datasheet
IMPROVING Z893X1 DSP FAMILY MEMORY READ AND WRITE
A SIMPLE CHANGE IN THE BUS CONNECTION CAN DRAMATICALLY AFFECT THE PERFORMANCE OF THE Z893X1 DSP CHIP-EVEN WITHOUT A BARREL SHIFTER!
The Barrel Shifter Problem In applications requiring reading and writing to memory, cost constraints often dictate that a 16-bit DSP or 16-bit microcontroller will be connected to 8-bit-wide memory instead of the expected 16-bit-wide memory. Specifically, 8-bit-wide SRAM or 8-bit FLASH Memory prove to be cost effective and are widely used instead of 16-bit-wide SRAM or 16-bit FLASH Memory or two 8-bit-wide half-size SRAM or two 8-bit-wide half-size FLASH Memory.
Zilog’s Z89321 and Z89371 chips (Z893X1 DSP family) provide for the favored system architecture where a 16-bit DSP or microcontroller connect to 8-bit memory. There is, however, one apparent drawback the Z893X1 does not have a flexible Barrel Shifter. Without the Barrel Shifter, variable-length left shift cannot be executed in one instruction (one cycle). Each time data is stored (written) to and later retrieved (read) from memory, a conversion from word (16 bits) to two bytes (8 bits) and from two bytes to word must be performed. What is needed is an 8-bit logical left-shift operation however, the Z893X1 DSP core does not have this instruction. The Z893X1 performs 8 one-bit, shift-left instructions, resulting in too many instructions and less than optimal performance in some cases.
Improving Performance without a Barrel Shifter This app. note describes a new system architecture that dramatically improves the performance of reading (conversion from bytes to word) and writing (conversion from word to bytes) to memory for the Z893X1 DSP family-even though it does not have a Barrel Shifter. In this solution, one shift-left instruction replaces the need for 8 shift-left instructions, and the process of reading from the SRAM (or FLASH) and writing to the SRAM (or FLASH) takes only 14 instructions (cycles), instead of the usual 23 instructions-a dramatic 64 percent increase in performance.
A Real-Life Competition Scenario
A Zilog Field Area Engineer (FAE) recently had a customer with an application demanding very critical word-to-bytes (writing) and bytes-to-word conversions (reading). This particular customer was in a critical loop to determine the performance (operation frequency) of their system, and the customer was using this critical loop to determine DSP performance of Zilog’s Z893X1 and the competition.
After evaluating their application and price range requirements, the decision came down to two chips the Zilog Z89321 and one other chip from a competing DSP vendor. As usual, there are advantages and disadvantages in any competitive situation the disadvantage of the Zilog Z89321 chip compared to the competitor’s chip is the lack of a Barrel Shifter. The advantage of the Zilog chip is higher instruction rate (operation speed)-20 MIPS for the Z89321 or 16 MIPS for the Z89371 (OTP version of the Z89321), compared to a much lower 12 MIPS for the low-cost version of the competitor’s chip.
The “Straightforward” Z893X1 Solution In the straightforward customer solution using the Z89321, the process of reading from the SRAM and writing to the SRAM took 23 instructions (cycles). (Refer to the “Code_1 The Customer Original Z893X1 Assembler” code listing in the Source Code Listings section at the conclusion of this app. note.) Each A-D sample requires 20 passes through this code. The Z89371 works at 16 MHz, therefore each sample requires 28.75 µsec. There is a requirement of 31 kHz sampling rate therefore, the period between interrupts is 32.26 µsec. This leaves only 10.875 percent of the time for the background process, which is not acceptable.
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