HR-4/3FAU(4.5AH)L5X2

HR-4/3FAU(4.5AH)L5X2 Datasheet

Part	Datasheet
HR-4/3FAU(4.5AH)L5X2	HR-4/3FAU(4.5AH)L5X2 (pdf)

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LXT970A Dual-Speed Fast Ethernet Transceiver Datasheet The LXT970A Dual-Speed Fast Ethernet Transceiver called hereafter the LXT970A Transceiver is an enhanced derivative of the LXT970 10/100 Mbps Fast Ethernet PHY Transceiver that supports selectable driver strength capabilities and link-loss criteria. The LXT970A Transceiver supports 100BASE-TX, 10BASE-T, and 100BASE-FX applications. It provides a Media Independent Interface MII for easy attachment to 10/100 Media Access Controllers MAC s and a pseudo-ECL interface for use with 100BASE-FX fiber networks. The LXT970A Transceiver supports full-duplex operation at 10 and 100 Mbps. Its operating condition is set using auto-negotiation, parallel detection or manual control. The encoder may be bypassed for symbol mode applications. The LXT970A Transceiver is fabricated with an advanced CMOS process and requires only a single 5V power supply. The MII may be operated independently with either a 5V or a 3.3V supply. • Combination 10BASE-T/100BASE-TX Network Interface Cards NICs • 10/100 Switches, 10/100 Printservers Product Features • 100BASE-FX Network Interface Cards NICs • IEEE Compliant: 10BASE-T and 100BASE-TX using a single RJ-45 connection. Supports auto-negotiation and parallel detection for legacy systems. MII interface with extended register capability. • Robust baseline wander correction performance. • 100BASE-FX fiber optic capable. • Standard CSMA/CD or full-duplex operation. • Configurable via MII serial port or external control pins. • Configurable for DTE or switch applications. • CMOS process with single 5Vsupply operation with provision for interface to 3.3V MII bus. • Integrated LED drivers. • Integrated supply monitor and line disconnect during low supply fault. • Available in: 64-pin TQFP FALXT970ATC Transceiver JALXT970ATC Transceiver RoHSCompliant 64-pin PQFP SLXT970AQC Transceiver EGLXT970AQC Transceiveer RoHSCompliant • Commercial temperature range 0 - 70oC ambient . Order Number 249099-002 25-Nov-2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. The LXT970A Dual-Speed Fast Ethernet Transceiver may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2005, Intel Corporation. All Rights Reserved. Datasheet LXT970A Dual-Speed Fast Ethernet Transceiver Contents Pin Assignments and Signal Descriptions Functional 18 18 Interfaces Network Media/Protocol Support 19 Twisted-Pair Interface 19 Fiber Interface 19 MII Interface 20 Selectable Driver 20 MII Data Interface 21 Repeater 24 MII Management Interface 24 Hardware Control Interface 26 Operating Requirements Power Supply Requirements Optional MII Power Supply 27 Reference Clock Requirements 28 Master Clock Mode 28 Slave Clock Mode 28 Bias Circuit Requirements 29 Control Mode Selection 29 MDIO Control Mode Manual Control Mode 29 Link Configuration 29 Manual Configuration 30 Auto-Negotiation/Parallel Detection 30 Controlling Auto-Negotiation 31 Monitoring Operational 31 Monitoring Status via MII 31 Monitoring Status via Indicator Pins 32 100BASE-X Operation 32 100BASE-X MII 32 100BASE-X Network Operations 10BASE-T 35 10BASE-T MII 35 10BASE-T Network 35 Protocol Sublayer Operations 35 PCS 35 100X Preamble Handling 36 10T Preamble 36 Data Errors 100X Only 36 Collision Indication 37 SQE 10T Only Jabber 10T Only 38 PMA 38 100TX Link Options 38 Datasheet LXT970A Dual-Speed Fast Ethernet Transceiver 10T Link 38 Carrier Sense CRS 39 Twisted-Pair PMD Layer 39 Scrambler/Descrambler 100TX Only 39 Baseline Wander Correction 100TX Only 39 Polarity 39 Fiber PMD Layer 39 Additional Operating Features 40 Low-Voltage-Fault 40 Power Down Mode 40 Software 40 Hardware Reset 40 Application 41 Ordering Information 77 Datasheet LXT970A Dual-Speed Fast Ethernet Transceiver Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Block Diagram 9 Pin Assignments Network Interface Card NIC Application 18 MII Interface 20 MII Data Interface 21 Loopback Paths 23 Repeater Block Diagram 24 MDIO Interrupt Signaling 25 Management Interface - Read Frame Structure 25 Management Interface - Write Frame Structure 26 Initialization Sequence 30 Auto-Negotiation Operation 31 100BASE-TX Frame Structure 33 100BASE-TX Data Flow Protocol Sublayers 36 100BASE-TX Reception with No Errors 37 00BASE-TX Reception with Invalid Symbol 37 00BASE-TX Transmission with No Errors 37 00BASE-TX Transmission with Collision 37 Voltage Divider 45 Typical Interface Circuitry 46 MII - 100BASE-TX Receive Timing / 4B Mode 51 MII - 100BASE-TX Transmit Timing / 4B Mode 52 MII - 100BASE-TX Receive Timing / 5B Mode 53 100BASE-TX Transmit Timing / 5B Mode 54 MII - 100BASE-FX Receive Timing / 4B Mode 55 MII - 100BASE-FX Transmit Timing / 4B Mode 56 MII - 10BASE-T Receiving Timing 57 MII - 10BASE-T Transmit Timing 10BASE-T SQE Heartbeat Timing 59 10BASE-T Jab and Unjab Timing 59 Auto Negotiation and Fast Link Pulse Timing Fast Link Pulse Timing 60 MDIO Timing when Sourced by STA 61 MDIO Timing when Sourced by PHY 61 Power-Down Recovery Timing Over Recommended Range 62 PHY Identifier Bit Mapping 66 64-Pin QFP Package Diagram 73 64-Pin TQFP Package Diagram Sample TQFP Package FALXT970ATC Transceiver............................. 75 Sample Pb-Free RoHS-Compliant TQFP Package JALXT970ATC Transceiver75 Sample PQFP Package SLXT970AQC Transceiver 76 Sample Pb-Free RoHS-Compliant PQFP Package EGLXT970AQC Transceiver76 Ordering Information Matrix Sample 78 Datasheet LXT970A Dual-Speed Fast Ethernet Transceiver Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Power Supply Signal Descriptions 10 MII Signal Descriptions 11 Fiber Interface Signal Descriptions 12 Twisted-Pair Interface Signal Descriptions 13 LED Indicator Signal 13 Miscellaneous Signal 13 Hardware Control Interface Signal Descriptions 14 MF Pin Function Settings1, 3 16 Auto-Negotiation Operating Speed/Full-Duplex Advertisement Settings 17 Test Loopback Operation 23 Carrier Sense, Loopback, and Collision Conditions 23 Configuring the LXT970A Transceiver Via Hardware Control................... 26 Operating Configurations / Auto-Negotiation Enabled 26 Operating Configurations / Auto-Negotiation Disabled 27 Mode Control 29 Status using FDS/LED Pins 32 4B/5B Coding 34 Magnetics Requirements 41 Crystal 41 Crystal Component Manufacturers 41 Absolute Maximum Ratings 47 Operating Conditions 47 Digital I/O 48 Digital I/O Characteristics - MultiFunction Pins 48 Required Clock Characteristics 48 Low Voltage Fault Detect Characteristics 49 100BASE-TX Transceiver Characteristics 49 100BASE-FX Transceiver Characteristics 49 10BASE-T Transceiver 50 10BASE-T Link Integrity Timing Characteristics 50 MII - 100BASE-TX Receive Timing Parameters / 4B Mode 51 MII - 100BASE-TX Transmit Timing Parameters / 4B Mode 52 MII - 100BASE-TX Receive Timing Parameters / 5B Mode 53 MII - 100BASE-TX Transmit Timing Parameters / 5B Mode 54 MII - 100BASE-FX Receive Timing Parameters / 4B Mode 55 MII - 100BASE-FX Transmit Timing Parameters / 4B Mode 56 MII - 10BASE-T Receive Timing 57 MII - 10BASE-T Transmit Timing 58 10BASE-T SQE Heartbeat Timing Parameters 59 10BASE-T Jab and Unjab Timing 59 Auto Negotiation and Fast Link Pulse Timing 60 MDIO Timing Parameters 61 Power-Down Recovery Timing Parameters 62 Register Set 63 Control Register Address 64 Status Register Address 1 65 PHY Identification Register 1 Address 66 PHY Identification Register 2 Address 66 Auto Negotiation Advertisement Register Address 67 Datasheet LXT970A Dual-Speed Fast Ethernet Transceiver 50 Auto Negotiation Link Partner Ability Register Address 5 51 Auto Negotiation Expansion Address 6 69 52 Mirror Register Address 16, Hex 53 Interrupt Enable Register Address 17, Hex 11 70 54 Interrupt Status Register Address 18, Hex 12 70 55 Configuration Register Address 19, Hex 71 56 Chip Status Register Address 20, Hex 14 72 57 Product Information 77 Datasheet LXT970A Dual-Speed Fast Ethernet Transceiver Date 25-Nov-2005 January 2001 Description Modified Figure 2 “Pin Assignments” on page Added Section “Top Label Markings” on page Added Table 57 “Product Information” on page Added Figure 44 “Ordering Information Matrix Sample” on page Initial Release. Datasheet LXT970A Dual-Speed Fast Ethernet Transceiver Figure Block Diagram MII TX Hardware Interface TX_EN TX_ER TXD<0:4> TX_CLK MF<0:4> CFG<0:1> FDE TRSTE RESET FDS /M DI NT MDIO MDDIS XTALI/O 2 RX_CLK RXD<0:4> MII RX CRS COL RX_DV RX_ER PWR_DWN 10Mbps Loopback Management/ Mode Select Logic Parallel to Serial Converter Manchester Encoder Scrambler 100 & Encoder Auto Negotiation Pulse Shaper Crystal Osc & PLL Carrier Sense Collision Detect Data Valid Error Detect Serial to Parallel Converter Clock Generator Manchester 10 Decoder Decoder & Descrambler Slicer Baseline Wander Correction Pw rD own / Line Energy Monitor ECL Driver TP Driver LED Drivers FIBOP FIBON Ordering Information Table 57 lists the LXT970A Transceiver product ordering information. Figure 44 provides the ordering information matrix. Table Product Information Intel Number FALXT970ATC.B11 JALXT970ATC.B11 SLXT970AQC.B11 EGLXT970AQC.B11 Package Type TQFP PQFP Pin Count 64 RoHS Compliant No Yes No Yes Datasheet LXT970A Dual-Speed Fast Ethernet Transceiver Figure 44 shows an order matrix with sample information for the LXT970A Transceiver. Figure Ordering Information Matrix Sample LXT 970A Q C B11 Temperature Range A = Ambient 0 550 C = Commercial 0 700 C E = Extended -40 850 C Internal Package Designator L = LQFP P = PLCC N = DIP Q = PQFP H = QFP T = TQFP B = BGA C = CBGA E = TBGA K = HSBGA BGA with heat slug Product Code = 3-5 Digit alphanumeric IXA Product Prefix LXT = PHY layer device IXE = Switching engine IXF = Formatting device MAC/Framer IXP = Network processor Intel Package Designator B5426-01 Datasheet

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LXT970A Dual-Speed Fast Ethernet Transceiver

Datasheet

The LXT970A Dual-Speed Fast Ethernet Transceiver called hereafter the LXT970A Transceiver is an enhanced derivative of the LXT970 10/100 Mbps Fast Ethernet PHY Transceiver that supports selectable driver strength capabilities and link-loss criteria. The LXT970A Transceiver supports 100BASE-TX, 10BASE-T, and 100BASE-FX applications. It provides a Media Independent Interface MII for easy attachment to 10/100 Media Access Controllers MAC s and a pseudo-ECL interface for use with 100BASE-FX fiber networks.

The LXT970A Transceiver supports full-duplex operation at 10 and 100 Mbps. Its operating condition is set using auto-negotiation, parallel detection or manual control. The encoder may be bypassed for symbol mode applications.

The LXT970A Transceiver is fabricated with an advanced CMOS process and requires only a single 5V power supply. The MII may be operated independently with either a 5V or a 3.3V supply.
• Combination 10BASE-T/100BASE-TX Network Interface Cards NICs
• 10/100 Switches, 10/100 Printservers

Product Features
• 100BASE-FX Network Interface Cards NICs
• IEEE Compliant:
10BASE-T and 100BASE-TX using a single RJ-45 connection.

Supports auto-negotiation and parallel detection for legacy systems.

MII interface with extended register capability.
• Robust baseline wander correction performance.
• 100BASE-FX fiber optic capable.
• Standard CSMA/CD or full-duplex operation.
• Configurable via MII serial port or external control pins.
• Configurable for DTE or switch applications.
• CMOS process with single 5Vsupply operation with provision for interface to 3.3V MII bus.
• Integrated LED drivers.
• Integrated supply monitor and line disconnect during low supply fault.
• Available in:
64-pin TQFP FALXT970ATC Transceiver JALXT970ATC Transceiver RoHSCompliant
64-pin PQFP SLXT970AQC Transceiver EGLXT970AQC Transceiveer RoHSCompliant
• Commercial temperature range 0 - 70oC ambient .

Order Number 249099-002
25-Nov-2005

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. The LXT970A Dual-Speed Fast Ethernet Transceiver may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2005, Intel Corporation. All Rights Reserved.

Datasheet

LXT970A Dual-Speed Fast Ethernet Transceiver

Contents

Pin Assignments and Signal Descriptions

Functional 18
18 Interfaces Network Media/Protocol Support 19

Twisted-Pair Interface 19 Fiber Interface 19 MII Interface 20

Selectable Driver 20 MII Data Interface 21 Repeater 24 MII Management Interface 24 Hardware Control Interface 26 Operating Requirements Power Supply Requirements Optional MII Power Supply 27 Reference Clock Requirements 28 Master Clock Mode 28 Slave Clock Mode 28 Bias Circuit Requirements 29 Control Mode Selection 29 MDIO Control Mode Manual Control Mode 29 Link Configuration 29 Manual Configuration 30 Auto-Negotiation/Parallel Detection 30 Controlling Auto-Negotiation 31 Monitoring Operational 31 Monitoring Status via MII 31 Monitoring Status via Indicator Pins 32 100BASE-X Operation 32 100BASE-X MII 32 100BASE-X Network Operations 10BASE-T 35 10BASE-T MII 35 10BASE-T Network 35 Protocol Sublayer Operations 35 PCS 35 100X Preamble Handling 36 10T Preamble 36 Data Errors 100X Only 36 Collision Indication 37 SQE 10T Only Jabber 10T Only 38 PMA 38 100TX Link Options 38

Datasheet

LXT970A Dual-Speed Fast Ethernet Transceiver
10T Link 38 Carrier Sense CRS 39 Twisted-Pair PMD Layer 39 Scrambler/Descrambler 100TX Only 39 Baseline Wander Correction
100TX Only 39 Polarity 39 Fiber PMD Layer 39 Additional Operating Features 40 Low-Voltage-Fault 40 Power Down Mode 40 Software 40 Hardware Reset 40

Application 41
Ordering Information 77

Datasheet

LXT970A Dual-Speed Fast Ethernet Transceiver

Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
42 43
Block Diagram 9 Pin Assignments Network Interface Card NIC Application 18 MII Interface 20 MII Data Interface 21 Loopback Paths 23 Repeater Block Diagram 24 MDIO Interrupt Signaling 25 Management Interface - Read Frame Structure 25 Management Interface - Write Frame Structure 26 Initialization Sequence 30 Auto-Negotiation Operation 31 100BASE-TX Frame Structure 33 100BASE-TX Data Flow Protocol Sublayers 36 100BASE-TX Reception with No Errors 37 00BASE-TX Reception with Invalid Symbol 37 00BASE-TX Transmission with No Errors 37 00BASE-TX Transmission with Collision 37 Voltage Divider 45 Typical Interface Circuitry 46 MII - 100BASE-TX Receive Timing / 4B Mode 51 MII - 100BASE-TX Transmit Timing / 4B Mode 52 MII - 100BASE-TX Receive Timing / 5B Mode 53 100BASE-TX Transmit Timing / 5B Mode 54 MII - 100BASE-FX Receive Timing / 4B Mode 55 MII - 100BASE-FX Transmit Timing / 4B Mode 56 MII - 10BASE-T Receiving Timing 57 MII - 10BASE-T Transmit Timing 10BASE-T SQE Heartbeat Timing 59 10BASE-T Jab and Unjab Timing 59 Auto Negotiation and Fast Link Pulse Timing Fast Link Pulse Timing 60 MDIO Timing when Sourced by STA 61 MDIO Timing when Sourced by PHY 61 Power-Down Recovery Timing Over Recommended Range 62 PHY Identifier Bit Mapping 66 64-Pin QFP Package Diagram 73 64-Pin TQFP Package Diagram Sample TQFP Package FALXT970ATC Transceiver............................. 75 Sample Pb-Free RoHS-Compliant TQFP Package JALXT970ATC Transceiver75 Sample PQFP Package SLXT970AQC Transceiver 76 Sample Pb-Free RoHS-Compliant PQFP Package EGLXT970AQC Transceiver76 Ordering Information Matrix Sample 78

Datasheet

LXT970A Dual-Speed Fast Ethernet Transceiver

Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Power Supply Signal Descriptions 10 MII Signal Descriptions 11 Fiber Interface Signal Descriptions 12 Twisted-Pair Interface Signal Descriptions 13 LED Indicator Signal 13 Miscellaneous Signal 13 Hardware Control Interface Signal Descriptions 14 MF Pin Function Settings1, 3 16 Auto-Negotiation Operating Speed/Full-Duplex Advertisement Settings 17 Test Loopback Operation 23 Carrier Sense, Loopback, and Collision Conditions 23 Configuring the LXT970A Transceiver Via Hardware Control................... 26 Operating Configurations / Auto-Negotiation Enabled 26 Operating Configurations / Auto-Negotiation Disabled 27 Mode Control 29 Status using FDS/LED Pins 32 4B/5B Coding 34 Magnetics Requirements 41 Crystal 41 Crystal Component Manufacturers 41 Absolute Maximum Ratings 47 Operating Conditions 47 Digital I/O 48 Digital I/O Characteristics - MultiFunction Pins 48 Required Clock Characteristics 48 Low Voltage Fault Detect Characteristics 49 100BASE-TX Transceiver Characteristics 49 100BASE-FX Transceiver Characteristics 49 10BASE-T Transceiver 50 10BASE-T Link Integrity Timing Characteristics 50 MII - 100BASE-TX Receive Timing Parameters / 4B Mode 51 MII - 100BASE-TX Transmit Timing Parameters / 4B Mode 52 MII - 100BASE-TX Receive Timing Parameters / 5B Mode 53 MII - 100BASE-TX Transmit Timing Parameters / 5B Mode 54 MII - 100BASE-FX Receive Timing Parameters / 4B Mode 55 MII - 100BASE-FX Transmit Timing Parameters / 4B Mode 56 MII - 10BASE-T Receive Timing 57 MII - 10BASE-T Transmit Timing 58 10BASE-T SQE Heartbeat Timing Parameters 59 10BASE-T Jab and Unjab Timing 59 Auto Negotiation and Fast Link Pulse Timing 60 MDIO Timing Parameters 61 Power-Down Recovery Timing Parameters 62 Register Set 63 Control Register Address 64 Status Register Address 1 65 PHY Identification Register 1 Address 66 PHY Identification Register 2 Address 66 Auto Negotiation Advertisement Register Address 67

Datasheet

LXT970A Dual-Speed Fast Ethernet Transceiver
50 Auto Negotiation Link Partner Ability Register Address 5 51 Auto Negotiation Expansion Address 6 69 52 Mirror Register Address 16, Hex 53 Interrupt Enable Register Address 17, Hex 11 70 54 Interrupt Status Register Address 18, Hex 12 70 55 Configuration Register Address 19, Hex 71 56 Chip Status Register Address 20, Hex 14 72 57 Product Information 77

Datasheet

LXT970A Dual-Speed Fast Ethernet Transceiver

Date 25-Nov-2005

January 2001
Description Modified Figure 2 “Pin Assignments” on page Added Section “Top Label Markings” on page Added Table 57 “Product Information” on page Added Figure 44 “Ordering Information Matrix Sample” on page Initial Release.

Datasheet

LXT970A Dual-Speed Fast Ethernet Transceiver

Figure Block Diagram

MII TX

Hardware Interface

TX_EN

TX_ER

TXD<0:4>

TX_CLK MF<0:4> CFG<0:1>

FDE TRSTE RESET FDS /M DI NT

MDIO MDDIS

XTALI/O 2

RX_CLK

RXD<0:4> MII RX

CRS COL RX_DV RX_ER

PWR_DWN
10Mbps Loopback

Management/ Mode Select

Logic

Parallel to Serial Converter

Manchester Encoder

Scrambler 100 & Encoder

Auto Negotiation

Pulse Shaper

Crystal Osc & PLL

Carrier Sense Collision Detect

Data Valid Error Detect

Serial to Parallel Converter

Clock Generator

Manchester 10 Decoder

Decoder & Descrambler

Slicer

Baseline Wander Correction

Pw rD own / Line Energy

Monitor

ECL Driver

TP Driver

LED Drivers

FIBOP

FIBON
Ordering Information
Table 57 lists the LXT970A Transceiver product ordering information. Figure 44 provides the ordering information matrix.

Table Product Information

Intel Number FALXT970ATC.B11 JALXT970ATC.B11 SLXT970AQC.B11 EGLXT970AQC.B11

Package Type TQFP PQFP

Pin Count 64

RoHS Compliant No Yes No Yes

Datasheet

LXT970A Dual-Speed Fast Ethernet Transceiver
Figure 44 shows an order matrix with sample information for the LXT970A Transceiver. Figure Ordering Information Matrix Sample

LXT 970A Q

C B11

Temperature Range A = Ambient 0 550 C = Commercial 0 700 C E = Extended -40 850 C

Internal Package Designator L = LQFP P = PLCC N = DIP Q = PQFP H = QFP T = TQFP B = BGA C = CBGA E = TBGA K = HSBGA BGA with heat slug

Product Code = 3-5 Digit alphanumeric

IXA Product Prefix LXT = PHY layer device IXE = Switching engine IXF = Formatting device MAC/Framer IXP = Network processor

Intel Package Designator

B5426-01

Datasheet

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Datasheet ID: HR-4/3FAU(4.5AH)L5X2 638951