CDK2308AILP64

CDK2308AILP64 Datasheet


CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters Rev 2B

Part Datasheet
CDK2308AILP64 CDK2308AILP64 CDK2308AILP64 (pdf)
Related Parts Information
CDK2308CILP64 CDK2308CILP64 CDK2308CILP64
CDK2308DILP64 CDK2308DILP64 CDK2308DILP64
CDK2308BILP64 CDK2308BILP64 CDK2308BILP64
CDK2308DITQ64X CDK2308DITQ64X CDK2308DITQ64X
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Data Sheet

CDK2308

Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters

FEATURES n 10-bit resolution n 20/40/65/80MSPS maximum sampling rate n Ultra-low power dissipation 24/43/65/78mW n 61.6dB SNR at 80MSPS and 8MHz FIN n Internal reference circuitry n 1.8V core supply voltage n 1.7V 3.6V I/O supply voltage n Parallel CMOS output n 64-pin QFN package n Dual channel n Pin compatible with CDK2307

APPLICATIONS n Medical Imaging n Portable Test Equipment n Digital Oscilloscopes n IF Communication

The CDK2308 is a high performance, low power dual Analog-to-Digital Converters ADC . The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range.

Several idle modes with fast startup times exist. Each channel can independently be powered down and the entire chip can either be put in Standby Mode or Power Down mode. The different modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup.

The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs.

Functional Block Diagram

CLKP CLKN

CLK_EXT
Ordering Information

Speed Package

CDK2308AILP64 CDK2308BILP64
20MSPS QFN-64 40MSPS QFN-64

CDK2308CILP64 CDK2308DILP64
65MSPS QFN-64 80MSPS QFN-64

Moisture sensitivity level for all parts is MSL-2A.

Pb-Free Yes

RoHS Compliant Yes

Operating Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C

Packaging Method Tray

Exar Corporation 48720 Kato Road, Fremont CA 94538, USA

Tel. +1 510 668-7000 - Fax. +1 510 668-7001

Data Sheet

Pin Configuration QFN-64, TQFP-64
64 63 62 61 60 59 58 57 56 55 54 53 52 51 D0_5 50 D0_4 49 D0_3
1 2 3 4 5 6 7 8 9 10 11 12 DVSSCLK 13 DVDDCLK 14 CLKP 15 CLKN 16

CDK2308

QFN-64
48 47 46 45 N/C 44 N/C 43 N/C 42 CLK_EXT 41 40 39 38 37 36 35 34 33
17 18 CLK_EXT_EN 19 20 21 22 23 24 25 N/C 26 N/C 27 N/C 28 29 30 31 32

Pin Assignments

Pin No. 1, 18, 23
2 3, 9, 12 4, 5, 8
6, 7 10, 11
13 14 15 16 17, 64 19 20 21
22 24, 41, 58 25, 40, 57

Pin Name DVDD

CM_EXT AVDD AVSS

IP0, IN0 IP1, IN1 DVSSCLK DVDDCLK

CLKP CLKN DVSS CLK_EXT_EN DFRMT PD_N

OE_N_1 OVDD OVSS

Description Digital and I/O-ring pre driver supply voltage, 1.8V Common Mode voltage output Analog supply voltage, 1.8V Analog ground Analog input Channel 0 non-inverting, inverting Analog input Channel 1 non-inverting, inverting Clock circuitry ground Clock circuitry supply voltage, 1.8V Clock input, non-inverting Format LVDS, PECL, CMOS/TTL, Sine Wave Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground Digital circuitry ground CLK_EXT signal enabled when low zero . Tristate when high. Data format selection. 0 Offset Binary, 1 Two's Complement Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up, always apply Power Down mode before using Active mode to reset chip. Output Enable Channel Tristate when high I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V. Ground for I/O ring
2009-2013 Exar Corporation
2/15

Data Sheet

Pin Assignments Continued

Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 59
60, 61
62, 63

Pin Name Description
More datasheets: FAN7710VLN | 359 | AP3211HK-G1 | CY7C036AV-25AXC | CY7C036AV-20AC | FQB7P06TM | FQI7P06TU | CDK2308CILP64 | CDK2308DILP64 | CDK2308BILP64


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Datasheet ID: CDK2308AILP64 512893