S1D13A05B00B200

S1D13A05B00B200 Datasheet


S1D13A05

Part Datasheet
S1D13A05B00B200 S1D13A05B00B200 S1D13A05B00B200 (pdf)
PDF Datasheet Preview
GRAPHICS

S1D13A05

S1D13A05 LCD/USB Companion Chip

February 2012

The S1D13A05 utilizes a guaranteed low-latency CPU architecture that provides support for microprocessors without READY/WAIT# handshaking signals. The 32-bit internal data path, write buffer and the Hardware Acceleration Engine provide high performance bandwidth into display memory allowing for fast display updates.

Additionally, products requiring a rotated display can take advantage of the SwivelViewTM feature which provides hardware rotation of the display memory transparent to the software application. The S1D13A05 also provides support for “Picture-in-Picture Plus” a variable size Overlay window .

The S1D13A05, with its integrated USB client, provides impressive support for Palm handhelds. However, its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications.
n FEATURES
• Embedded 256KB Display Buffer.
• Low Operating Voltage.
• Low-latency CPU interface.
• Direct support for multiple CPU types.
• Programmable resolutions and color depths.
• Passive LCD support.
• Active Matrix LCD support.
• Extended TFT interfaces Type 2, 3,
• ‘Direct’ Sharp HR-TFT support including Mode
• ‘Direct’ Casio TFT support.
rotation of displayed image .
• Patent # 5,734,875 - Patent # 5,956,049 - Patent #6,262,751
• “Picture-in-Picture Plus”.
• Pixel Doubling.
• Hardware Acceleration Engine.
• Software Initiated Power Save Mode.
• 48MHz crystal for USBCLK.
• Software Video Invert.
• 121-pin PFBGA package.
n SYSTEM BLOCK DIAGRAM

Data and

Control Signals S1D13A05

LCD Panel

X40A-C-001-03

GRAPHICS S1D13A05
n DESCRIPTION

Memory Interface

Integrated LCD Controller Features
• Embedded 256K byte SRAM display buffer.
• 1/2/4/8/16 bit-per-pixel bpp support.

CPU Interface
• ‘Fixed’ low-latency CPU access times.
• Direct support for Hitachi SH-4 / SH-3. Motorola M68xxx REDCAP2, DragonBall, ColdFire . Motorola Dragonball SZ support 66MHz MPU bus interface with programmable READY.
• Up to 64 gray shades on monochrome passive panels.
• Up to 64K colors on passive/active matrix panels.
• Single-panel, single-drive passive displays.
• 4/8-bit monochrome and 4/8/16-bit color interfaces.
• 9/12/18-bit Active matrix TFT interface.
• ‘Direct support for multiple TFT interfaces Epson, Sharp, Type 2, 3, 4, external timing IC not required .

Power Down Modes
• Software Initiated Power Save Mode.
• SwivelView hardware rotation by 90°, 180°,
• “Picture-in-Picture Plus” displays a variable size window overlaid over background image.
• Pixel Doubling horizontal and vertical resolutions can be doubled without any additional memory.

Operating Voltage
• Software video invert.
• COREVDD ± 10% volts or ± 10% volts.
• IOVDD ± 10% volts.

Clock Source
• Three independent clock inputs including dedicated USB clock single clock possible if USB not required .
• 48MHz crystal oscillator for USBCLK.

Package
• 121-pin PFBGA
• Typical resolutions supported 160x160 2 pages 160x240
More datasheets: NIS5132MN2-FN-7 | 74LVQ138SC | 74LVQ138SCX | 74LVQ138SJX | 74LVQ138SJ | FDS3680 | DS-180 RT | B43501A5227M | FIT0452 | MB39A214APFT-G-JNERE1


Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived S1D13A05B00B200 Datasheet file may be downloaded here without warranties.

Datasheet ID: S1D13A05B00B200 511873