DLP-2232M-G

DLP-2232M-G Datasheet

DLP-2232M-G MODULE / EVALUATION KIT

Part	Datasheet
DLP-2232M-G	DLP-2232M-G (pdf)

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DLP-2232M-G MODULE / EVALUATION KIT LEAD-FREE Introduction The DLP-2232M-G utilizes FTDI's third-generation USB UART/FIFO I.C., the FT2232D. This low-cost development tool features two Multi-Purpose UART/FIFO controllers that can be configured individually in several different modes. In addition to the UART interface, FIFO interface, and Bit-Bang IO modes of the second-generation FT232BM and FT245BM devices, the FT2232D offers a variety of additional modes of operation including a Multi-Protocol Synchronous Serial Engine interface designed specifically for synchronous serial protocols such as JTAG and SPI bus. The DLP-2232M-G features a quality four-layer printed circuit board with a solid ground plane, an integral 93C56 EEPROM on board for easy OEM customization and a standard 40-pin, 0.6in wide footprint. Integral power control and on-board MOSFET power switch make the DLP-2232M-G a perfect choice for USB bus-powered, high-power designs as well as self- and low-powered products. DLP-2232M-G DLP Design, Inc. Features Summary • Single board, USB Dual Channel Serial / Parallel Ports with a variety of configurations • Entire USB protocol handled on-board. No USB-specific firmware programming required • DLP-USB232M-style UART interface option with full Handshaking & Modem interface signals • UART Interface supports 7/8 bit data, 1/2 stop bits, and Odd/Even/Mark/Space/No Parity • Transfer Data Rate 300 to 1 Mega Baud RS232 • Transfer Data Rate 300 to 3 Mega Baud TTL and RS422 / RS485 • Auto Transmit Enable control for RS485 serial applications using TXDEN pin • DLP-USB245M-style FIFO interface option with bi-directional data bus and simple 4wire handshake interface • Transfer Data Rate up to 1 MegaByte / Second • Enhanced Bit-Bang Mode interface option • New Synchronous Bit-Bang Mode interface option • New CPU-Style FIFO Interface Mode option • New Multi-Protocol Synchronous Serial Engine MPSSE interface option • New MCU Host Bus Emulation Mode option • New Fast Opto-Isolated Serial Interface Mode option • Interface mode and USB Description strings configurable in on-board EEPROM • EEPROM Configurable in-circuit via USB • Support for USB Suspend and Resume conditions via PWREN#, and SI/WUx pins • Support for bus powered, self powered, and high-power bus powered USB configurations • Integrated Power-On-Reset circuit, with optional Reset input and Reset Output pins • 5V and 3.3V logic IO Interfacing with independent level conversion on each channel • USB Bulk or Isochronous data transfer modes • 4.35V to 5.25V single supply operating voltage range • UHCI / OHCI / EHCI host controller compatible • USB Full Speed 12 Mbits / Second compatible • Standard 40-pin, 0.6in wide footprint VIRTUAL COM PORT VCP DRIVERS • Windows 98 / 98 SE / 2000 / ME / XP • Windows CE • MAC OS-8 and OS-9 • MAC OS-X • Linux and greater [ ** = In planning or under development ] D2XX Direct Drivers + DLL S/W • Windows 98 / 98 SE / 2000 / ME / XP APPLICATION AREAS • USB Dual Port RS232 Converters • USB Dual Port RS422 / RS485 • Upgrading Legacy Peripheral Designs • USB Instrumentation • USB JTAG Programming • USB to SPI Bus Interfaces • USB Industrial Control • Field Upgradeable USB Products • Galvanically Isolated Products With USB Interface DLP-2232M-G DLP Design, Inc. The DLP-2232M-G module is a USB interface that incorporates the functionality of two DLP-USB2xxM modules into a single 40-pin module. A single downstream USB port is converted to two IO channels that can each be individually configured as a DLPUSB232M-style UART interface, or a DLP-USB245M-style FIFO interface, without the need to add a USB hub. There are also several new modes which can be enabled in the external EEPROM, or by using DLL driver commands. These include Synchronous Bit-Bang Mode, a CPU-Style FIFO Interface Mode, a Multi-Protocol Synchronous Serial Engine Interface Mode, MCU Host Bus Emulation Mode, and Fast Opto-Isolated Serial Interface Mode. Additionally, a new high output drive level option means that the device UART / FIFO IO pins will drive out at around three times the normal power level, allowing the data bus to be shared by several devices. Classic BM-style Asynchronous Bit-Bang Mode is also supported, but has been enhanced to give the user access to the device’s internal RD# and WR# strobes. FTDI provides a royalty free Virtual Com Port VCP driver that makes the peripheral ports look like a standard COM port to the PC. Most existing software applications should be able interface with the Virtual Com Port simply by reconfiguring them to use the new ports created by the driver. Using the VCP drivers, an application programmer would communicate with the device in exactly the same way as they would a regular PC COM port - using the Windows VCOMM API calls or a COM port library. The FT2232D driver also incorporates the functions defined for FTDI’s D2XX drivers, allowing applications programmers to interface software directly to the device using a Windows DLL. DLP-2232M-G DLP Design, Inc. Features and Enhancements The DLP-2232M-G incorporates all of the enhancements introduced for the second generation DLP-USB232M and DLP-USB245M modules, summarized here: • Two Individually Configurable IO Channels Each of the DLP-2232M-G’s Channels A and B can be individually configured as a DLP-USB232M-style UART interface, or as a DL-USB245M-style FIFO interface. Additionally, these channels can be configured in a number of special IO modes. • Integrated Power-On-Reset POR circuit The module incorporates an internal POR function. A RESET# pin is available to allow external logic to reset the module where required, however for most applications this pin can simply be left disconnected as the RESET input to the FT2232D is pulled to VCC through a 47K resistor. A RSTOUT# pin is provided in order to allow the new POR circuit to provide a stable reset to external MCU and other devices. • Integrated level converter on UART / FIFO interface and control signals Each channel of the DLP-2232M-G has its own independent VCCIO pin that can be supplied by between 3V to 5V. This allows each channel’s output voltage drive level to be individually configured. Thus allowing, for example, 3.3V logic to be interfaced to the device without the need for external level converter I.C.’s. • Improved power management control for high-power USB Bus Powered devices The PWREN# pin of the FT2232D directly drives a P-Channel MOSFET for applications where power switching of external circuitry is required. The BM pull down enable feature configured in the external EEPROM is also retained. This will make the module gently pull down on the FIFO / UART IO lines when the power is shut off PWREN# is high . In this mode, any residual voltage on external circuitry is bled to GND when power is removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored. • Support for Isochronous USB Transfers Whilst USB Bulk transfer is usually the best choice for data transfer, the scheduling time of the data is not guaranteed. For applications where scheduling latency takes priority over data integrity such as transferring audio and low bandwidth video data, the DLP2232M-G offers the option of USB Isochronous transfer via configuration of bit in the EEPROM. • Send Immediate / Wake Up Signal Pin on each channel There is a Send Immediate / Wake Up SI/WU signal pin on each of the two channels. These combine two functions on one pin. If USB is in suspend mode and remote wakeup is enabled in the EEPROM , strobing this pin low will cause the device to request a resume from suspend WakeUp on the USB Bus. Normally, this can be used to wake up the Host PC. During normal operation, if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from the DLP-2232M-G DLP Design, Inc. drivers regardless of the packet size. This can be used to optimize USB transfer speed for applications that send small packets of data to the host PC. • Programmable Receive Buffer Timeout The TX buffer timeout is programmable over USB in 1ms increments from 1ms to 255ms, thus allowing the module to be better optimized for protocols requiring faster response times from short data packets. • Baud Rate Pre-Scaler Divisors The DLP-2232M-G UART mode baud rate pre-scaler supports division by n+0 , n+0.125 , n+0.25 , n+0.375 , n+0.5 , n+0.625 , n+0.75 and n+0.875 where n is an integer between 2 and • USB full speed option An EEPROM based option allows the DLP-2232M-G to return a USB device descriptor as opposed to USB Note The device would be a USB Full Speed device 12Mb/s as opposed to a USB High Speed device 480Mb/s . For more details on these features please see the FT232BM and FT245BM datasheets and application notes. In addition to the DLP-USB2xxM module features, the DLP-2232M-G incorporates the following new features and interface modes: • Enhanced Asynchronous Bit-Bang Interface The DLP-2232M-G supports FTDI’s BM chip Bit Bang mode. In Bit Bang mode, the eight FIFO data lines can be switched between FIFO interface mode and an 8-bit Parallel IO port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer equivalent to the baud rate prescaler . With the DLP-2232M-G module, this mode has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can be used to allow external logic to be clocked by accesses to the Bit-Bang IO bus. • Synchronous Bit-Bang Interface With Synchronous Bit-Bang Mode, the device is only read when it is written to, as opposed to asynchronously by the data rate generator. This makes it easier for the controlling program to measure the response to an output stimulus, as the data returned is synchronous to the output data. • High Output Drive Level Capability The IO interface pins can be made to drive out at 12 mA, instead of the normal 4 mA allowing multiple devices to be interfaced to the bus. DLP-2232M-G DLP Design, Inc. • CPU-Style FIFO Interface The CPU style FIFO interface is essentially the same function as the classic FT245 interface, however the bus signals have been redefined to make them easier to interface to a CPU bus. • Multi-Protocol Synchronous Serial Engine Interface M.P.S.S.E. The Multi-Protocol Synchronous Serial Engine MPSSE interface is a new option designed to interface efficiently with synchronous serial protocols such as JTAG and SPI Bus. It is very flexible in that it can be configured for different industry standards, or proprietary bus protocols. For instance, it is possible to connect one of the DLP-2232MG’s channels to an SRAM configurable FPGA as supplied by vendors such as Altera and Xilinx. The FPGA device would normally be un-configured i.e. have no defined function at power-up. Application software on the PC could use the MPSSE to download configuration data to the FPGA over USB. This data would define the hardware’s function and then, after the FPGA device is configured, the DLP-2232M-G can switch back into FIFO interface mode to allow the programmed FPGA device to communicate with the PC over USB. The other DLP-2232M-G channel would also be available for other devices. This approach would allow a customer to create a “generic” USB peripheral who’s hardware function can be defined under control of the application software. The FPGA based hardware could be easily upgraded or totally changed simply by changing the FPGA configuration data file. See the FTDI MORPH-IC or DLP-Design DLP-2232PB and DLP-2232SY development modules for practical examples • MCU Host Bus Emulation This new mode combines the ‘A’ and ‘B’ bus interface to make the DLP-2232M-G interface emulate a standard 8048 / 8051 style MCU bus. This allows peripheral devices for these MCU families to be directly attached to the DLP-2232M-G with IO being performed over USB with the help of MPSSE interface technology.

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DLP-2232M-G MODULE / EVALUATION KIT
*LEAD-FREE*

Introduction

The DLP-2232M-G utilizes FTDI's third-generation USB UART/FIFO I.C., the FT2232D. This low-cost development tool features two Multi-Purpose UART/FIFO controllers that can be configured individually in several different modes. In addition to the UART interface, FIFO interface, and Bit-Bang IO modes of the second-generation FT232BM and FT245BM devices, the FT2232D offers a variety of additional modes of operation including a Multi-Protocol Synchronous Serial Engine interface designed specifically for synchronous serial protocols such as JTAG and SPI bus.

The DLP-2232M-G features a quality four-layer printed circuit board with a solid ground plane, an integral 93C56 EEPROM on board for easy OEM customization and a standard 40-pin, 0.6in wide footprint. Integral power control and on-board MOSFET power switch make the DLP-2232M-G a perfect choice for USB bus-powered, high-power designs as well as self- and low-powered products.

DLP-2232M-G DLP Design, Inc.

Features Summary
• Single board, USB Dual Channel Serial / Parallel Ports with a variety of configurations
• Entire USB protocol handled on-board. No USB-specific firmware programming required
• DLP-USB232M-style UART interface option with full Handshaking & Modem interface signals
• UART Interface supports 7/8 bit data, 1/2 stop bits, and Odd/Even/Mark/Space/No Parity
• Transfer Data Rate 300 to 1 Mega Baud RS232
• Transfer Data Rate 300 to 3 Mega Baud TTL and RS422 / RS485
• Auto Transmit Enable control for RS485 serial applications using TXDEN pin
• DLP-USB245M-style FIFO interface option with bi-directional data bus and simple 4wire handshake interface
• Transfer Data Rate up to 1 MegaByte / Second
• Enhanced Bit-Bang Mode interface option
• New Synchronous Bit-Bang Mode interface option
• New CPU-Style FIFO Interface Mode option
• New Multi-Protocol Synchronous Serial Engine MPSSE interface option
• New MCU Host Bus Emulation Mode option
• New Fast Opto-Isolated Serial Interface Mode option
• Interface mode and USB Description strings configurable in on-board EEPROM
• EEPROM Configurable in-circuit via USB
• Support for USB Suspend and Resume conditions via PWREN#, and SI/WUx pins
• Support for bus powered, self powered, and high-power bus powered USB configurations
• Integrated Power-On-Reset circuit, with optional Reset input and Reset Output pins
• 5V and 3.3V logic IO Interfacing with independent level conversion on each channel
• USB Bulk or Isochronous data transfer modes
• 4.35V to 5.25V single supply operating voltage range
• UHCI / OHCI / EHCI host controller compatible
• USB Full Speed 12 Mbits / Second compatible
• Standard 40-pin, 0.6in wide footprint

VIRTUAL COM PORT VCP DRIVERS
• Windows 98 / 98 SE / 2000 / ME / XP
• Windows CE **
• MAC OS-8 and OS-9**
• MAC OS-X**
• Linux and greater** [ ** = In planning or under development ]

D2XX Direct Drivers + DLL S/W
• Windows 98 / 98 SE / 2000 / ME / XP

APPLICATION AREAS
• USB Dual Port RS232 Converters
• USB Dual Port RS422 / RS485
• Upgrading Legacy Peripheral Designs
• USB Instrumentation
• USB JTAG Programming
• USB to SPI Bus Interfaces
• USB Industrial Control
• Field Upgradeable USB Products
• Galvanically Isolated Products

With USB Interface

DLP-2232M-G DLP Design, Inc.

The DLP-2232M-G module is a USB interface that incorporates the functionality of two DLP-USB2xxM modules into a single 40-pin module. A single downstream USB port is converted to two IO channels that can each be individually configured as a DLPUSB232M-style UART interface, or a DLP-USB245M-style FIFO interface, without the need to add a USB hub.

There are also several new modes which can be enabled in the external EEPROM, or by using DLL driver commands. These include Synchronous Bit-Bang Mode, a CPU-Style FIFO Interface Mode, a Multi-Protocol Synchronous Serial Engine Interface Mode, MCU Host Bus Emulation Mode, and Fast Opto-Isolated Serial Interface Mode. Additionally, a new high output drive level option means that the device UART / FIFO IO pins will drive out at around three times the normal power level, allowing the data bus to be shared by several devices.

Classic BM-style Asynchronous Bit-Bang Mode is also supported, but has been enhanced to give the user access to the device’s internal RD# and WR# strobes.

FTDI provides a royalty free Virtual Com Port VCP driver that makes the peripheral ports look like a standard COM port to the PC. Most existing software applications should be able interface with the Virtual Com Port simply by reconfiguring them to use the new ports created by the driver. Using the VCP drivers, an application programmer would communicate with the device in exactly the same way as they would a regular PC COM port - using the Windows VCOMM API calls or a COM port library.

The FT2232D driver also incorporates the functions defined for FTDI’s D2XX drivers, allowing applications programmers to interface software directly to the device using a Windows DLL.

DLP-2232M-G DLP Design, Inc.

Features and Enhancements

The DLP-2232M-G incorporates all of the enhancements introduced for the second generation DLP-USB232M and DLP-USB245M modules, summarized here:
• Two Individually Configurable IO Channels Each of the DLP-2232M-G’s Channels A and B can be individually configured as a DLP-USB232M-style UART interface, or as a DL-USB245M-style FIFO interface. Additionally, these channels can be configured in a number of special IO modes.
• Integrated Power-On-Reset POR circuit The module incorporates an internal POR function. A RESET# pin is available to allow external logic to reset the module where required, however for most applications this pin can simply be left disconnected as the RESET input to the FT2232D is pulled to VCC through a 47K resistor. A RSTOUT# pin is provided in order to allow the new POR circuit to provide a stable reset to external MCU and other devices.
• Integrated level converter on UART / FIFO interface and control signals Each channel of the DLP-2232M-G has its own independent VCCIO pin that can be supplied by between 3V to 5V. This allows each channel’s output voltage drive level to be individually configured. Thus allowing, for example, 3.3V logic to be interfaced to the device without the need for external level converter I.C.’s.
• Improved power management control for high-power USB Bus Powered devices The PWREN# pin of the FT2232D directly drives a P-Channel MOSFET for applications where power switching of external circuitry is required. The BM pull down enable feature configured in the external EEPROM is also retained. This will make the module gently pull down on the FIFO / UART IO lines when the power is shut off PWREN# is high . In this mode, any residual voltage on external circuitry is bled to GND when power is removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored.
• Support for Isochronous USB Transfers Whilst USB Bulk transfer is usually the best choice for data transfer, the scheduling time of the data is not guaranteed. For applications where scheduling latency takes priority over data integrity such as transferring audio and low bandwidth video data, the DLP2232M-G offers the option of USB Isochronous transfer via configuration of bit in the EEPROM.
• Send Immediate / Wake Up Signal Pin on each channel There is a Send Immediate / Wake Up SI/WU signal pin on each of the two channels. These combine two functions on one pin. If USB is in suspend mode and remote wakeup is enabled in the EEPROM , strobing this pin low will cause the device to request a resume from suspend WakeUp on the USB Bus. Normally, this can be used to wake up the Host PC. During normal operation, if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from the

DLP-2232M-G DLP Design, Inc.
drivers regardless of the packet size. This can be used to optimize USB transfer speed for applications that send small packets of data to the host PC.
• Programmable Receive Buffer Timeout The TX buffer timeout is programmable over USB in 1ms increments from 1ms to 255ms, thus allowing the module to be better optimized for protocols requiring faster response times from short data packets.
• Baud Rate Pre-Scaler Divisors The DLP-2232M-G UART mode baud rate pre-scaler supports division by n+0 , n+0.125 , n+0.25 , n+0.375 , n+0.5 , n+0.625 , n+0.75 and n+0.875 where n is an integer between 2 and
• USB full speed option An EEPROM based option allows the DLP-2232M-G to return a USB device descriptor as opposed to USB Note The device would be a USB Full Speed device 12Mb/s as opposed to a USB High Speed device 480Mb/s . For more details on these features please see the FT232BM and FT245BM datasheets and application notes.

In addition to the DLP-USB2xxM module features, the DLP-2232M-G incorporates the following new features and interface modes:
• Enhanced Asynchronous Bit-Bang Interface The DLP-2232M-G supports FTDI’s BM chip Bit Bang mode. In Bit Bang mode, the eight FIFO data lines can be switched between FIFO interface mode and an 8-bit Parallel IO port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer equivalent to the baud rate prescaler . With the DLP-2232M-G module, this mode has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can be used to allow external logic to be clocked by accesses to the Bit-Bang IO bus.
• Synchronous Bit-Bang Interface With Synchronous Bit-Bang Mode, the device is only read when it is written to, as opposed to asynchronously by the data rate generator. This makes it easier for the controlling program to measure the response to an output stimulus, as the data returned is synchronous to the output data.
• High Output Drive Level Capability The IO interface pins can be made to drive out at 12 mA, instead of the normal 4 mA allowing multiple devices to be interfaced to the bus.

DLP-2232M-G DLP Design, Inc.
• CPU-Style FIFO Interface The CPU style FIFO interface is essentially the same function as the classic FT245 interface, however the bus signals have been redefined to make them easier to interface to a CPU bus.
• Multi-Protocol Synchronous Serial Engine Interface M.P.S.S.E. The Multi-Protocol Synchronous Serial Engine MPSSE interface is a new option designed to interface efficiently with synchronous serial protocols such as JTAG and SPI Bus. It is very flexible in that it can be configured for different industry standards, or proprietary bus protocols. For instance, it is possible to connect one of the DLP-2232MG’s channels to an SRAM configurable FPGA as supplied by vendors such as Altera and Xilinx. The FPGA device would normally be un-configured i.e. have no defined function at power-up. Application software on the PC could use the MPSSE to download configuration data to the FPGA over USB. This data would define the hardware’s function and then, after the FPGA device is configured, the DLP-2232M-G can switch back into FIFO interface mode to allow the programmed FPGA device to communicate with the PC over USB. The other DLP-2232M-G channel would also be available for other devices.

This approach would allow a customer to create a “generic” USB peripheral who’s hardware function can be defined under control of the application software. The FPGA based hardware could be easily upgraded or totally changed simply by changing the FPGA configuration data file. See the FTDI MORPH-IC or DLP-Design DLP-2232PB and DLP-2232SY development modules for practical examples
• MCU Host Bus Emulation This new mode combines the ‘A’ and ‘B’ bus interface to make the DLP-2232M-G interface emulate a standard 8048 / 8051 style MCU bus. This allows peripheral devices for these MCU families to be directly attached to the DLP-2232M-G with IO being performed over USB with the help of MPSSE interface technology.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DLP-2232M-G Datasheet file may be downloaded here without warranties.

Datasheet ID: DLP-2232M-G 510278