STK12C68-C35

STK12C68-C35 Datasheet

STK12C68

Part	Datasheet
STK12C68-C35	STK12C68-C35 (pdf)

Related Parts	Information
STK12C68-PF45I	STK12C68-PF45I
STK12C68-WF25	STK12C68-WF25
STK12C68-WF45I	STK12C68-WF45I
STK12C68-C45	STK12C68-C45
STK12C68-WF25I	STK12C68-WF25I
STK12C68-L45I	STK12C68-L45I
STK12C68-L35	STK12C68-L35
STK12C68-PF25	STK12C68-PF25
STK12C68-C35I	STK12C68-C35I
STK12C68-L35I	STK12C68-L35I
STK12C68-L45	STK12C68-L45
STK12C68-PF55	STK12C68-PF55

PDF Datasheet Preview
STK12C68 64 Kbit 8K x 8 AutoStore nvSRAM Functional Description • 25 ns, 35 ns, and 45 ns access times The Cypress STK12C68 is a fast static RAM with a nonvolatile • Hands off automatic STORE on power down with external 68 µF capacitor element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides • STORE to QuantumTrap nonvolatile elements is initiated by software, hardware, or AutoStore on power down • RECALL to SRAM initiated by software or power up unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down. On • Unlimited Read, Write, and Recall cycles power up, data is restored to the SRAM the RECALL operation ly. • 1,000,000 STORE cycles to QuantumTrap on • 100 year data retention to QuantumTrap ms • Single 5V+10% operation gra • Commercial and industrial temperatures pro • 228-pin 330mil SOIC, 28-pin 300mil PDIP, 28-pin 600mil n PDIP packages s. ctio • 28-pin 300 mil CDIP and 28-pad 350 mil LCC packages ign odu • RoHS compliance from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin. ROW DECODER New nDgeosing pr Logic Block Diagram ded foprport o A5 en su A6 m to A7 m n A8 eco tio A9 R uc A11 NoItn prod A12 Quantum Trap 128 X 512 STORE STATIC RAM ARRAY 128 X 512 RECALL VCAP POWER CONTROL STORE/ RECALL CONTROL SOFTWARE DETECT - A0 A12 COLUMN I/O INPUT BUFFERS DQ 1 DQ 2 COLUMN DEC A0 A1 A2 A3 A4 A10 CE WE • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback STK12C68 Contents Pin Configurations 3 DC Electrical Characteristics 8 Pin Definitions 3 Data Retention and Endurance 9 Device Operation 4 Part Numbering Nomenclature 17 Ordering Information 17 Package Diagrams 18 Document History Page 23 Sales, Solutions, and Legal Information 24 Worldwide Sales and Design Support 24 Products 24 Page 2 of 24 [+] Feedback Pin Configurations Figure 28-Pin SOIC/DIP and LLC STK12C68 igns. oduction programs only. Pin Definitions Des pr Pin Name Alt I/O Type ew oing r N ng DQ0-DQ7 ed fo port o WE Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. Input or Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation. Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. nd up CE mmen to s OE Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. eco ctio VSS t R du VCC NoIn pro HSB Ground for the Device. The device is connected to ground of the system. Power Supply Power Supply Inputs to the Device. Input or Output Hardware Store Busy HSB . When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected connection optional . VCAP Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. Page 3 of 24 [+] Feedback STK12C68 Device Operation The STK12C68 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to SRAM the RECALL operation . This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM Read and Write operations are inhibited. The STK12C68 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 2 shows the proper connection of the storage capacitor VCAP for automatic store operation. A charge storage capacitor between 68 µF and 220 µF +20% rated at 6V should be provided. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up is placed on WE to hold it inactive during power up. Figure AutoStore Mode SRAM Read only The STK12C68 performs a Read cycle whenever CE and OE are s LOW while WE and HSB are HIGH. The address specified on am pins determines the 8,192 data bytes accessed. When the r Read is initiated by an address transition, the outputs are valid rog after a delay of tAA Read cycle If the Read is initiated by CE p or OE, the outputs are valid at tACE or at tDOE, whichever is later n Read cycle The data outputs repeatedly respond to address tio changes within the tAA access time without the need for transins uc tions on any control input pins, and remains valid until another ig od address change or until CE or OE is brought HIGH, or WE or es pr HSB is brought LOW. w D ing SRAM Write Ne ngo A Write cycle is performed whenever CE and WE are LOW and for t o HSB is HIGH. The address inputs must be stable prior to entering d or the Write cycle and must remain stable until either CE or WE de pp goes HIGH at the end of the cycle. The data on the common I/O en su pins are written into the memory if it has valid tSD, before m to the end of a WE controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to com tion avoid data bus contention on common I/O lines. If OE is left LOW, e c internal circuitry turns off the output buffers tHZWE after WE goes R u LOW. NoItn prod AutoStore Operation In system power mode, both VCC and VCAP are connected to the +5V power supply without the 68 uF capacitor. In this mode, the AutoStore function of the STK12C68 operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the 10 ms The STK12C68 stores data to nvSRAM using one of three STORE cycle. storage operations Hardware store activated by HSB To reduce unnecessary nonvolatile stores, AutoStore, and Hardware Store operations are ignored, unless at least one Write New nDgeosiinggnsproduc Ordering Information for rt o These parts are not recommended for new designs. They are in production to support ongoing production programs only. ded ppo Speed ns Ordering Code en su 25 STK12C68-SF25TR m to STK12C68-SF25 com tion STK12C68-SF25ITR Re uc STK12C68-SF25I ot rod STK12C68-PF25I N In p STK12C68-WF25I Package Diagram 001-85058 001-85058 001-85058 001-85058 001-85014 001-85017 Package Type 28-pin SOIC 330 mil 28-pin SOIC 330 mil 28-pin SOIC 330 mil 28-pin SOIC 330 mil 28-pin PDIP 300 mil 28-pin PDIP 600 mil Operating Range Commercial Industrial STK12C68-C35 001-51695 28-pin CDIP 300 mil Commercial STK12C68-SF45TR 001-85058 28-pin SOIC 330 mil Commercial STK12C68-SF45 001-85058 28-pin SOIC 330 mil STK12C68-SF45ITR 001-85058 28-pin SOIC 330 mil Industrial STK12C68-SF45I 001-85058 28-pin SOIC 330 mil STK12C68-C45I 001-51695 28-pin CDIP 300 mil All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts Page 17 of 24 [+] Feedback Package Diagrams Figure 28-Pin 330 Mil SOIC 51-85058 STK12C68 programs only. 51-85058 *B Page 18 of 24 [+] Feedback Added following text in the Ordering Information section “These parts are not recommended for new designs. In production to support ongoing production programs only.” Added watermark in PDF stating “Not recommended for new designs. In production to support ongoing production programs only.” Added Contents on page 3054694 3189527 GVCH 10/12/2010 Removed the following prune parts from the document; ew designs. In Page 23 of 24 [+] Feedback STK12C68 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 \| PSoC 3 \| PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless programs only. Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 24 of 24 [+] Feedback

PDF Datasheet Preview

STK12C68
64 Kbit 8K x 8 AutoStore nvSRAM

Functional Description
• 25 ns, 35 ns, and 45 ns access times

The Cypress STK12C68 is a fast static RAM with a nonvolatile
• Hands off automatic STORE on power down with external 68 µF capacitor
element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides
• STORE to QuantumTrap nonvolatile elements is initiated by software, hardware, or AutoStore on power down
• RECALL to SRAM initiated by software or power up
unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down. On
• Unlimited Read, Write, and Recall cycles
power up, data is restored to the SRAM the RECALL operation
ly.
• 1,000,000 STORE cycles to QuantumTrap on
• 100 year data retention to QuantumTrap ms
• Single 5V+10% operation gra
• Commercial and industrial temperatures pro
• 228-pin 330mil SOIC, 28-pin 300mil PDIP, 28-pin 600mil
n PDIP packages s. ctio
• 28-pin 300 mil CDIP and 28-pad 350 mil LCC packages ign odu
• RoHS compliance
from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin.

ROW DECODER

New nDgeosing pr Logic Block Diagram ded foprport o A5 en su A6 m to A7 m n A8 eco tio A9 R uc A11 NoItn prod A12

Quantum Trap 128 X 512

STORE

STATIC RAM ARRAY 128 X 512

RECALL

VCAP

POWER CONTROL

STORE/ RECALL CONTROL

SOFTWARE DETECT
- A0 A12

COLUMN I/O

INPUT BUFFERS

DQ 1 DQ 2

COLUMN DEC

A0 A1 A2 A3 A4 A10

CE WE
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

STK12C68

Contents

Pin Configurations 3

DC Electrical Characteristics 8

Pin Definitions 3

Data Retention and Endurance 9

Device Operation 4
Part Numbering Nomenclature 17 Ordering Information 17 Package Diagrams 18 Document History Page 23 Sales, Solutions, and Legal Information 24

Worldwide Sales and Design Support 24 Products 24

Page 2 of 24 [+] Feedback

Pin Configurations

Figure 28-Pin SOIC/DIP and LLC

STK12C68
igns. oduction programs only. Pin Definitions

Des pr Pin Name Alt I/O Type
ew oing r N ng DQ0-DQ7
ed fo port o WE

Input

Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

Input or Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.

Input

Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
nd up CE
mmen to s OE

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
eco ctio VSS t R du VCC NoIn pro HSB

Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Input or Output Hardware Store Busy HSB . When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected connection optional .

VCAP

Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements.

Page 3 of 24 [+] Feedback

STK12C68

Device Operation

The STK12C68 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to SRAM the RECALL operation . This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM Read and Write operations are inhibited. The STK12C68 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations.

During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 2 shows the proper connection of the storage capacitor VCAP for automatic store operation. A charge storage capacitor between 68 µF and 220 µF +20% rated at 6V should be provided. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up is placed on WE to hold it inactive during power up.

Figure AutoStore Mode

SRAM Read only The STK12C68 performs a Read cycle whenever CE and OE are s LOW while WE and HSB are HIGH. The address specified on am pins determines the 8,192 data bytes accessed. When the r Read is initiated by an address transition, the outputs are valid rog after a delay of tAA Read cycle If the Read is initiated by CE p or OE, the outputs are valid at tACE or at tDOE, whichever is later n Read cycle The data outputs repeatedly respond to address tio changes within the tAA access time without the need for transins uc tions on any control input pins, and remains valid until another ig od address change or until CE or OE is brought HIGH, or WE or es pr HSB is brought LOW. w D ing SRAM Write Ne ngo A Write cycle is performed whenever CE and WE are LOW and for t o HSB is HIGH. The address inputs must be stable prior to entering d or the Write cycle and must remain stable until either CE or WE de pp goes HIGH at the end of the cycle. The data on the common I/O en su pins are written into the memory if it has valid tSD, before m to the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
com tion avoid data bus contention on common I/O lines. If OE is left LOW, e c internal circuitry turns off the output buffers tHZWE after WE goes R u LOW. NoItn prod AutoStore Operation

In system power mode, both VCC and VCAP are connected to the +5V power supply without the 68 uF capacitor. In this mode, the AutoStore function of the STK12C68 operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the 10 ms

The STK12C68 stores data to nvSRAM using one of three STORE cycle.
storage operations Hardware store activated by HSB

To reduce unnecessary nonvolatile stores, AutoStore, and Hardware Store operations are ignored, unless at least one Write
New nDgeosiinggnsproduc Ordering Information
for rt o These parts are not recommended for new designs. They are in production to support ongoing production programs only.
ded ppo Speed ns
Ordering Code
en su 25

STK12C68-SF25TR
m to STK12C68-SF25
com tion STK12C68-SF25ITR

Re uc STK12C68-SF25I
ot rod STK12C68-PF25I

N In p STK12C68-WF25I

Package Diagram 001-85058 001-85058 001-85058 001-85058 001-85014 001-85017

Package Type 28-pin SOIC 330 mil 28-pin SOIC 330 mil 28-pin SOIC 330 mil 28-pin SOIC 330 mil 28-pin PDIP 300 mil 28-pin PDIP 600 mil

Operating Range Commercial

Industrial

STK12C68-C35
001-51695
28-pin CDIP 300 mil

Commercial

STK12C68-SF45TR
001-85058
28-pin SOIC 330 mil

Commercial

STK12C68-SF45
001-85058
28-pin SOIC 330 mil

STK12C68-SF45ITR
001-85058
28-pin SOIC 330 mil

Industrial

STK12C68-SF45I
001-85058
28-pin SOIC 330 mil

STK12C68-C45I
001-51695
28-pin CDIP 300 mil

All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts

Page 17 of 24 [+] Feedback

Package Diagrams

Figure 28-Pin 330 Mil SOIC 51-85058

STK12C68
programs only.
51-85058 *B

Page 18 of 24 [+] Feedback
Added following text in the Ordering Information section “These parts are not recommended for new designs. In production to support ongoing production programs only.” Added watermark in PDF stating “Not recommended for new designs. In production to support ongoing production programs only.” Added Contents on page
3054694
3189527

GVCH
10/12/2010 Removed the following prune parts from the document;
ew designs. In

Page 23 of 24 [+] Feedback

STK12C68

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF

PSoC Solutions
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks

PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless
programs
only.

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 24 of 24
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived STK12C68-C35 Datasheet file may be downloaded here without warranties.

Datasheet ID: STK12C68-C35 508336