S29WS256R0SBHW000

S29WS256R0SBHW000 Datasheet

S29WS512R, S29WS256R, S29WS128R

Part	Datasheet
S29WS256R0SBHW000	S29WS256R0SBHW000 (pdf)

Related Parts	Information
S29WS512R0SBHW200	S29WS512R0SBHW200
S29WS512R0SBHW000	S29WS512R0SBHW000
S29WS256RAABHW000	S29WS256RAABHW000

PDF Datasheet Preview
"Spansion, Inc." and "Cypress Semiconductor Corp." have merged together to deliver high-performance, high-quality solutions at the heart of today's most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices. The new company "Cypress Semiconductor Corp." will continue to offer "Spansion, Inc." products to new and existing customers. Continuity of Specifications There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future S29WS512R, S29WS256R, S29WS128R 512/256/128 Mb 32/16/8M x 16 bit V S29WS-R Flash This product family has been retired and is not recommended for designs. For new and current designs, S29WS512P, S29WS256P, and S29WS128P supersedes S29WS512R, S29WS256R, and S29WS128R respectively. This is the factoryrecommended migration path. Please refer to the S29WS-P data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. 65 nm MirrorBit Technology 100,000 cycles per sector typical Single supply V read/program/erase V 10-year data retention typical Wireless Temperature range -25°C to +85°C Data Protection 16-bit Word data bus width Simultaneous Read/Write SRW operation ign Read from one bank while programming or erasing in another bank s Memory array is divided into 16 equal size banks e Programmable linear 8/16 with wrap around and continuos burst D read modes w RDY output for data transfer flow control e Sector Erase N Four 32 Kbyte sectors at top or bottom of memory array r All other sectors are 128 Kbytes fo Write Buffer Programming up to 64 -byte groups Optional acceleration voltage supply ACC to reduce factory d programming time e Suspend and Resume commands for Program and Erase d operations n Write operation status register bits indicate program and erase e operation completion Not Recomm Program-Erase Endurance Low VCC write inhibit Secured Silicon Sector 512 Bytes of Secured Silicon Sector region consisting of One Time Program OTP area of 256 bytes each for factory and customer Hardware Sector Protection via ACC pin All sectors protected when ACC input is at VIL Boot code controlled sector protection A range of sectors may be protected to prevent program and erase until the next hardware reset or power is removed from the device Dynamic sector protection All sectors are unprotected at power on for simplified system production test & programming A single command is used to protect all sectors from program or erase A single sector at a time may be unprotected by a command to enable programming or erase. Common Flash Interface CFI data structure Offered Packages 512/256/128R 84-ball FBGA 11.6mm x 8mm VBH084 • San Jose, CA 95134-1709 • 408-943-2600 S29WS512R, S29WS256R, S29WS128R Performance Characteristics Read Access Times maximum values Speed Option MHz Synch. Internal Access, ns tIA Synch. Burst Access, ns tBACC Asynch. Access Time, ns tACC Current Consumption typical values Burst Read 104 MHz ICCB 32 mA Simultaneous Operation 104 MHz ICC5 52 mA Program ICC2 20 mA Erase ICC2 20 mA Standby Mode ICC3 20 µA ign Typical Program & Erase Times typical values s Effective Write Buffer Programming VCC Per Word e Effective Write Buffer Programming VACC Per Word D Sector Erase 32 KByte Sector VCC Not Recommended for New Sector Erase 128 KByte Sector VCC µs 8 µs Ordering Information 5 Valid Combinations 5 SSR 44 Secure Silicon 44 Input/Output Descriptions & Logic Symbol 6 Block 7 Power Conservation 46 Standby 46 Automatic Sleep 46 Physical Dimensions/Connection Diagrams............. 7 Output Disable 46 Related Documents 7 Electrical 47 Special Handling Instructions for FBGA Package.......... 7 n Connection Diagrams and Physical Dimensions 8 ig Product Overview 10 es Address Space Maps 10 D Data Address & Quantity Nomenclature 11 Flash Memory 12 w Device ID and CFI 21 e Device Operations 23 N Device Bus Operations 24 r Asynchronous 24 fo Page Mode Read 25 d Synchronous Burst Read Mode and Configuration e 25 d Status Register 31 n Blank 34 e Simultaneous Read/Write 35 m Writing Commands/Command Sequences.................. 35 Program/Erase Operations 35 m Handshaking 41 o Hardware Reset 42 Not Rec Software Reset 42 Absolute Maximum Ratings 47 Operating 47 DC Characteristics 48 Capacitance 49 AC Test Conditions 49 Key to Switching Waveforms 50 VCC Power 50 CLK 51 AC Characteristics 52 Appendix 63 Command 63 Device ID and Common Flash Memory Interface Address 65 Page 4 of 77 S29WS512R S29WS256R, S29WS128R The Spansion S29WS512/256/128R are Mirrorbit flash products fabricated on 65 nm process technology. These burst mode flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. These products can operate up to 104 MHz and use a single VCC of V to V that makes them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered power consumption. Ordering Information This product family has been retired and is not recommended for designs. For new and current designs, S29WS512P, S29WS256P, and S29WS128P supersedes S29WS512R, S29WS256R, and S29WS128R respectively. This is the factory-recommended migration path. Please refer to the S29WS-P data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. The order number is formed by a valid combinations of the following: S29WS n 0P BH W 00 0 ig Packing Type s 0 = Tray standard see note 1 e 2 = 7-inch Tape and Reel D 3 = 13-inch Tape and Reel Model Number w Boot Configuration Options e 00 = Uniform, 1 CE N 20 = Top Boot, 1 CE r Temperature Range fo W = Wireless to +85C Package Type And Material d BH = Very Thin Fine-Pitch BGA, Low-Halogen Lead Pb -free Package e Speed Option Burst Frequency d 0P = 66 MHz n 0S = 83 MHz eAA = 104 MHz mProcess Technology R = 65 nm MirrorBit Technology m Flash Density o 512 =512 Mb c 256 =256 Mb e 128 =128 Mb R Device Family Not S29WS Volt-only Simultaneous Read/Write, Burst Mode Flash Memory Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29WS-R Valid Combinations Notes 1, 2 Base Ordering Part Number S29WS512R S29WS256R S29WS128R Speed Option Package Type, Material, & Temperature Range 0P, 0S, AA BHW Low-Halogen, Lead Pb -free Packing Type 0, 2, 3 Note 1 Model Numbers 00, 20 Package Type Note 2 mm x 8 mm 84-ball MCP-Compatible Notes Type 0 is standard. Specify other options as required. BGA package marking omits leading S29 and packing type designator from ordering part number. Product Status Advance Page 5 of 77 S29WS512R S29WS256R, S29WS128R Input/Output Descriptions & Logic Symbol Table identifies the input and output package connections provided on the device. Table Input/Output Descriptions Symbol Amax A0 DQ15 DQ0 F1-CE# F2-CE# OE# WE# VCC VCCQ VSS NC RDY AVD# RESET# Type Input I/O Input Input Supply No Connect Output Input Input Input Input Reserved Higher order address lines. Amax = A24 for WS512R, A23 for WS256R, A22 for WS128R Data input/output Flash-1 Chip Enable. Asynchronous relative to CLK. Used to select the first portion of the flash device address space that can be directly selected by one host chip enable signal. Flash-2 Chip Enable. Asynchronous relative to CLK. Used to select the first portion of the flash device address space that can be directly selected by one host chip enable signal. Output Enable. Asynchronous relative to CLK for the Burst mode Write Enable ign Device Power Supply s Input/Output Power Supply must be ramped simultaneously with VCC e Ground D No Connected internally Ready. Indicates when valid burst data is ready to be read ew The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal N address counter. CLK should remain low during asynchronous access r Address Valid input. Indicates to device that the valid address is present on the address inputs. fo VIL = for asynchronous mode, indicates valid address for burst mode, cause staring address to be latched on rising edge of CLK. d VIH = device ignores address inputs e Hardware Reset. Low = device resets and returns to reading array data. d Accelerated input. n At VIL,disables all program and erase functions. e Should be at VIH for all other conditions. Not Recomm Reserved for future use Page 6 of 77 S29WS512R S29WS256R, S29WS128R Block Diagrams VCC VSS VCCQ Figure Simultaneous Operation Circuit Latches and Control Logic Bank Address Y-Decoder Bank 0 X-Decoder Effective Write Buffer Programming VACC Per Byte Typical Program & Erase Time Product Ordering Information Valid Combination Table Changed Typical value from µs to 6 µs n Change Sector Erase 32 KByte Sector from 0.3s to 0.355s ig Added package, boot configuration and frequency information to ordering information s Removed WS2901GR De Added model # 00 and 02 for boot configuration Block Diagram ew Input/Output Descriptions & Logic r N Pin Out Diagram fo Synchronous Read Wait State Table ed DC Characterization mend AC Characterization com Product Overview Re Synchronous Burst Read Mode Not VCC Power Up Renamed VPP to ACC Removed A/D mux from I/O description Removed Address multiplexing wording from AVD# Removed WP# pin Reformatted the frequency description Added 83 MHz value for ICCB and ICC5 Changed all 108 MHz to 104 MHz Changed VLKO Min/Max from 1.3V/1.4V to 1.0V/1.1V Synchronous Burst Changed tBDH min from 5 ns for 66 MHz/83 MHz to 3 ns, ns for 108 MHz/ 133 Mhz to 2 ns for 104 Mhz/133 MHz Asynchronous Read Changed tWEA from 4 ns to tCLK Asyncronous Write Change tESL and tPSL from 20 µs to 30 µs Added note 3 on AVD requirement to subsequent CLK cycle Corrected Secure Silicon Region size to 512 Bytes Deleted wait state 2 from Wait State Tables Figure Changed 256 Byte Boundary Crossing Latency additional wait states up to 2 Changed tVCS value to 300 µs Changed VIOS value to 300 µs Added tRPH to timing diagram Wait State Configuration Register Setup Corrected typo in table to wait state 13 Device ID and CFI Table General update CFI values Device ID and Common Flash Memory Interface Table Corrected CFI setting for 4Ah Removed 133 MHz speed option Ordering Information & Valid Combination Table Flash Memory Array Table Device Bus Operation Added Low-Halogen Lead Free package option Removed Standard Lead Free package option Updated table to correct sector range for bank 16 of S29WS512R Deleted Asynchronous Write WE# latched Address Page 71 of 77 S29WS512R S29WS256R, S29WS128R Section Write Buffer Programming Command Changed to word offset AC Characterization Program/Erase Operation Changed Clock High or Low time tCLK H/L to tCLK Deleted Programming of a previously programmed location Deleted ACC mode from single word programming Changed 32-word buffer programming performance VCC mode 400 µs, ACC mode to 256 µs Change Chip Programming Time for VCC mode as below: • 128 Mbit 105s typical 210s max • 256 Mbit 210s typical 420s max • 512 Mbit 420s typical 840s max Changed sector erase time as follows: • 128 Kbyte VCC Note 6 typ , max Program and Erase Performance • 32 Kbyte VCC Note 6 typ , max n • 128 Kbyte ACC Note 6 typ , max ig • 32 Kbyte ACC Note 6 typ , max Updated chip erase time both VCC and VPP as follows: es • WS128R 78/126 s typ , 154/250 s max D • WS256R 155/251 s typ , 308/500 s max Global Combinations t R Input/Output Descriptions & Logic o Symbol N VCC Power Up • WS512R 308/500 s typ , 612/998 s max Added Note 6 to state, The first value is excluding pre-programming time, while the second value is inclusive of pre-programming for the FFFFh pattern, with status polling rate as 400 ns typ . Added Note 7 to state, The erase time is calculated from the time of issuing erase command to the completion of erase operation indicated by status register . Remove 1G product option Add additional model numbers for uniform boot, 1 and 2CEs Blank Check Command functional in Asynchronous Read Mode only Change ICCB for 83 MHz 16word burst to 26 mA Effect Word Programming time using Write Buffer change to µs for VCC mode and 8 µs for ACC mode Removed model numbers 10, 30, 50 Input/Output Descriptions table Updated ACC description Removed tRH from table Device ID and Common Flash Memory Interface Address Map ID/CFI Data table Updated SA + 51h description Sector Lock Range Command Clarified Sector Lock Range command behavior Global Added product obsolescence information Page 72 of 77 S29WS512R S29WS256R, S29WS128R Document History Page Document Title S29WS512R, S29WS256R, S29WS128R 512/256/128 Mb 32/16/8M x 16 bit , V, S29WS-R Flash Document Number 002-01101 ECN No. Orig. of Change WIOB WIOB Submission Date Description of Change 03/28/2007 Initial release 04/24/2007 Device ID and Common Flash Memory Interface Address Map Updated device ID for word offset 03H to 00FFh Effective Write Buffer Programming VCC Per Byte Changed Typical value from 4.7µs to µs Effective Write Buffer Programming VACC Per Byte Changed Typical value from µs to 6 µs Not Recommended for New Design WIOB Typical Program & Erase Time Change Sector Erase 32 KByte Sector from 0.3s to 0.355s Product Ordering Information Added package, boot configuration and frequency information to ordering information Valid Combination Table Removed WS2901GR Added model # 00 and 02 for boot configuration Block Diagram Renamed VPP to ACC Input/Output Descriptions & Logic Symbol Removed A/D mux from I/O description Removed Address multiplexing wording from AVD# 03/19/2008 Pin Out Diagram Removed WP# pin Synchronous Read Wait State Table Reformatted the frequency description DC Characterization Added 83 MHz value for ICCB and ICC5 Changed all 108 MHz to 104 MHz Changed VLKO Min/Max from 1.3V/1.4V to 1.0V/1.1V AC Characterization Synchronous Burst Changed tBDH min from 5 ns for 66 MHz/83 MHz to 3 ns, ns for 108 MHz/133 Mhz to 2 ns for 104 Mhz/133 MHz Asynchronous Read Changed tWEA from 4 ns to tCLK Asyncronous Write Change tESL and tPSL from 20 µs to 30 µs Added note 3 on AVD requirement to subsequent CLK cycle Product Overview Corrected Secure Silicon Region size to 512 Bytes Synchronous Burst Read Mode Deleted wait state 2 from Wait State Tables Figure 7.1Changed 256 Byte Boundary Crossing Latency additional wait states up to 2 VCC Power Up Changed tVCS value to 300 µs Changed VIOS value to 300 µs Added tRPH to timing diagram Wait State Configuration Register Set-up Corrected typo in table to wait state 13 WIOB 03/25/2008 Device ID and Common Flash Memory Interface Table Corrected CFI setting for 4Ah Page 73 of 77 S29WS512R S29WS256R, S29WS128R Document History Page Continued Document Title S29WS512R, S29WS256R, S29WS128R 512/256/128 Mb 32/16/8M x 16 bit , V, S29WS-R Flash Document Number 002-01101 ECN No. Orig. of Submission Change Description of Change Global Removed 133 MHz speed option Ordering Information & Valid Combination Table Added Low-Halogen Lead Free package option Removed Standard Lead Free package option Flash Memory Array Updated table to correct sector range for bank 16 of S29WS512R Table Device Bus Operation Deleted Asynchronous Write WE# latched Address Not Recommended for New Design WIOB 10/27/2008 Write Buffer Programming Command Changed to word offset AC Characterization Changed Clock High or Low time tCLK H/L to tCLK Program/Erase Operation Deleted Programming of a previously programmed location Program and Erase Performance Deleted ACC mode from single word programming Changed 32-word buffer programming performance VCC mode 400 µs, ACC mode to 256 µs Change Chip Programming Time for VCC mode as below • 128 Mbit 105s typical 210s max • 256 Mbit 210s typical 420s max • 512 Mbit 420s typical 840s max Changed sector erase time as follows: • 128 Kbyte VCC Note 6 typ , max • 32 Kbyte VCC Note 6 typ , max • 128 Kbyte ACC Note 6 typ , max • 32 Kbyte ACC Note 6 typ , max Updated chip erase time both VCC and VPP as follows: • WS128R 78/126 s typ , 154/250 s max • WS256R 155/251 s typ , 308/500 s max • WS512R 308/500 s typ , 612/998 s max Added Note 6 to state, The first value is excluding pre-programming time, while the second value is inclusive of pre-programming for the FFFFh pattern, with status polling rate as 400 ns typ . Added Note 7 to state, The erase time is calculated from the time of issuing erase command to the completion of erase operation indicated by status reg- ister . Global Remove 1G product option Ordering Information and Valid Combinations Add additional model numbers for uniform boot, 1 and 2CEs WIOB 02/27/2009 Device Operation Blank Check Command functional in Asynchronous Read Mode only DC Characteristics Change ICCB for 83 MHz 16word burst to 26 mA Programming Performance Effect Word Programming time using Write Buffer change to µs for VCC mode and 8 µs for ACC mode Ordering Information and Valid Combinations Removed model numbers 10, 30, 50 Input/Output Descriptions & Logic Symbol Input/Output Descriptions table WIOB 05/07/2009 Updated ACC description VCC Power Up Removed tRH from table Device ID and Common Flash Memory Interface Address Map ID/CFI Data table Updated SA + 51h description Page 74 of 77 S29WS512R S29WS256R, S29WS128R Document History Page Continued Document Title S29WS512R, S29WS256R, S29WS128R 512/256/128 Mb 32/16/8M x 16 bit , V, S29WS-R Flash Document Number 002-01101 G H ECN No. Orig. of Change WIOB WIOB Submission Date Description of Change 06/01/2011 Sector Lock Range Command Clarified Sector Lock Range command behavior 18/19/2011 Global Added product obsolescence information 4953774 WIOB 10/09/2015 Updated to Cypress template. Design Not Recommended for New Page 75 of 77 S29WS512R S29WS256R, S29WS128R Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Solutions psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP cypress.com/go/interface Cypress Developer Community Lighting & Power Control............ cypress.com/go/powerpsoc Community \| Forums \| Blogs \| Video \| Training cypress.com/go/memory PSoC Touch Sensing cypress.com/go/touch USB Wireless/RF cypress.com/go/wireless Technical Support Design cypress.com/go/support Not Recommended for New Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

PDF Datasheet Preview

"Spansion, Inc." and "Cypress Semiconductor Corp." have merged together to deliver high-performance, high-quality solutions at the heart of today's most advanced embedded systems, from automotive, industrial and networking platforms to highly interactive consumer and mobile devices. The new company "Cypress Semiconductor Corp." will continue to offer "Spansion, Inc." products to new and existing customers.

Continuity of Specifications There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future
S29WS512R, S29WS256R, S29WS128R
512/256/128 Mb 32/16/8M x 16 bit V S29WS-R Flash
This product family has been retired and is not recommended for designs. For new and current designs, S29WS512P, S29WS256P, and S29WS128P supersedes S29WS512R, S29WS256R, and S29WS128R respectively. This is the factoryrecommended migration path. Please refer to the S29WS-P data sheet for specifications and ordering information.

Availability of this document is retained for reference and historical purposes only.
65 nm MirrorBit Technology
100,000 cycles per sector typical

Single supply V read/program/erase V
10-year data retention typical

Wireless Temperature range -25°C to +85°C

Data Protection
16-bit Word data bus width Simultaneous Read/Write SRW operation
ign Read from one bank while programming or erasing in another bank
s Memory array is divided into 16 equal size banks e Programmable linear 8/16 with wrap around and continuos burst D read modes w RDY output for data transfer flow control e Sector Erase N Four 32 Kbyte sectors at top or bottom of memory array r All other sectors are 128 Kbytes fo Write Buffer Programming up to 64 -byte groups

Optional acceleration voltage supply ACC to reduce factory
d programming time e Suspend and Resume commands for Program and Erase d operations n Write operation status register bits indicate program and erase e operation completion Not Recomm Program-Erase Endurance

Low VCC write inhibit Secured Silicon Sector
512 Bytes of Secured Silicon Sector region consisting of One Time Program OTP area of 256 bytes each for factory and customer

Hardware Sector Protection via ACC pin All sectors protected when ACC input is at VIL

Boot code controlled sector protection A range of sectors may be protected to prevent program and erase until the next hardware reset or power is removed from the device

Dynamic sector protection All sectors are unprotected at power on for simplified system production test & programming A single command is used to protect all sectors from program or erase A single sector at a time may be unprotected by a command to enable programming or erase.

Common Flash Interface CFI data structure

Offered Packages 512/256/128R 84-ball FBGA 11.6mm x 8mm VBH084
• San Jose, CA 95134-1709
• 408-943-2600

S29WS512R, S29WS256R, S29WS128R

Performance Characteristics

Read Access Times maximum values

Speed Option MHz

Synch. Internal Access, ns tIA

Synch. Burst Access, ns tBACC

Asynch. Access Time, ns tACC

Current Consumption typical values

Burst Read 104 MHz ICCB
32 mA

Simultaneous Operation 104 MHz ICC5
52 mA

Program ICC2
20 mA

Erase ICC2
20 mA

Standby Mode ICC3
20 µA
ign Typical Program & Erase Times typical values s Effective Write Buffer Programming VCC Per Word e Effective Write Buffer Programming VACC Per Word D Sector Erase 32 KByte Sector VCC Not Recommended for New Sector Erase 128 KByte Sector VCC
µs 8 µs
Ordering Information 5 Valid Combinations 5

SSR 44 Secure Silicon 44

Input/Output Descriptions & Logic Symbol 6 Block 7

Power Conservation 46

Standby 46 Automatic Sleep 46

Physical Dimensions/Connection Diagrams............. 7 Output Disable 46

Related Documents 7 Electrical 47

Special Handling Instructions for FBGA Package.......... 7
n Connection Diagrams and Physical Dimensions 8 ig Product Overview 10 es Address Space Maps 10 D Data Address & Quantity Nomenclature 11

Flash Memory 12
w Device ID and CFI 21 e Device Operations 23 N Device Bus Operations 24 r Asynchronous 24 fo Page Mode Read 25 d Synchronous Burst Read Mode and Configuration
e 25 d Status Register 31 n Blank 34 e Simultaneous Read/Write 35 m Writing Commands/Command Sequences.................. 35

Program/Erase Operations 35
m Handshaking 41 o Hardware Reset 42 Not Rec Software Reset 42

Absolute Maximum Ratings 47 Operating 47 DC Characteristics 48 Capacitance 49 AC Test Conditions 49 Key to Switching Waveforms 50 VCC Power 50 CLK 51 AC Characteristics 52

Appendix 63 Command 63 Device ID and Common Flash Memory Interface

Address 65

Page 4 of 77

S29WS512R S29WS256R, S29WS128R

The Spansion S29WS512/256/128R are Mirrorbit flash products fabricated on 65 nm process technology. These burst mode flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. These products can operate up to 104 MHz and use a single VCC of V to V that makes them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered power consumption.
Ordering Information
This product family has been retired and is not recommended for designs. For new and current designs, S29WS512P, S29WS256P, and S29WS128P supersedes S29WS512R, S29WS256R, and S29WS128R respectively. This is the factory-recommended migration path. Please refer to the S29WS-P data sheet for specifications and ordering information.

Availability of this document is retained for reference and historical purposes only.

The order number is formed by a valid combinations of the following:

S29WS
n 0P BH W 00 0 ig Packing Type s 0 = Tray standard see note 1 e 2 = 7-inch Tape and Reel D 3 = 13-inch Tape and Reel

Model Number
w Boot Configuration Options e 00 = Uniform, 1 CE N 20 = Top Boot, 1 CE r Temperature Range fo W = Wireless to +85C

Package Type And Material
d BH = Very Thin Fine-Pitch BGA, Low-Halogen Lead Pb -free Package e Speed Option Burst Frequency d 0P = 66 MHz n 0S = 83 MHz eAA = 104 MHz mProcess Technology

R = 65 nm MirrorBit Technology
m Flash Density o 512 =512 Mb c 256 =256 Mb e 128 =128 Mb R Device Family Not S29WS Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.

S29WS-R Valid Combinations Notes 1, 2
Base Ordering Part Number S29WS512R S29WS256R S29WS128R

Speed Option

Package Type, Material, & Temperature Range
0P, 0S, AA

BHW Low-Halogen, Lead Pb -free

Packing Type
0, 2, 3 Note 1

Model Numbers
00, 20

Package Type Note 2
mm x 8 mm 84-ball

MCP-Compatible
Notes Type 0 is standard. Specify other options as required. BGA package marking omits leading S29 and packing type designator from ordering part number.

Product Status

Advance

Page 5 of 77

S29WS512R S29WS256R, S29WS128R

Input/Output Descriptions & Logic Symbol

Table identifies the input and output package connections provided on the device.

Table Input/Output Descriptions

Symbol Amax A0 DQ15 DQ0 F1-CE#

F2-CE# OE# WE# VCC VCCQ VSS NC RDY

AVD#

RESET#

Type Input I/O Input

Input Supply No Connect Output

Input

Input

Input

Input

Reserved

Higher order address lines. Amax = A24 for WS512R, A23 for WS256R, A22 for WS128R

Data input/output

Flash-1 Chip Enable. Asynchronous relative to CLK. Used to select the first portion of the flash device address space that can be directly selected by one host chip enable signal.

Flash-2 Chip Enable. Asynchronous relative to CLK. Used to select the first portion of the flash device address space that can be directly selected by one host chip enable signal.

Output Enable. Asynchronous relative to CLK for the Burst mode

Write Enable
ign Device Power Supply s Input/Output Power Supply must be ramped simultaneously with VCC e Ground D No Connected internally

Ready. Indicates when valid burst data is ready to be read
ew The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst
mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal

N address counter. CLK should remain low during asynchronous access r Address Valid input. Indicates to device that the valid address is present on the address inputs. fo VIL = for asynchronous mode, indicates valid address for burst mode, cause staring address to be
latched on rising edge of CLK.
d VIH = device ignores address inputs e Hardware Reset. Low = device resets and returns to reading array data. d Accelerated input. n At VIL,disables all program and erase functions. e Should be at VIH for all other conditions. Not Recomm Reserved for future use

Page 6 of 77

S29WS512R S29WS256R, S29WS128R

Block Diagrams

VCC VSS VCCQ

Figure Simultaneous Operation Circuit

Latches and Control Logic

Bank Address

Y-Decoder

Bank 0 X-Decoder
Effective Write Buffer Programming VACC Per Byte Typical Program & Erase Time Product Ordering Information

Valid Combination Table

Changed Typical value from µs to 6 µs
n Change Sector Erase 32 KByte Sector from 0.3s to 0.355s ig Added package, boot configuration and frequency information to ordering information s Removed WS2901GR De Added model # 00 and 02 for boot configuration

Block Diagram
ew Input/Output Descriptions & Logic
r N Pin Out Diagram fo Synchronous Read Wait State Table ed DC Characterization mend AC Characterization com Product Overview Re Synchronous Burst Read Mode Not VCC Power Up

Renamed VPP to ACC Removed A/D mux from I/O description Removed Address multiplexing wording from AVD#

Removed WP# pin

Reformatted the frequency description

Added 83 MHz value for ICCB and ICC5 Changed all 108 MHz to 104 MHz Changed VLKO Min/Max from 1.3V/1.4V to 1.0V/1.1V Synchronous Burst Changed tBDH min from 5 ns for 66 MHz/83 MHz to 3 ns, ns for 108 MHz/ 133 Mhz to 2 ns for 104 Mhz/133 MHz Asynchronous Read Changed tWEA from 4 ns to tCLK Asyncronous Write Change tESL and tPSL from 20 µs to 30 µs Added note 3 on AVD requirement to subsequent CLK cycle

Corrected Secure Silicon Region size to 512 Bytes

Deleted wait state 2 from Wait State Tables Figure Changed 256 Byte Boundary Crossing Latency additional wait states up to 2

Changed tVCS value to 300 µs Changed VIOS value to 300 µs

Added tRPH to timing diagram

Wait State Configuration Register Setup

Corrected typo in table to wait state 13

Device ID and CFI Table

General update CFI values

Device ID and Common Flash Memory Interface Table

Corrected CFI setting for 4Ah

Removed 133 MHz speed option
Ordering Information & Valid Combination Table

Flash Memory Array

Table Device Bus Operation

Added Low-Halogen Lead Free package option Removed Standard Lead Free package option Updated table to correct sector range for bank 16 of S29WS512R Deleted Asynchronous Write WE# latched Address

Page 71 of 77

S29WS512R S29WS256R, S29WS128R

Section Write Buffer Programming Command

Changed to word offset

AC Characterization Program/Erase Operation

Changed Clock High or Low time tCLK H/L to tCLK Deleted Programming of a previously programmed location

Deleted ACC mode from single word programming

Changed 32-word buffer programming performance VCC mode 400 µs, ACC mode to 256 µs Change Chip Programming Time for VCC mode as below:
• 128 Mbit 105s typical 210s max
• 256 Mbit 210s typical 420s max
• 512 Mbit 420s typical 840s max Changed sector erase time as follows:
• 128 Kbyte VCC Note 6 typ , max

Program and Erase Performance
• 32 Kbyte VCC Note 6 typ , max
n
• 128 Kbyte ACC Note 6 typ , max ig
• 32 Kbyte ACC Note 6 typ , max

Updated chip erase time both VCC and VPP as follows:
es
• WS128R 78/126 s typ , 154/250 s max D
• WS256R 155/251 s typ , 308/500 s max

Global
Combinations
t R Input/Output Descriptions & Logic o Symbol N VCC Power Up
• WS512R 308/500 s typ , 612/998 s max Added Note 6 to state, The first value is excluding pre-programming time, while the second value is inclusive of pre-programming for the FFFFh pattern, with status polling rate as 400 ns typ . Added Note 7 to state, The erase time is calculated from the time of issuing erase command to the completion of erase operation indicated by status register .

Remove 1G product option Add additional model numbers for uniform boot, 1 and 2CEs Blank Check Command functional in Asynchronous Read Mode only Change ICCB for 83 MHz 16word burst to 26 mA Effect Word Programming time using Write Buffer change to µs for VCC mode and 8 µs for ACC mode

Removed model numbers 10, 30, 50

Input/Output Descriptions table Updated ACC description Removed tRH from table

Device ID and Common Flash Memory Interface Address Map

ID/CFI Data table Updated SA + 51h description

Sector Lock Range Command

Clarified Sector Lock Range command behavior

Global

Added product obsolescence information

Page 72 of 77

S29WS512R S29WS256R, S29WS128R

Document History Page

Document Title S29WS512R, S29WS256R, S29WS128R 512/256/128 Mb 32/16/8M x 16 bit , V, S29WS-R Flash Document Number 002-01101

ECN No.

Orig. of Change WIOB

WIOB

Submission Date

Description of Change
03/28/2007 Initial release
04/24/2007

Device ID and Common Flash Memory Interface Address Map Updated device ID for word offset 03H to 00FFh

Effective Write Buffer Programming VCC Per Byte Changed Typical value
from 4.7µs to µs

Effective Write Buffer Programming VACC Per Byte Changed Typical value
from µs to 6 µs

Not Recommended for New Design WIOB
Typical Program & Erase Time Change Sector Erase 32 KByte Sector from 0.3s to 0.355s Product Ordering Information Added package, boot configuration and frequency information to ordering information

Valid Combination Table Removed WS2901GR

Added model # 00 and 02 for boot configuration

Block Diagram Renamed VPP to ACC

Input/Output Descriptions & Logic Symbol Removed A/D mux from I/O description

Removed Address multiplexing wording from AVD#
03/19/2008

Pin Out Diagram Removed WP# pin Synchronous Read Wait State Table Reformatted the frequency description DC Characterization Added 83 MHz value for ICCB and ICC5 Changed all 108 MHz to 104 MHz Changed VLKO Min/Max from 1.3V/1.4V to 1.0V/1.1V

AC Characterization Synchronous Burst Changed tBDH min from 5 ns for 66 MHz/83 MHz to 3 ns, ns for 108 MHz/133 Mhz to 2 ns for 104 Mhz/133 MHz

Asynchronous Read Changed tWEA from 4 ns to tCLK

Asyncronous Write Change tESL and tPSL from 20 µs to 30 µs

Added note 3 on AVD requirement to subsequent CLK cycle

Product Overview Corrected Secure Silicon Region size to 512 Bytes

Synchronous Burst Read Mode Deleted wait state 2 from Wait State Tables

Figure 7.1Changed 256 Byte Boundary Crossing Latency additional wait
states up to 2

VCC Power Up Changed tVCS value to 300 µs Changed VIOS value to 300 µs Added tRPH to timing diagram

Wait State Configuration Register Set-up Corrected typo in table to wait state 13

WIOB
03/25/2008

Device ID and Common Flash Memory Interface Table Corrected CFI setting for 4Ah

Page 73 of 77

S29WS512R S29WS256R, S29WS128R

Document History Page Continued

Document Title S29WS512R, S29WS256R, S29WS128R 512/256/128 Mb 32/16/8M x 16 bit , V, S29WS-R Flash Document Number 002-01101

ECN No.

Orig. of Submission

Change

Description of Change

Global Removed 133 MHz speed option
Ordering Information & Valid Combination Table Added Low-Halogen Lead

Free package option

Removed Standard Lead Free package option

Flash Memory Array Updated table to correct sector range for bank 16 of

S29WS512R

Table Device Bus Operation Deleted Asynchronous Write WE# latched

Address

Not Recommended for New Design WIOB
10/27/2008

Write Buffer Programming Command Changed to word offset AC Characterization Changed Clock High or Low time tCLK H/L to tCLK Program/Erase Operation Deleted Programming of a previously programmed location

Program and Erase Performance Deleted ACC mode from single word programming

Changed 32-word buffer programming performance VCC mode 400 µs, ACC mode to 256 µs

Change Chip Programming Time for VCC mode as below
• 128 Mbit 105s typical 210s max
• 256 Mbit 210s typical 420s max
• 512 Mbit 420s typical 840s max

Changed sector erase time as follows:
• 128 Kbyte VCC Note 6 typ , max
• 32 Kbyte VCC Note 6 typ , max
• 128 Kbyte ACC Note 6 typ , max
• 32 Kbyte ACC Note 6 typ , max Updated chip erase time both VCC and VPP as follows:
• WS128R 78/126 s typ , 154/250 s max
• WS256R 155/251 s typ , 308/500 s max
• WS512R 308/500 s typ , 612/998 s max

Added Note 6 to state, The first value is excluding pre-programming time, while the second value is inclusive of pre-programming for the FFFFh pattern, with status polling rate as 400 ns typ . Added Note 7 to state, The erase time is calculated from the time of issuing erase command to the completion of erase operation indicated by status reg-
ister .

Global Remove 1G product option
Ordering Information and Valid Combinations Add additional model numbers
for uniform boot, 1 and 2CEs

WIOB
02/27/2009

Device Operation Blank Check Command functional in Asynchronous Read Mode only

DC Characteristics Change ICCB for 83 MHz 16word burst to 26 mA Programming Performance Effect Word Programming time using Write Buffer
change to µs for VCC mode and 8 µs for ACC mode
Ordering Information and Valid Combinations Removed model numbers 10,
30, 50

Input/Output Descriptions & Logic Symbol Input/Output Descriptions table

WIOB 05/07/2009 Updated ACC description

VCC Power Up Removed tRH from table Device ID and Common Flash Memory Interface Address Map ID/CFI Data
table Updated SA + 51h description

Page 74 of 77

S29WS512R S29WS256R, S29WS128R

Document History Page Continued

Document Title S29WS512R, S29WS256R, S29WS128R 512/256/128 Mb 32/16/8M x 16 bit , V, S29WS-R Flash Document Number 002-01101
*G *H

ECN No.

Orig. of Change

WIOB

WIOB

Submission Date

Description of Change
06/01/2011 Sector Lock Range Command Clarified Sector Lock Range command behavior
18/19/2011 Global Added product obsolescence information
4953774 WIOB 10/09/2015 Updated to Cypress template.

Design Not Recommended for New

Page 75 of 77

S29WS512R S29WS256R, S29WS128R

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Not Recommended for New

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived S29WS256R0SBHW000 Datasheet file may be downloaded here without warranties.

Datasheet ID: S29WS256R0SBHW000 508320