CYV15G0101DX-VIDEO

CYV15G0101DX-VIDEO Datasheet

CYV15G0101DXB U5

Part	Datasheet
CYV15G0101DX-VIDEO	CYV15G0101DX-VIDEO (pdf)

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HOTLink II Video Evaluation Board Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 [+] Feedback HOTLink II Video Evaluation Board Table of Contents Introduction 5 Kit Contents 5 Evaluation Board Features 7 Functional Overview 7 Block Diagram 7 DVB and MPEG Overview 8 SMPTE 259M Overview 9 Scrambling/Descrambling 10 HEB Test Software Set-up and Operation 10 HOTLink II Video Board Software Set-up Instructions 10 Board Configuration Instructions 11 Running the Tests 13 Parallel Loop Back Tests 13 Serial Loop Back Tests 15 Function Test Suite Tests 17 References 21 Appendix A Schematics of HOTLink II Video Evaluation Board 22 Appendix B PCB Layout Diagrams of HOTLink II Video Evaluation Board 32 Appendix C Bill of Materials BOM of HOTLink II Video Evaluation Board 44 2 [+] Feedback HOTLink II Video Evaluation Board List of Figures Figure Top View of Video Board 5 Figure Block Diagram of HOTLink II Video Evaluation Board 7 Figure DVB-ASI Transmission Blocks 8 Figure MPEG-2 Packet 8 Figure Example of MPEG-2 System Model 9 Figure Cypress’s SMPTE 259M Transmitter and Receiver Implementation 10 Figure SMPTE 259M Scrambler/Encoder and Descrambler/Decoder 10 Figure HEB Test GUI Window 11 Figure CLK SEL JP1 Close View 12 Figure CLK SEL JP1 Block Diagram 12 Figure Configuration Window for All Tests 13 Figure Parallel Loop Back Hardware Test Set-up 14 Figure Parallel Loop Back Test Window 15 Figure Serial Loop Back Hardware Set-up 16 Figure Serial Loop Back Test Window 17 Figure Functional Test Suite Hardware Set-up 18 Figure Functional Test Suite Test Window 19 Figure Functional Test Suite Expected Results 20 Figure Functional Test Suite Expected Results 21 Figure A-1. Top Level Schematic CypressEvalBoard.prj 23 Figure A-2. Delta39K CPLD Schematics 39K.sch 24 Figure A-3. Cable Driver and Equalizer Schematics DriverEqualizer.sch 25 Figure A-4. HOTLink II Schematics HOTLink.sch 26 Figure A-5. PCI Bus Schematics PCI32.sch 27 Figure A-6. Clocks Schematics Clocks.sch 28 Figure A-7. EZ-USB FX2 USB Microcontroller Schematics USB.sch 29 Figure A-8. USB Page 1 Schematics Page1.sch 30 Figure A-9. USB Page 2 Schematics Page2.sch 31 Figure B-1. Board Stackup 33 Figure B-2. Top Overlay 34 Figure B-3. Top Layer 35 Figure B-4. GND Layer 36 Figure B-5. Internal Plane 2 37 Figure B-6. Internal Plane 3 38 Figure B-7. Internal Plane 4 39 Figure B-8. MidLayer1 40 Figure B-9. +3.3V Layer 41 Figure B-10. Bottom Layer 42 Figure B-11. Bottom Overlay 43 [+] Feedback HOTLink II Video Evaluation Board List of Tables Table HOTLink II Video Board Core Components Description 6 Table SDI Bit Rates 9 Table CLK SEL Pin Descriptions 12 Table C-1. Bill of Materials for HOTLink II Video Evaluation Board 45 4 [+] Feedback HOTLink II Video Evaluation Board Introduction The HOTLink II transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud. The frequency agility of the HOTLink II transceiver enables its application in various data and video transmission standards. The HOTLink II transceiver supports serial video transmission, which includes Digital Video Broadcasting DVB-ASI and Society of Motion Picture Television Engineers SMPTE standards of video transmission. DVB is a widely accepted standard for digital video transmission, especially in the video-on-demand market segment. SMPTE has in turn developed several standards for serial and parallel video transmission at different speeds and formats. The HOTLink II video evaluation board demonstrates the ability of the Cypress HOTLink II family of devices to pass video at signaling rates of up to 360 Mbps, the functionality of Delta39K CPLD as an ideal CPLD solution for SMPTE applications, the flexible clocking abilities of CyClocksRT , and the use of EZ-USB FX2 USB microcontroller for video data and in-system configuration applications. Kit Contents The kit contains the following: HOTLink II video board, as shown in Figure CD containing: a. DVB/SMPTE Test software GUI HEB Test b. Application notes c. Evaluation board user’s guide d. Cypress device data sheets Coaxial cable AC/DC wall adapter LVTTL Out P4 LVTTL IN P3 37K PLD CY37256VP160 U8 39K CPLD CY39200V388 U10 HOTLink II CYV15G0101DXB U5 Transformer PE-65508 T1 Cable Driver GS1528 U6 Cable Equalizer GS1524 U7 Power on Reset U9 Power Supply Jack DVB defines standards for television, multiple simultaneous standard definition television SDTV , and communication to mobile TV receivers, with a choice of multicast and/or unicast. By using a DVB interactive return channel, enhanced user services can include customized web and television content, distance learning, interactive ordering and more. Asynchronous Serial Interface ASI is a system for serial encoded transmission of different data rates, with a constant signaling rate, based on a layered structure of MPEG transport packets. A constant receiver clock is used. Data can be transported over several hundred meters on coaxial cable or many kilometers using fibre optics. The serial transfer of transport streams operates at a 270-MBaud rate and uses 8B/10B encoding. Figure 4-2 shows the blocks of the coaxial cable Asynchronous Serial Transmission Link. MPEG is a popular encoding and compression system for digital multimedia content defined by the Motion Picture Experts Group MPEG . An uncompressed PAL TV picture requires a bandwidth of 216 Mbps which is far beyond the capacity of most radio frequency signals. Uncompressed NTSC requires 168 Mbps and the situation becomes more acute for HDTV with bandwidths exceeding 1 Gbps. MPEG-2 provides a way to compress this digital video signal to a more manageable rate. Because MPEG-2 provides good compression it has become a standard for digital TV. The HOTLink II video board supports transmission of the MPEG-2 stream over DVB-ASI. MPEG-2 packet size can either be 188 or 204 bytes wide. This packet is comprised of a header and a payload. The header is a minimum of 4 bytes wide and starts with a Sync Byte 47’h . Figure 4-3 shows the different fields of the MPEG-2 header. MPEG-2 addresses the combination of one or more elementary streams of video and auxiliary data into single or multiple streams which are suitable for storage or transmission. This is specified in two Layer 2 Layer 1 Layer 0 Sync Byte Insertion 8B/10B Encoding Parallel/Serial Conversion Amplifier /Buffer Coupling / Impedance Matching MPEG-2 Sync Byte Deletion 8B/10B Decoding Clock/Data Recovery and Serial/Parallel conversion Amplifier /Buffer Coupling / Impedance Matching 188/204 Bytes Figure 4-2.DVB-ASI Transmission Blocks Header Payload Connector Coaxial Cable Connector Sync Byte Transport Start Transport Error Indicator Priority Indicator Adaptation Scrambling Field Control Continuity Adaptation Counter Field Figure 4-3.MPEG-2 Packet Payload [+] Feedback HOTLink II Video Evaluation Board Audio Data Audio Encoder Packetizer Audio Program Elementary Stream Program Stream MUX Program Stream Video Data Video Encoder

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HOTLink II Video Evaluation Board

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600
[+] Feedback

HOTLink II Video Evaluation Board

Table of Contents Introduction 5 Kit Contents 5 Evaluation Board Features 7 Functional Overview 7

Block Diagram 7 DVB and MPEG Overview 8 SMPTE 259M Overview 9

Scrambling/Descrambling 10

HEB Test Software Set-up and Operation 10 HOTLink II Video Board Software Set-up Instructions 10 Board Configuration Instructions 11 Running the Tests 13

Parallel Loop Back Tests 13 Serial Loop Back Tests 15 Function Test Suite Tests 17

References 21 Appendix A Schematics of HOTLink II Video Evaluation Board 22 Appendix B PCB Layout Diagrams of HOTLink II Video Evaluation Board 32 Appendix C Bill of Materials BOM of HOTLink II Video Evaluation Board 44
2 [+] Feedback

HOTLink II Video Evaluation Board

List of Figures

Figure Top View of Video Board 5 Figure Block Diagram of HOTLink II Video Evaluation Board 7 Figure DVB-ASI Transmission Blocks 8 Figure MPEG-2 Packet 8 Figure Example of MPEG-2 System Model 9 Figure Cypress’s SMPTE 259M Transmitter and Receiver Implementation 10 Figure SMPTE 259M Scrambler/Encoder and Descrambler/Decoder 10 Figure HEB Test GUI Window 11 Figure CLK SEL JP1 Close View 12 Figure CLK SEL JP1 Block Diagram 12 Figure Configuration Window for All Tests 13 Figure Parallel Loop Back Hardware Test Set-up 14 Figure Parallel Loop Back Test Window 15 Figure Serial Loop Back Hardware Set-up 16 Figure Serial Loop Back Test Window 17 Figure Functional Test Suite Hardware Set-up 18 Figure Functional Test Suite Test Window 19 Figure Functional Test Suite Expected Results 20 Figure Functional Test Suite Expected Results 21 Figure A-1. Top Level Schematic CypressEvalBoard.prj 23 Figure A-2. Delta39K CPLD Schematics 39K.sch 24 Figure A-3. Cable Driver and Equalizer Schematics DriverEqualizer.sch 25 Figure A-4. HOTLink II Schematics HOTLink.sch 26 Figure A-5. PCI Bus Schematics PCI32.sch 27 Figure A-6. Clocks Schematics Clocks.sch 28 Figure A-7. EZ-USB FX2 USB Microcontroller Schematics USB.sch 29 Figure A-8. USB Page 1 Schematics Page1.sch 30 Figure A-9. USB Page 2 Schematics Page2.sch 31 Figure B-1. Board Stackup 33 Figure B-2. Top Overlay 34 Figure B-3. Top Layer 35 Figure B-4. GND Layer 36 Figure B-5. Internal Plane 2 37 Figure B-6. Internal Plane 3 38 Figure B-7. Internal Plane 4 39 Figure B-8. MidLayer1 40 Figure B-9. +3.3V Layer 41 Figure B-10. Bottom Layer 42 Figure B-11. Bottom Overlay 43
[+] Feedback

HOTLink II Video Evaluation Board List of Tables Table HOTLink II Video Board Core Components Description 6 Table SDI Bit Rates 9 Table CLK SEL Pin Descriptions 12 Table C-1. Bill of Materials for HOTLink II Video Evaluation Board 45
4 [+] Feedback

HOTLink II Video Evaluation Board

Introduction

The HOTLink II transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud.

The frequency agility of the HOTLink II transceiver enables its application in various data and video transmission standards. The HOTLink II transceiver supports serial video transmission, which includes Digital Video Broadcasting DVB-ASI and Society of Motion Picture Television Engineers SMPTE standards of video transmission. DVB is a widely accepted standard for digital video transmission, especially in the video-on-demand market segment. SMPTE has in turn developed several standards for serial and parallel video transmission at different speeds and formats.

The HOTLink II video evaluation board demonstrates the ability of the Cypress HOTLink II family of devices to pass video at signaling rates of up to 360 Mbps, the functionality of

Delta39K CPLD as an ideal CPLD solution for SMPTE applications, the flexible clocking abilities of CyClocksRT , and the use of EZ-USB FX2 USB microcontroller for video data and in-system configuration applications.

Kit Contents

The kit contains the following:

HOTLink II video board, as shown in Figure CD containing:
a. DVB/SMPTE Test software GUI HEB Test b. Application notes c. Evaluation board user’s guide d. Cypress device data sheets Coaxial cable AC/DC wall adapter

LVTTL Out P4

LVTTL IN P3
37K PLD

CY37256VP160 U8
39K CPLD

CY39200V388 U10

HOTLink II

CYV15G0101DXB U5

Transformer PE-65508 T1

Cable Driver GS1528 U6

Cable Equalizer GS1524 U7

Power on Reset U9

Power Supply Jack
DVB defines standards for television, multiple simultaneous standard definition television SDTV , and communication to mobile TV receivers, with a choice of multicast and/or unicast. By using a DVB interactive return channel, enhanced user services can include customized web and television content, distance learning, interactive ordering and more.

Asynchronous Serial Interface ASI is a system for serial encoded transmission of different data rates, with a constant signaling rate, based on a layered structure of MPEG transport packets. A constant receiver clock is used. Data can be transported over several hundred meters on coaxial cable or many kilometers using fibre optics. The serial transfer of transport streams operates at a 270-MBaud rate and uses 8B/10B encoding. Figure 4-2 shows the blocks of the coaxial cable Asynchronous Serial Transmission Link.

MPEG is a popular encoding and compression system for digital multimedia content defined by the Motion Picture Experts Group MPEG . An uncompressed PAL TV picture requires a bandwidth of 216 Mbps which is far beyond the capacity of most radio frequency signals. Uncompressed NTSC requires 168 Mbps and the situation becomes more acute for HDTV with bandwidths exceeding 1 Gbps. MPEG-2 provides a way to compress this digital video signal to a more manageable rate. Because MPEG-2 provides good compression it has become a standard for digital TV.

The HOTLink II video board supports transmission of the MPEG-2 stream over DVB-ASI. MPEG-2 packet size can either be 188 or 204 bytes wide. This packet is comprised of a header and a payload. The header is a minimum of 4 bytes wide and starts with a Sync Byte 47’h . Figure 4-3 shows the different fields of the MPEG-2 header. MPEG-2 addresses the combination of one or more elementary streams of video and auxiliary data into single or multiple streams which are suitable for storage or transmission. This is specified in two

Layer 2

Layer 1

Layer 0

Sync Byte Insertion
8B/10B Encoding

Parallel/Serial Conversion

Amplifier /Buffer

Coupling / Impedance Matching

MPEG-2

Sync Byte Deletion
8B/10B Decoding

Clock/Data Recovery and Serial/Parallel conversion

Amplifier /Buffer

Coupling / Impedance Matching
188/204 Bytes

Figure 4-2.DVB-ASI Transmission Blocks

Header

Payload

Connector

Coaxial Cable

Connector

Sync Byte

Transport Start Transport Error Indicator Priority

Indicator

Adaptation

Scrambling Field Control

Continuity Adaptation Counter Field

Figure 4-3.MPEG-2 Packet

Payload
[+] Feedback

HOTLink II Video Evaluation Board

Audio Data Audio Encoder

Packetizer

Audio Program Elementary Stream

Program Stream MUX

Program Stream

Video Data Video Encoder

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYV15G0101DX-VIDEO Datasheet file may be downloaded here without warranties.

Datasheet ID: CYV15G0101DX-VIDEO 508274