CYDD18S36V18-167BBXC

CYDD18S36V18-167BBXC Datasheet


18 Mbit 256K x 36 x 2 DDR or 256K x 72 SDR CYDD18S72V18

Part Datasheet
CYDD18S36V18-167BBXC CYDD18S36V18-167BBXC CYDD18S36V18-167BBXC (pdf)
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PDF Datasheet Preview
FullFlex
• True dual-ported memory allows simultaneous access to the shared array from each port
• Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate SDR operation on each port DDR interface at 200 MHz SDR interface at 250 MHz Up to 36-Gb/s bandwidth 250 MHz * 72 bit * 2 ports
• Selectable pipelined or flow-through mode
• 1.5V or 1.8V core power supply
• Commercial and Industrial temperature ranges
• IEEE JTAG boundary scan
• Available in 484-ball PBGA Packages and 256-ball

FBGA Packages
• FullFlex72 family
18 Mbit 256K x 36 x 2 DDR or 256K x 72 SDR CYDD18S72V18
9 Mbit 128K x 36 x 2 DDR or 128K x 72 SDR CYDD09S72V18
4 Mbit 64K x 36 x 2 DDR or 64 x 72 SDR CYDD04S72V18
• FullFlex36 family 36 Mbit 512K x 36 x 2 DDR CYDD36S36V18 18 Mbit 256K x 36 x 2 DDR CYDD18S36V18 9 Mbit 128K x 36 x 2 DDR CYDD09S36V18 4 Mbit 64K x 36 x 2 DDR CYDD04S36V18
• FullFlex18 family 36 Mbit 1M x 18 x 2 DDR CYDD36S18V18 18 Mbit 512K x 18 x 2 DDR CYDD18S18V18 9 Mbit 256K x 18 x 2 DDR CYDD09S18V18 4 Mbit 128K x 18 x 2 DDR CYDD04S18V18
• Built-in deterministic access control to manage address collisions Deterministic flag output upon collision detection Collision detection on back-to-back clock cycles First Busy Address readback
• Advanced features for improved high-speed data transfer and flexibility Variable Impedance Matching VIM Echo clocks

FullFlex Synchronous DDR Dual-Port SRAM

Selectable LVTTL 3.3V , Extended HSTL 1.8V LVCMOS, or 2.5V LVCMOS I/O on each port

Burst counters for sequential memory access

Mailbox with interrupt flags for message passing

Dual Chip Enables for easy depth expansion

Functional Description

The FullFlex Dual-Port SRAM families consist of 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two ports are provided, allowing the array to be accessed simultaneously. Simultaneous access to a location triggers deterministic access control. For FullFlex72, these ports can operate independently in DDR mode with 36-bit bus widths or in SDR mode with 72-bit bus widths. For FullFlex36 and FullFlex18, the ports operate in DDR mode only. Each port can be independently configured for two pipelined stages for SDR mode or stages in DDR mode. Each port can also be configured to operate in pipelined or flow-through mode in SDR mode.

Advanced features include built-in deterministic access control to manage address collisions during simultaneous access to the same memory location, Variable Impedance Matching VIM to improve data transmission by matching the output driver impedance to the line impedance, and echo clocks to improve data transfer.

To reduce the static power consumption, chip enables can be used to power down the internal circuitry. The number of cycles of latency before a change in CE0 or CE1 will enable or disable the databus matches the number of cycles of read latency selected for the device. In order for a valid write or read to occur, both chip enable inputs on a port must be active.

Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally.

Additional features of this device include a mask register and a mirror register to control counter increments and wrap-around. The counter-interrupt CNTINT flags notify the host that the counter will reach maximum count value on the next clock cycle. The host can read the burst-counter internal address, mask register address, and busy address on the address lines. The host can also load the counter with the address stored in the mirror register by utilizing the retransmit functionality. Mailbox interrupt flags can be used for message passing, and JTAG boundary scan and asynchronous Master Reset MRST are also available. The logic block diagram in Figure 1 displays these features.

The FullFlex72 DDR family of devices is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 DDR only families of devices are offered in both 484-ball and 256-ball fine pitch BGA packages.

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
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FTSELL CQENL PORTSTD[1:0]L

DDRONL

DQ[71:0]L BE [7:0]L

CE0L CE1L OEL

R/WL CQ0L CCQQ10LL CQ1L

CONFIG Block

IO Control

CONFIG Block

IO Control

Dual Ported Array

FullFlex

FTSELR CQENR PORTSTD[1:0]R DDRONR

DQ [71:0]R BE [7:0]R

CE0R CE1R OER R/WR CQ0R CCQQ10RR CQ1R

A [19:0]L
Ordering Information

FullFlex
256K x 72/256K x 36 x 2 18 Mbit 1.8V/1.5V Synchronous CYDD18S72V18 Dual-Port SRAM SDR and DDR I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
200 CYDD18S72V18-200BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Lead-Free Commercial

CYDD18S72V18-200BGC BG484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Leaded Commercial
167 CYDD18S72V18-167BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Lead-Free Commercial

CYDD18S72V18-167BGC BG484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Leaded Commercial

CYDD18S72V18-167BGXI BY484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Lead-Free Industrial

CYDD18S72V18-167BGI BG484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Leaded Industrial
128K x 72/128K x 36 x 2 9 Mbit 1.8V/1.5V Synchronous CYDD09S72V18 Dual-Port SRAM SDR and DDR I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
200 CYDD09S72V18-200BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Lead-Free Commercial

CYDD09S72V18-200BGC BG484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Leaded Commercial
167 CYDD09S72V18-167BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Lead-Free Commercial

CYDD09S72V18-167BGC BG484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Leaded Commercial

CYDD09S72V18-167BGXI BY484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Lead-Free Industrial

CYDD09S72V18-167BGI BG484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Leaded Industrial
64K x 72/64K x 36 x 2 4 Mbit 1.8V/1.5V Synchronous CYDD04S72V18 Dual-Port SRAM SDR and DDR I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
200 CYDD04S72V18-200BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Lead-Free Commercial

CYDD04S72V18-200BGC BG484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Leaded Commercial
167 CYDD04S72V18-167BGXC BY484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Lead-Free Commercial

CYDD04S72V18-167BGC BG484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Leaded Commercial

CYDD04S72V18-167BGXI BY484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Lead-Free Industrial

CYDD04S72V18-167BGI BG484A 484-ball Grid Array 23 mm x 23 mm with mm pitch Leaded Industrial
1024K x 36 x 2 36 Mbit 1.8V/1.5V Synchronous CYDD36S36V18 Dual-Port SRAM DDR only I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
167 CYDD36S36V18-167BGXC BY484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Lead-Free Commercial

CYDD36S36V18-167BGC BG484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Leaded Commercial
133 CYDD36S36V18-133BGXC BY484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Lead-Free Commercial

CYDD36S36V18-133BGC BG484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Leaded Commercial

CYDD36S36V18-133BGXI BY484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Lead-Free Industrial

CYDD36S36V18-133BGI BG484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Leaded Industrial

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FullFlex
Ordering Information continued
512K x 36 x 2 18 Mbit 1.8V/1.5V Synchronous CYDD18S36V18 Dual-Port SRAM DDR only I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
200 CYDD18S36V18-200BBXC BW256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Lead-Free Commercial

CYDD18S36V18-200BBC BB256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Leaded Commercial
167 CYDD18S36V18-167BBXC BW256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Lead-Free Commercial

CYDD18S36V18-167BBC BB256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Leaded Commercial

CYDD18S36V18-167BBXI BW256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Lead-Free Industrial

CYDD18S36V18-167BBI

BB256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Leaded Industrial
256K x 36 x 2 9 Mbit 1.8V/1.5V Synchronous CYDD09S36V18 Dual-Port SRAM DDR only I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
200 CYDD09S36V18-200BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Commercial

CYDD09S36V18-200BBC BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Commercial
167 CYDD09S36V18-167BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Commercial

CYDD09S36V18-167BBC BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Commercial

CYDD09S36V18-167BBXI BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Industrial

CYDD09S36V18-167BBI

BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Industrial
128K x 36 x 2 4 Mbit 1.8V/1.5V Synchronous CYDD04S36V18 Dual-Port SRAM DDR only I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
200 CYDD04S36V18-200BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Commercial

CYDD04S36V18-200BBC BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Commercial
167 CYDD04S36V18-167BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Commercial

CYDD04S36V18-167BBC BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Commercial

CYDD04S36V18-167BBXI BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Industrial

CYDD04S36V18-167BBI

BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Industrial
2048K x 18 x 2 36 Mbit 1.8V/1.5V Synchronous CYDD36S18V18 Dual-Port SRAM DDR only I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
167 CYDD36S18V18-167BGXC BY484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Lead-Free Commercial

CYDD36S18V18-167BGC BG484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Leaded Commercial
133 CYDD36S18V18-133BGXC BY484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Lead-Free Commercial

CYDD36S18V18-133BGC BG484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Leaded Commercial

CYDD36S18V18-133BGXI BY484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Lead-Free Industrial

CYDD36S18V18-133BGI BG484S 484-ball Grid Array 27 mm x 27 mm with mm pitch Leaded Industrial
1024K x 18 x 2 18 Mbit 1.8V/1.5V Synchronous CYDD18S18V18 Dual-Port SRAM DDR only I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
200 CYDD18S18V18-200BBXC BW256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Lead-Free Commercial

CYDD18S18V18-200BBC BB256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Leaded Commercial
167 CYDD18S18V18-167BBXC BW256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Lead-Free Commercial

CYDD18S18V18-167BBC BB256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Leaded Commercial

CYDD18S18V18-167BBXI BW256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Lead-Free Industrial

CYDD18S18V18-167BBI

BB256C 256-ball Grid Array 19 mm x 19 mm with mm pitch Leaded Industrial

Page 46 of 53 [+] Feedback

FullFlex
Ordering Information continued
512K x 18 x 2 9 Mbit 1.8V/1.5V Synchronous CYDD09S18V18 Dual-Port SRAM DDR only I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
200 CYDD09S18V18-200BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Commercial

CYDD09S18V18-200BBC BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Commercial
167 CYDD09S18V18-167BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Commercial

CYDD09S18V18-167BBC BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Commercial

CYDD09S18V18-167BBXI BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Industrial

CYDD09S18V18-167BBI

BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Industrial
256K x 18 x 2 4 Mbit 1.8V/1.5V Synchronous CYDD04S18V18 Dual-Port SRAM DDR only I/O

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
200 CYDD04S18V18-200BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Commercial

CYDD04S18V18-200BBC BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Commercial
167 CYDD04S18V18-167BBXC BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Commercial

CYDD04S18V18-167BBC BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Commercial

CYDD04S18V18-167BBXI BW256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Lead-Free Industrial

CYDD04S18V18-167BBI

BB256E 256-ball Grid Array 17 mm x 17 mm with mm pitch Leaded Industrial

Page 47 of 53 [+] Feedback

Package Diagrams

FullFlex

PIN 1 CORNER

A B C D E F G H J K L M N P R T
256-ball Lead-Free FBGA 17 x 17 mm BW256

TOP VIEW
256-ball Leaded FBGA 17 x 17 mm BB256

M C M C A B

BOTTOM VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Ø0.45±0.05 256X -CPLD DEVICES 37K & 39K

PIN 1 CORNER
+205.160X -ALL OTHER DEVICES
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A B C D E F G H J K L M N P R T

SEATING PLANE
0.20 4X

REFERENCE JEDEC MO-192

A1 A MAX. MAX.
51-85108-*F

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FullFlex

Package Diagrams continued
256-ball Lead-Free FBGA 19 x 19 x mm BW256
256-ball Leaded FBGA 19 x 19 x mm BB256

BOTTOM VIEW

TOP VIEW

PIN A1 CORNER
11 13 15
386692 See ECN SPN Updated ordering information

Added statement about no echo clocks for flow-through mode

Updated electrical characteristics

Added note 27 timing for x18 devices

Updated address readback latency to 2 cycles for DDR mode

Updated DDR timing numbers for tCD, tDC, tCCQ, tCQHQV, tCQHQX, tCKHZ, tCKLZ Updated input edge rate

Removed -133 speed bin electrical characteristics and timing columns

Updated Table 5 on collision detection to be the same as the one found in the EROS

Added description of busy readback in collision detection section

Changed dummy write descriptions

Updated PORTSTD[1:0] connection details

Updated ZQ pins connection details

Updated address count notes

Updated note 17, BO to BEO

Added power supply requirements to MRST and VC_SEL

Updated 484 ball package

Changed name from FLEX72-E, FLEX36-E, AND FLEX18-E to FullFlex72,

FullFlex36, and FullFlex18
401662 See ECN KGH Updated READY description to include Wired OR note

Updated master reset to include wired OR note for READY

Updated electrical characteristics to include IOH and IOL values Updated electrical characteristics to include READY

Added IIX3 Updated maximum input capacitance

Added note 29

Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1

Changed voltage name from VDDQ to VDDIO

Changed voltage name from VDD to VCORE Updated the Package Type for the CYDXXS36V18 parts

Updated the Package Type for the CYDXXS18V18 parts

Included the Package Diagram for the 256-Ball FBGA 19 x 19 mm BW256

Included an OE Controlled Write for Flow-through Mode Switching Waveform

Included a Read with Echo Clock Switching Waveform

Included a Unit column for Table 5

Removed Switching Characteristic tCA from chart Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow-through Mode Updated AC Test Load and Waveforms

Included FullFlex36 DDR 484-ball BGA Pinout Top View

Included FullFlex18 DDR 484-ball BGA Pinout Top View Included Timing

Parameter tCORDY

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FullFlex

Document Title FullFlex Synchronous DDR Dual-Port SRAM Document Number 38-06072

Description of Change
458129 SEE ECN YDT Changed ordering information with lead-free part numbers

Removed VC_SEL

Added I/O and core voltage adders

Removed references to bin drop for LVTTL/2.5V LVCMOS and 1.5V core modes

Updated Cin and Cout

Updated ICC, ISB1, ISB2 and ISB3 tables

Updated device widths information on first page

Updated busy address read back timing diagram

Added HTSL input waveform

Removed HSTL AC from DC tables

Added 484-ball 27mmx27mmx2.33mm PBGA package
470037 SEE ECN YDT Changed VOL of 1.8V LVCMOS to 0.45V and VOH to VDDIO - 0.45V

Updated tRSF

VREF is left DNU when HSTL is not used

Changed LVTTL/LVCMOS adder for DDR

Formatted pin description table

Changed VDDIO pins for 36Mx36 and 36Mx18

Changed 36Mx72 JTAG IDCODE
499993 SEE ECN YDT DLL Change, added Clock Input Cycle to Cycle Jitter

Modified DLL description

Changed Input Capaciance Table

Changed tCCS number

Added note 34
627539 SEE ECN QSL change all NC to DNU
corrected switching waveform for CQEN = High from both Pipeline and

Flowthrough mode to only pipeline mode

Added note 17 to DDRON restriction

Modified Master Reset Description

Created a new table for flow-through mode only
changed note 29 description

Modified tSD, tHD, tSBE, tHBE, tCD, tDC, tCCQ, tCQHQV, tCQHQX, tCKHZ, and
tCKLZ timing parameter

Removed all instances of CYDD36S72V18

Page 53 of 53 [+] Feedback
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Datasheet ID: CYDD18S36V18-167BBXC 508273