CYW4356XKUBGT

CYW4356XKUBGT Datasheet

CYW4356

Part	Datasheet
CYW4356XKUBGT	CYW4356XKUBGT (pdf)

PDF Datasheet Preview
ADVANCE CYW4356 Single-Chip 5G WiFi IEEE 802.11ac 2x2 MAC/ Baseband/Radio with Integrated Bluetooth FM Receiver, and Wireless Charging The Cypress CYW4356 is a complete dual-band GHz and 5 GHz 5G WiFi 2 x 2 MIMO MAC/PHY/Radio System-on-a-Chip. This Wi-Fi single-chip device provides a high level of integration with dual-stream IEEE 802.11ac MAC/baseband/radio, Bluetooth and FM radio receiver. Additionally, it supports wireless charging. In IEEE 802.11ac mode, the WLAN operation supports rates of MCS9 up to 256 QAM in 20 MHz, 40 MHz, and 80 MHz channels for data rates up to 867 Mbps. In addition, all the rates specified in IEEE 802.11a/b/g/n are supported. Included on-chip are GHz and 5 GHz transmit power amplifiers and receive low noise amplifiers. For the WLAN section, several alternative host interface options are included an SDIO v3.0 interface that can operate in 4b or 1b modes, and a PCIe v3.0 compliant interface running at Gen1 speeds. For the Bluetooth section, host interface options of a high-speed 4-wire UART and USB full-speed 12 Mbps are provided. The CYW4356 uses advanced design techniques and process technology to reduce active and idle power, and includes an embedded power management unit that simplifies the system power topology. In addition, the CYW4356 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms that ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. Coexistence support for external radios such as LTE cellular and GPS is provided via an external interface. As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved. This data sheet provides details on the functional, operational, and electrical characteristics for the Cypress CYW4356. It is intended for hardware design, application, and OEM engineers. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number BCM4356 BCM4330 BCM4356XKUBG BCM4356XKWBG CYW4356 CYW4330 CYW4356XKUBG CYW4356XKWBG Cypress Part Number • San Jose, CA 95134-1709 • 408-943-2600 ADVANCE CYW4356 Figure Functional Block Diagram VIO VBAT WLAN Host I/F WL_REG_ON PCIe SDIO External Coexistence I/F COEX Bluetooth Host I/F FM Rx Host I/F CLK_REQ BT_REG_ON UART USB I2S PCM BT_DEV_WAKE BT_HOST_WAKE FM I/F FM Audio Out I2S 5G WLAN T/R Switch 2G WLAN T/R Switch CYW4356 5G WLAN T/R Switch 2G WLAN Tx 2.G WL/BT Rx 3PST Switch BT Tx FM Rx Ant1 Diplexer Ant0 Diplexer IEEE 802.11X Key Features • IEEE 802.11ac Draft compliant. • Dual-stream spatial multiplexing up to 867 Mbps data rate. • Supports 20, 40, and 80 MHz channels with optional SGI 256 QAM modulation . • Full IEEE 802.11a/b/g/n legacy compatibility with enhanced performance. • TX and RX low-density parity check LDPC support for improved range and power efficiency. • Supports IEEE 802.11ac/n beamforming. • On-chip power amplifiers and low-noise amplifiers for both bands. • Supports various RF front-end architectures including: Two antennas with one each dedicated to Bluetooth and WLAN. Two antennas with WLAN diversity and a shared Bluetooth antenna. • Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN. Mechanical Information 149 Ordering Information 153 Additional Information 153 Acronyms and Abbreviations 153 References 153 IoT Resources 153 Document History 154 Sales, Solutions, and Legal Information 155 Page 5 of 155 ADVANCE CYW4356 Overview Overview The Cypress CYW4356 single-chip device provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE a/b/g/n/ac MAC/baseband/radio, Bluetooth + EDR enhanced data rate , FM receiver, and Alliance for Wireless Power A4WP support. The wireless charging feature works in collaboration with the Wireless Power Transfer WPT BCM59350 front-end IC. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the CYW4356 and their associated external interfaces, which are described in greater detail in the following sections. Table Device Options and Features Feature Package ball count PCIe USB2.0 Bluetooth I2S GPIO SDIO WPT BSC, GPIO SPROM WLBGA 192 pins Yes Multiplexed onto six parallel Flash pins 11 Yes 395 bumps Yes No 16 Yes WLCSP Page 6 of 155 ADVANCE Figure CYW4356 Block Diagram CYW4356 FM RX BSC, GPIO BT Digital IO BT/FM FMRX FM RF FM Digital Power PTU UART/USB SLIMBus Debug UART MEIF I2S/PCM1 I2S/PCM2 GPIO SMPS Control GNSS LNA ANT Control Wake/Sleep Control IO Port Control Debug AHB Bus Matrix ETM JTAG SDP Cortex M3 AHB2 APB Bridge APB WD Timer SW Timer GPIO Ctrl RAM ROM Patch Inter Ctrl DMA Bus Arb BT PHY BT RF BTFM Control Clock Sleep Timer Clock Management PMU Controller SPI Interface The CYW4356 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates can be possible. The physical interface between the SPI master and the CYW4356 consists of the four SPI signals SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO and one interrupt signal SPI_INT . The SPI signals are muxed onto the UART signals, see Table The CYW4356 can be configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an activelow or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode and half-duplex handshaking is implemented between the SPI master and the CYW4356. The SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented in the higher layer protocols. Table SPI to UART Signal Mapping SPI_CLK SPI_CSB SPI_MISO SPI_MOSI SPI_INT SPI Signals UART_CTS_N UART_RTS_N UART_TXD UART_RXD BT_DEV_WAKE UART Signals SPI/UART Transport Detection The BT_HOST_WAKE BT_GPIO1 pin is also used for BT transport detection. The transport detection occurs during the power-up sequence. It selects either UART or SPI transport operation based on the following pin state • If the BT_HOST_WAKE BT_GPIO1 pin is pulled low by an external pull-down during power-up, it selects the SPI transport interface. • If the BT_HOST_WAKE BT_GPIO1 pin is not pulled low externally during power-up, then the default internal pull-up is detected as a high and it selects the UART transport interface. When the A4WP feature is not used and USB is selected as the Bluetooth interface to the host, an external pull-up outside the chip 10 resistor to BT_VDDIO is required. The pull-up is not necessary but is recommended when the Bluetooth/host interface is UART instead of USB. PCM Interface The CYW4356 supports two independent PCM interfaces that share the pins with the I2S interfaces. The PCM Interface on the CYW4356 can connect to linear PCM codec devices in master or slave mode. In master mode, the CYW4356 generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYW4356. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands. Slot Mapping The CYW4356 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. Frame Synchronization The CYW4356 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. Page 28 of 155 ADVANCE CYW4356 Data Formatting The CYW4356 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYW4356 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first. Wideband Speech Support When the host encodes Wideband Speech WBS packets in transparent mode, the encoded packets are transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16bit samples, resulting in a 64 Kbps bit rate. The CYW4356 also supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit data at 16 kHz 256 Kbps rate is transferred over the PCM bus. Multiplexed Bluetooth and FM Over PCM In this mode of operation, the CYW4356 multiplexes both FM and Bluetooth audio PCM channels over the same interface, reducing the number of required I/Os. This mode of operation is initiated through an HCI command from the host. The format of the data stream consists of three channels a Bluetooth channel followed by two FM channels audio left and right . In this mode of operation, the bus data rate only supports 48 kHz operation per channel with 16 bits sent for each channel. This is done to allow the low data rate Bluetooth data to coexist in the same interface as the higher speed I2S data. To accomplish this, the Bluetooth data is repeated six times for 8 kHz data and three times for 16 kHz data. An initial sync pulse on the PCM_SYNC line is used to indicate the beginning of the frame. To support multiple Bluetooth audio streams within the Bluetooth channel, both 16 kHz and 8 kHz streams can be multiplexed. This mode of operation is only supported when the Bluetooth host is the master. Figure 12 shows the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased. To change between modes of operation, the transport must be halted and restarted in the new configuration. Figure Functional Multiplex Data Diagram BT SCO 1 Rx BT SCO 2 Rx 1 Frame BT SCO 3 Rx PCM_OUT BT SCO 1 Tx BT SCO 2 Tx BT SCO 3 Tx FM Right FM Left PCM_IN FM Right FM Left PCM_SYNC PCM_CLK 16 bits per SCO frame Each SCO channel duplicates the data 6 times. Each WBS frame duplicates the data three times per frame 16 bits per frame 16 bits per frame Burst PCM Mode In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host. Page 29 of 155 ADVANCE PCM Interface Timing Short Frame Sync, Master Mode Ordering Information Part Number BCM4356XKUBG BCM4356XKWBG Package 192-ball WLBGA mm x mm, mm pitch 395-bump WLCSP mm x mm, mm pitch Operating Ambient Temperature Dual-band GHz and 5 GHz WLAN + BT to +85°C + FMRX + A4WP to 185°F Dual-band GHz and 5 GHz WLAN + BT to +85°C + FMRX + A4WP to 185°F Additional Information Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Cypress documents, go to: References The references in this section may be used in conjunction with this document. Note Cypress provides customer access to technical documentation and software through its Cypress Developer Community and Downloads and Support site see IoT Resources . For Cypress documents, replace the “xx” in the document number with the largest number available in the repository to ensure that you have the most current version of the document. Document or Item Name Bluetooth MWS Coexistence Transport Interface Specification A4WP Wireless Power Transfer System Baseline System Specification BSS January 2, 2013 PCI Express CEM v2.0 Specification Number Source IoT Resources Cypress provides a wealth of data at to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website Page 153 of 155 ADVANCE CYW4356 Document History Document Title CYW4356 Single-Chip 5G WiFi IEEE 802.11ac 2x2 MAC/Baseband/Radio with Integrated Bluetooth FM Receiver, and Wireless Charging Document Number 002-15053 Orig. of Change Submission Date Description of Change 04/01/2014 4356-DS100-R Initial release 04/24/2014 4356-DS101-R 06/25/2014 4356-DS102-R Updated: • Pin name PCI_PME_L to PCIE_PME_L. • “BCM4356 PMU Features”. • Table 59 “PCI Express Interface Parameters” Added: • “Electrostatic Discharge Specifications”.

PDF Datasheet Preview

ADVANCE

CYW4356

Single-Chip 5G WiFi IEEE 802.11ac 2x2 MAC/ Baseband/Radio with Integrated Bluetooth

FM Receiver, and Wireless Charging

The Cypress CYW4356 is a complete dual-band GHz and 5 GHz 5G WiFi 2 x 2 MIMO MAC/PHY/Radio System-on-a-Chip. This Wi-Fi single-chip device provides a high level of integration with dual-stream IEEE 802.11ac MAC/baseband/radio, Bluetooth and FM radio receiver. Additionally, it supports wireless charging. In IEEE 802.11ac mode, the WLAN operation supports rates of MCS9 up to 256 QAM in 20 MHz, 40 MHz, and 80 MHz channels for data rates up to 867 Mbps. In addition, all the rates specified in IEEE 802.11a/b/g/n are supported. Included on-chip are GHz and 5 GHz transmit power amplifiers and receive low noise amplifiers. For the WLAN section, several alternative host interface options are included an SDIO v3.0 interface that can operate in 4b or 1b modes, and a PCIe v3.0 compliant interface running at Gen1 speeds. For the Bluetooth section, host interface options of a high-speed 4-wire UART and USB full-speed 12 Mbps are provided. The CYW4356 uses advanced design techniques and process technology to reduce active and idle power, and includes an embedded power management unit that simplifies the system power topology. In addition, the CYW4356 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms that ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. Coexistence support for external radios such as LTE cellular and GPS is provided via an external interface. As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved. This data sheet provides details on the functional, operational, and electrical characteristics for the Cypress CYW4356. It is intended for hardware design, application, and OEM engineers.

Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.

Table Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number BCM4356 BCM4330 BCM4356XKUBG BCM4356XKWBG

CYW4356 CYW4330 CYW4356XKUBG CYW4356XKWBG

Cypress Part Number
• San Jose, CA 95134-1709
• 408-943-2600

ADVANCE

CYW4356

Figure Functional Block Diagram

VIO VBAT

WLAN Host I/F

WL_REG_ON PCIe SDIO

External Coexistence I/F

COEX

Bluetooth Host I/F FM Rx Host I/F

CLK_REQ BT_REG_ON

UART USB

I2S PCM BT_DEV_WAKE BT_HOST_WAKE

FM I/F

FM Audio Out I2S
5G WLAN

T/R Switch
2G WLAN

T/R Switch

CYW4356
5G WLAN

T/R Switch
2G WLAN Tx 2.G WL/BT Rx 3PST Switch

BT Tx FM Rx

Ant1 Diplexer

Ant0 Diplexer

IEEE 802.11X Key Features
• IEEE 802.11ac Draft compliant.
• Dual-stream spatial multiplexing up to
867 Mbps data rate.
• Supports 20, 40, and 80 MHz channels with optional SGI 256

QAM modulation .
• Full IEEE 802.11a/b/g/n legacy compatibility with enhanced
performance.
• TX and RX low-density parity check LDPC support for
improved range and power efficiency.
• Supports IEEE 802.11ac/n beamforming.
• On-chip power amplifiers and low-noise amplifiers for both
bands.
• Supports various RF front-end architectures including:

Two antennas with one each dedicated to Bluetooth and WLAN.

Two antennas with WLAN diversity and a shared Bluetooth antenna.
• Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN.
Mechanical Information 149 Ordering Information 153

Additional Information 153 Acronyms and Abbreviations 153 References 153

IoT Resources 153 Document History 154 Sales, Solutions, and Legal Information 155

Page 5 of 155

ADVANCE

CYW4356

Overview

Overview The Cypress CYW4356 single-chip device provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE a/b/g/n/ac MAC/baseband/radio, Bluetooth + EDR enhanced data rate , FM receiver, and Alliance for Wireless Power A4WP support. The wireless charging feature works in collaboration with the Wireless Power Transfer WPT BCM59350 front-end IC. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the CYW4356 and their associated external interfaces, which are described in greater detail in the following sections.

Table Device Options and Features

Feature Package ball count PCIe USB2.0 Bluetooth I2S GPIO SDIO WPT BSC, GPIO SPROM

WLBGA 192 pins Yes Multiplexed onto six parallel Flash pins 11 Yes
395 bumps Yes No 16 Yes

WLCSP

Page 6 of 155

ADVANCE

Figure CYW4356 Block Diagram

CYW4356

FM RX BSC, GPIO

BT Digital IO

BT/FM

FMRX FM RF

FM Digital

Power

PTU UART/USB SLIMBus Debug UART MEIF I2S/PCM1

I2S/PCM2 GPIO

SMPS Control GNSS LNA ANT

Control Wake/Sleep

Control

IO Port Control

Debug

AHB Bus Matrix ETM JTAG SDP

Cortex M3

AHB2 APB Bridge APB

WD Timer SW Timer GPIO Ctrl

RAM ROM Patch Inter Ctrl DMA Bus Arb

BT PHY

BT RF

BTFM Control Clock

Sleep Timer

Clock Management

PMU Controller
SPI Interface The CYW4356 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates can be possible. The physical interface between the SPI master and the CYW4356 consists of the four SPI signals SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO and one interrupt signal SPI_INT . The SPI signals are muxed onto the UART signals, see Table The CYW4356 can be configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an activelow or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode and half-duplex handshaking is implemented between the SPI master and the CYW4356. The SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented in the higher layer protocols.

Table SPI to UART Signal Mapping

SPI_CLK SPI_CSB SPI_MISO SPI_MOSI SPI_INT

SPI Signals

UART_CTS_N UART_RTS_N UART_TXD UART_RXD BT_DEV_WAKE

UART Signals

SPI/UART Transport Detection The BT_HOST_WAKE BT_GPIO1 pin is also used for BT transport detection. The transport detection occurs during the power-up sequence. It selects either UART or SPI transport operation based on the following pin state
• If the BT_HOST_WAKE BT_GPIO1 pin is pulled low by an external pull-down during power-up, it selects the SPI transport interface.
• If the BT_HOST_WAKE BT_GPIO1 pin is not pulled low externally during power-up, then the default internal pull-up is detected
as a high and it selects the UART transport interface. When the A4WP feature is not used and USB is selected as the Bluetooth interface to the host, an external pull-up outside the chip 10 resistor to BT_VDDIO is required. The pull-up is not necessary but is recommended when the Bluetooth/host interface is UART instead of USB.

PCM Interface The CYW4356 supports two independent PCM interfaces that share the pins with the I2S interfaces. The PCM Interface on the CYW4356 can connect to linear PCM codec devices in master or slave mode. In master mode, the CYW4356 generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYW4356. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.

Slot Mapping The CYW4356 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot.

Frame Synchronization The CYW4356 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot.

Page 28 of 155

ADVANCE

CYW4356

Data Formatting The CYW4356 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYW4356 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

Wideband Speech Support When the host encodes Wideband Speech WBS packets in transparent mode, the encoded packets are transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16bit samples, resulting in a 64 Kbps bit rate. The CYW4356 also supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit data at 16 kHz 256 Kbps rate is transferred over the PCM bus.

Multiplexed Bluetooth and FM Over PCM In this mode of operation, the CYW4356 multiplexes both FM and Bluetooth audio PCM channels over the same interface, reducing the number of required I/Os. This mode of operation is initiated through an HCI command from the host. The format of the data stream consists of three channels a Bluetooth channel followed by two FM channels audio left and right . In this mode of operation, the bus data rate only supports 48 kHz operation per channel with 16 bits sent for each channel. This is done to allow the low data rate Bluetooth data to coexist in the same interface as the higher speed I2S data. To accomplish this, the Bluetooth data is repeated six times for 8 kHz data and three times for 16 kHz data. An initial sync pulse on the PCM_SYNC line is used to indicate the beginning of the frame. To support multiple Bluetooth audio streams within the Bluetooth channel, both 16 kHz and 8 kHz streams can be multiplexed. This mode of operation is only supported when the Bluetooth host is the master. Figure 12 shows the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased. To change between modes of operation, the transport must be halted and restarted in the new configuration.

Figure Functional Multiplex Data Diagram

BT SCO 1 Rx

BT SCO 2 Rx
1 Frame

BT SCO 3 Rx

PCM_OUT

BT SCO 1 Tx

BT SCO 2 Tx

BT SCO 3 Tx

FM Right

FM Left

PCM_IN

FM Right

FM Left

PCM_SYNC

PCM_CLK
16 bits per SCO frame

Each SCO channel duplicates the data 6 times. Each WBS frame duplicates the data three times per frame
16 bits per frame
16 bits per frame

Burst PCM Mode In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host.

Page 29 of 155

ADVANCE

PCM Interface Timing Short Frame Sync, Master Mode
Ordering Information

Part Number BCM4356XKUBG

BCM4356XKWBG

Package
192-ball WLBGA mm x mm, mm pitch 395-bump WLCSP mm x mm, mm pitch

Operating Ambient Temperature

Dual-band GHz and 5 GHz WLAN + BT to +85°C
+ FMRX + A4WP
to 185°F

Dual-band GHz and 5 GHz WLAN + BT to +85°C
+ FMRX + A4WP
to 185°F

Additional Information

Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Cypress documents, go to:

References The references in this section may be used in conjunction with this document. Note Cypress provides customer access to technical documentation and software through its Cypress Developer Community and Downloads and Support site see IoT Resources . For Cypress documents, replace the “xx” in the document number with the largest number available in the repository to ensure that you have the most current version of the document.

Document or Item Name

Bluetooth MWS Coexistence Transport Interface Specification

A4WP Wireless Power Transfer System Baseline System Specification BSS January 2, 2013

PCI Express CEM v2.0 Specification

Number

Source

IoT Resources

Cypress provides a wealth of data at to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website

Page 153 of 155

ADVANCE

CYW4356

Document History

Document Title CYW4356 Single-Chip 5G WiFi IEEE 802.11ac 2x2 MAC/Baseband/Radio with Integrated Bluetooth FM Receiver, and Wireless Charging Document Number 002-15053

Orig. of Change

Submission Date

Description of Change
04/01/2014 4356-DS100-R

Initial release
04/24/2014 4356-DS101-R
06/25/2014 4356-DS102-R

Updated:
• Pin name PCI_PME_L to PCIE_PME_L.
• “BCM4356 PMU Features”.
• Table 59 “PCI Express Interface Parameters”

Added:
• “Electrostatic Discharge Specifications”.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYW4356XKUBGT Datasheet file may be downloaded here without warranties.

Datasheet ID: CYW4356XKUBGT 508255