CYW4354XKUBGT

CYW4354XKUBGT Datasheet

CYW4354

Part	Datasheet
CYW4354XKUBGT	CYW4354XKUBGT (pdf)

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CYW4354 Single-Chip 5G Wi-Fi IEEE 802.11ac 2x2 MAC/Baseband/Radio with Integrated Bluetooth and FM Receiver The Cypress CYW4354 is a complete GHz and 5 GHz 5G 2 x 2 MAC/PHY/Radio This device provides a high level of integration with IEEE 802.11ac MAC/baseband/radio, Bluetooth and FM radio receiver. In IEEE 802.11ac mode, the WLAN operation supports rates of up to 256 QAM in 20 MHz, 40 MHz, and 80 MHz channels for data rates up to 867 Mbps. In addition, all the rates specified in IEEE 802.11a/b/g/n are supported. Included are GHz and 5 GHz transmit power amplifiers and receive low noise amplifiers. For the WLAN section, several alternative host interface options are included an SDIO v3.0 interface that can operate in 4b or 1b modes, a high-speed inter-chip HSIC interface, and a PCIe v3.0 compliant interface running at Gen1 speeds. For the Bluetooth section, host interface options of a high-speed 4-wire UART and USB full-speed 12 Mbps are provided. The CYW4354 uses advanced design techniques and process technology to reduce active and idle power, and includes an embedded power management unit that simplifies the system power topology. In addition, the CYW4354 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms that ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. Coexistence support for external radios such as LTE cellular and GPS is provided via an external interface. As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number BCM4354 BCM4354XKUBG BCM4354XKWBG BCM4354ZKUBG CYW4354 CYW4354XKUBG CYW4354XKWBG CYW4354ZKUBG Cypress Part Number • San Jose, CA 95134-1709 • 408-943-2600 CYW4354 IEEE 802.11X Key Features • IEEE 802.11ac Draft compliant. • spatial multiplexing up to 867 Mbps data rate. • Supports 20, 40, and 80 MHz channels with optional SGI 256 QAM modulation . • Full IEEE 802.11a/b/g/n legacy compatibility with enhanced performance. • TX and RX parity check LDPC support for improved range and power efficiency. • Supports IEEE 802.11ac/n beamforming. • power amplifiers and amplifiers for both bands. • Supports various RF architectures including: Two antennas with one each dedicated to Bluetooth and WLAN. Two antennas with WLAN diversity and a shared Bluetooth antenna. • Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN. • Internal fractional nPLL allows support for a wide range of reference clock frequencies • Supports IEEE external coexistence interface to optimize bandwidth utilization with other wireless. technologies such as LTE or GPS. • Supports standard SDIO v3.0 up to SDR104 mode at 208 MHz, and 1-bit host interfaces. • Backward compatible with SDIO v2.0 host interfaces. • Alternative host interface supports HSIC v1.0 • PCIe mode complies with PCI Express base specification Bluetooth and FM Key Features • Complies with Bluetooth Core Specification Version with provisions for supporting future specifications. • Bluetooth Class 1 or Class 2 transmitter operation. • Supports extended synchronous connections eSCO , for enhanced voice quality by allowing for retransmission of dropped packets. • Adaptive frequency hopping AFH for reducing radio frequency interference. • Interface support, host controller interface HCI using a USB or UART interface and PCM for audio data. • USB 12 Mbps supported for Bluetooth. • The FM unit supports HCI for communication. • Low power consumption improves battery life of handheld devices. • FM receiver 65 MHz to 108 MHz FM bands supports the European radio data systems RDS and the North American radio broadcast data system RBDS standards. • Supports multiple simultaneous Advanced Audio Distribution Profiles A2DP for stereo sound. • Automatic frequency detection for standard crystal and TCXO values. • Supports serial flash interfaces. General Features • Supports battery range from 3.0V to 5.25V supplies with internal switching regulator. • Programmable dynamic power management • 484 bytes of user-accessible OTP for storing board parameters • GPIOs 11 in WLBGA, 16 in WLCSP • Package options: 192-ball WLBGA mm x mm, mm pitch 395-bump WLCSP mm x mm, mm pitch • Security WPA and WPA2 Personal support for powerful encryp- tion and authentication AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility Reference WLAN subsystem provides Compatible Extensions CCX, CCX Reference WLAN subsystem provides Wi-Fi Protected Setup WPS • Worldwide regulatory support Global products supported with worldwide homologated design. Page 2 of 165 CYW4354 Figure Functional Block Diagram VBAT WLAN Host I/F External Coexistence I/F WL_REG_ON PCIe SDIO HSIC COEX Bluetooth Host I/F FM Rx Host I/F CLK_REQ BT_REG_ON UART USB Environmental Characteristics 157 Mechanical Information 158 Ordering Information 162 Document History 163 Page 5 of 165 CYW4354 Overview Overview The Cypress CYW4354 single-chip device provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE a/b/g/n/ac MAC/baseband/radio, Bluetooth + EDR enhanced data rate , and FM receiver. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 on page 7 shows the interconnect of all the major physical blocks in the CYW4354 and their associated external interfaces, which are described in greater detail in the following sections. Table Device Options and Features Feature Package ball count PCIe USB2.0 Bluetooth HSIC I2S GPIO SDIO WLBGA 192 pins Yes Multiplexed onto six parallel flash pins 11 Yes 395 bumps Yes No 16 Yes WLCSP Page 6 of 165 Figure CYW4354 Block Diagram CYW4354 FM RX BT Digital IO BT/FM FMRX FM RF FM Digital IO Port Control PTU UART SLIMBus Debug UART MEIF I2S/PCM1 I2S/PCM2 GPIO SMPS Control GNSS LNA ANT Control Wake/Sleep Control Coex Debug AHB Bus Matrix ETM JTAG SDP Cortex M3 AHB AHB2 APB Bridge APB WD Timer SW Timer GPIO Ctrl RAM ROM Patch Inter Ctrl DMA Bus Arb BT PHY BT RF BTFM Control Clock Sleep Timer Clock Management PMU Controller XO Buffer SPI Interface The CYW4354 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates can be possible. The physical interface between the SPI master and the CYW4354 consists of the four SPI signals SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO and one interrupt signal SPI_INT . The SPI signals are muxed onto the UART signals, see Table The CYW4354 can be configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an activelow or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode and half-duplex handshaking is implemented between the SPI master and the CYW4354. The SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented in the higher layer protocols. Table SPI to UART Signal Mapping SPI_CLK SPI_CSB SPI_MISO SPI_MOSI SPI_INT SPI Signals UART_CTS_N UART_RTS_N UART_TXD UART_RXD BT_DEV_WAKE UART Signals SPI/UART Transport Detection The BT_HOST_WAKE BT_GPIO1 pin is also used for BT transport detection. The transport detection occurs during the power-up sequence. It selects either UART or SPI transport operation based on the following pin state • If the BT_HOST_WAKE BT_GPIO1 pin is pulled low by an external pull-down during power-up, it selects the SPI transport interface. • If the BT_HOST_WAKE BT_GPIO1 pin is not pulled low externally during power-up, then the default internal pull-up is detected as a high and it selects the UART transport interface. PCM Interface The CYW4354 supports two independent PCM interfaces that share the pins with the I2S interfaces. The PCM Interface on the CYW4354 can connect to linear PCM Codec devices in master or slave mode. In master mode, the CYW4354 generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYW4354. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands. Slot Mapping The CYW4354 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. Frame Synchronization The CYW4354 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. Page 29 of 165 CYW4354 Data Formatting The CYW4354 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYW4354 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first. Wideband Speech Support When the host encodes Wideband Speech WBS packets in transparent mode, the encoded packets are transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16bit samples, resulting in a 64 Kbps bit rate. The CYW4354 also supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit data at 16 kHz 256 Kbps rate is transferred over the PCM bus. Multiplexed Bluetooth and FM Over PCM In this mode of operation, the CYW4354 multiplexes both FM and Bluetooth audio PCM channels over the same interface, reducing the number of required I/Os. This mode of operation is initiated through an HCI command from the host. The format of the data stream consists of three channels a Bluetooth channel followed by two FM channels audio left and right . In this mode of operation, the bus data rate only supports 48 kHz operation per channel with 16 bits sent for each channel. This is done to allow the low data rate Bluetooth data to coexist in the same interface as the higher speed I2S data. To accomplish this, the Bluetooth data is repeated six times for 8 kHz data and three times for 16 kHz data. An initial sync pulse on the PCM_SYNC line is used to indicate the beginning of the frame. To support multiple Bluetooth audio streams within the Bluetooth channel, both 16 kHz and 8 kHz streams can be multiplexed. This mode of operation is only supported when the Bluetooth host is the master. Figure 9 shows the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased. To change between modes of operation, the transport must be halted and restarted in the new configuration. Figure Functional Multiplex Data Diagram BT SCO 1 Rx BT SCO 2 Rx 1 Frame BT SCO 3 Rx PCM_OUT BT SCO 1 Tx BT SCO 2 Tx BT SCO 3 Tx FM Right FM Left PCM_IN FM Right FM Left PCM_SYNC PCM_CLK 16 bits per SCO frame Each SCO channel duplicates the data 6 times. Each WBS frame duplicates the data three times per frame 16 bits per frame 16 bits per frame Burst PCM Mode In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host. Page 30 of 165 PCM Interface Timing Short Frame Sync, Master Mode Figure PCM Timing Diagram Short Frame Sync, Master Mode PCM_BCLK Ordering Information CYW4354XKUBG CYW4354XKWBG CYW4354ZKUBG Package 192-ball WLBGA mm x mm, mm pitch 395-bump WLCSP mm x mm, mm pitch 192-ball WLBGA mm x mm, mm pitch CYW4354 Description Dual-band GHz and 5 GHz WLAN + BT + FMRX Operating Ambient Temperature to +85°C to 185°F Dual-band GHz and 5 GHz WLAN + BT + FMRX to +85°C to 185°F Dual-band GHz and 5 GHz WLAN to +85°C to 185°F Page 162 of 165 CYW4354 Document History Document Title CYW4354 Single-Chip 5G Wi-Fi IEEE 802.11ac 2x2 MAC/Baseband/Radio with Integrated Bluetooth and FM Receiver Document Number 002-14809 Orig. of Change Submission Date Description of Change 07/31/13 4354-DS100-R Initial Release 4354-DS101-R 11/06/13 Updated • Section 2 “Power Supplies and Power Management,” on page • “WLAN Power Management” on page • “Crystal Interface and Clock Generation” on page • Table 4 “Crystal Oscillator and External Clock Requirements and Performance,” on page 33 Frequency conditions. • Figure 7 “Startup Signaling Sequence,” on page • “Receiver Path” on page • “Transmit Path” on page • Section 13 “Pinout and Signal Descriptions,” on page • Table 29 “GPIO Alternative Signal Functions,” on page • Table 34 “Recommended Operating Conditions and DC Characteristics,” on page 142 DC supply voltage for digital I/O minimum value . • Table 42 “WLAN GHz Receiver Performance Specifications,” on page 163 SISO/MIMO RX sensitivity. • Table 46 “WLAN 5 GHz Receiver Performance Specifications,” on page 180: SISO/MIMO RX sensitivity. • Table 51 “LDO3P3 Specifications,” on page • Table 57 “Typical WLAN Power Consumption,” on page • Table 58 “Bluetooth BLE and FM Current Consumption,” on page • Section 22 “Package Information,” on page • Section 23 “Mechanical Information,” on page • Section 24 “Ordering Information,” on page Added • Figure 4 “Typical Power Topology for the CYW435X,” on page • “External kHz Low-Power Oscillator” on page • Table 30 “GPIO Status Vs. Test Modes,” on page • Table 52 “LDO3P3_B Specifications,” on page 4354-DS102-R 12/12/13 Updated: • The CYW4354 now supports PCI Express base specification v3.0 running at Gen1 speeds. • “WLAN GHz Receiver Performance Specifications” on page 158 Note update. • “WLAN GHz Transmitter Performance Specifications” on page 170 Note update. • “WLAN 5 GHz Receiver Performance Specifications” on page 174 Note update. • “WLAN 5 GHz Transmitter Performance Specifications” on page 187 Note update. • “Package Thermal Characteristics” on page 219 Note update. • Section 24 “Ordering Information,” on page 4354-DS103-R 12/20/13 Updated: • Table 33 “Environmental Ratings,” on page 141 Ambient temperature range for functional operation is now to +85°C. Page 163 of 165 CYW4354 Document Title CYW4354 Single-Chip 5G Wi-Fi IEEE 802.11ac 2x2 MAC/Baseband/Radio with Integrated Bluetooth and FM Receiver Document Number 002-14809 4354-DS104-R Updated: • Table 4 “External kHz Sleep Clock Specifications,” on page 28 • Figure 33 “WLBGA Ball Map, x Array, 192-Balls, Bottom 03/24/14 View Balls Facing Up ,” on page 83 • Table 20 “395-Bump WLCSP Coordinates,” on page 90 Modified Bump 230, see note at end of the Table • Table 32 “Bluetooth Receiver RF Specifications,” on page 129 footnotes modified Table 50 “Bluetooth BLE and FM Current Consumption,” on page 167 4354-DS105-R Updated: • Table 4 “External kHz Sleep Clock Specifications,” on page 28 • Figure 34 “WLBGA Ball Map, x Array, 192-Ball, Bottom View Balls Facing Up ,” on page 84 • Table 49 “Bluetooth BLE and FM Current Consumption,” on page 164 • “Receiver Path” on page 80 04/02/14 • Figure 32 “Radio Functional Block Diagram core 0 ,” on page 81 • Table 38 “WLAN GHz Receiver Performance Specifications,” on page 139 • Table 39 “WLAN GHz Transmitter Performance Specifications,” on page • Table 40 “WLAN 5 GHz Receiver Performance Specifications,” on page 147 • Table 41 “WLAN 5 GHz Transmitter Performance Specifications,” on page • General Spurious Emissions Specifications deleted 4354-DS106-R 05/20/14 Updated: Section 24 “Ordering Information,” on page 4354-DS107-R Updated • “CYW4354 PMU Features” on page 22 • Figure 3 “Typical Power Topology for the CYW4354,” on page 23 • Table 18 “Pin List by Pin Number 192-Pin WLBGA Package ,” on page 85 06/30/14 • Table 19 “Pin List by Pin Name 192-Pin WLBGA Package ,” on page 88 • Table 20 “395-Bump WLCSP Coordinates,” on page 91 • Table 21 “WLCSP Signal Descriptions,” on page 102 • Table 60 “PCI Express Interface Parameters,” on page 175 Added • “Electrostatic Discharge Specifications” on page 124 4354-DS108-R 08/08/14 Updated: Changed document type from “Preliminary Data Sheet” to “Data Sheet”. 4354-DS109-R 10/15/14 Updated • “I/O States” on page <Cross-Ref>Figure 52 “WLBGA Keep-Out Areas for PCB Layout Top View, Balls Facing Down ,” on page 5451155 UTSV 09/28/16 Converted to Cypress Template Page 164 of 165 CYW4354 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Microcontrollers cypress.com/arm PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP Automotive Clocks & Buffers Interface Internet of Things Lighting & Power Control Memory cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/powerpsoc cypress.com/memory Cypress Developer Community Forums \| WICED IoT Forums \| Projects \| Video \| Blogs \| Training \| Components Technical Support cypress.com/support PSoC cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless/RF

PDF Datasheet Preview

CYW4354

Single-Chip 5G Wi-Fi IEEE 802.11ac 2x2 MAC/Baseband/Radio with Integrated Bluetooth and FM Receiver

The Cypress CYW4354 is a complete GHz and 5 GHz 5G 2 x 2 MAC/PHY/Radio This device provides a high level of integration with IEEE 802.11ac MAC/baseband/radio, Bluetooth and FM radio receiver. In IEEE 802.11ac mode, the WLAN operation supports rates of up to 256 QAM in 20 MHz, 40 MHz, and 80 MHz channels for data rates up to 867 Mbps. In addition, all the rates specified in IEEE 802.11a/b/g/n are supported. Included are GHz and 5 GHz transmit power amplifiers and receive low noise amplifiers. For the WLAN section, several alternative host interface options are included an SDIO v3.0 interface that can operate in 4b or 1b modes, a high-speed inter-chip HSIC interface, and a PCIe v3.0 compliant interface running at Gen1 speeds. For the Bluetooth section, host interface options of a high-speed 4-wire UART and USB full-speed 12 Mbps are provided. The CYW4354 uses advanced design techniques and process technology to reduce active and idle power, and includes an embedded power management unit that simplifies the system power topology. In addition, the CYW4354 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms that ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. Coexistence support for external radios such as LTE cellular and GPS is provided via an external interface. As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved.

Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.

Table Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number BCM4354 BCM4354XKUBG BCM4354XKWBG BCM4354ZKUBG

CYW4354 CYW4354XKUBG CYW4354XKWBG CYW4354ZKUBG

Cypress Part Number
• San Jose, CA 95134-1709
• 408-943-2600

CYW4354

IEEE 802.11X Key Features
• IEEE 802.11ac Draft compliant.
• spatial multiplexing up to 867 Mbps data rate.
• Supports 20, 40, and 80 MHz channels with optional SGI 256

QAM modulation .
• Full IEEE 802.11a/b/g/n legacy compatibility with enhanced
performance.
• TX and RX parity check LDPC support for
improved range and power efficiency.
• Supports IEEE 802.11ac/n beamforming.
• power amplifiers and amplifiers for both
bands.
• Supports various RF architectures including:

Two antennas with one each dedicated to Bluetooth and WLAN.

Two antennas with WLAN diversity and a shared Bluetooth antenna.
• Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN.
• Internal fractional nPLL allows support for a wide range of reference clock frequencies
• Supports IEEE external coexistence interface to optimize bandwidth utilization with other wireless. technologies such as LTE or GPS.
• Supports standard SDIO v3.0 up to SDR104 mode at 208 MHz, and 1-bit host interfaces.
• Backward compatible with SDIO v2.0 host interfaces.
• Alternative host interface supports HSIC v1.0
• PCIe mode complies with PCI Express base specification

Bluetooth and FM Key Features
• Complies with Bluetooth Core Specification Version with
provisions for supporting future specifications.
• Bluetooth Class 1 or Class 2 transmitter operation.
• Supports extended synchronous connections eSCO , for
enhanced voice quality by allowing for retransmission of dropped packets.
• Adaptive frequency hopping AFH for reducing radio frequency interference.
• Interface support, host controller interface HCI using a USB or UART interface and PCM for audio data.
• USB 12 Mbps supported for Bluetooth.
• The FM unit supports HCI for communication.
• Low power consumption improves battery life of handheld devices.
• FM receiver 65 MHz to 108 MHz FM bands supports the European radio data systems RDS and the North American radio broadcast data system RBDS standards.
• Supports multiple simultaneous Advanced Audio Distribution Profiles A2DP for stereo sound.
• Automatic frequency detection for standard crystal and TCXO values.
• Supports serial flash interfaces.

General Features
• Supports battery range from 3.0V to 5.25V supplies with
internal switching regulator.
• Programmable dynamic power management
• 484 bytes of user-accessible OTP for storing board parameters
• GPIOs 11 in WLBGA, 16 in WLCSP
• Package options:
192-ball WLBGA mm x mm, mm pitch 395-bump WLCSP mm x mm, mm pitch
• Security WPA and WPA2 Personal support for powerful encryp-
tion and authentication AES and TKIP in hardware for faster data encryption and

IEEE 802.11i compatibility Reference WLAN subsystem provides Compatible

Extensions CCX, CCX Reference WLAN subsystem provides Wi-Fi Protected Setup

WPS
• Worldwide regulatory support Global products supported with
worldwide homologated design.

Page 2 of 165

CYW4354

Figure Functional Block Diagram

VBAT

WLAN Host I/F

External Coexistence I/F

WL_REG_ON PCIe SDIO HSIC

COEX

Bluetooth Host I/F FM Rx Host I/F

CLK_REQ BT_REG_ON

UART USB
Environmental Characteristics 157 Mechanical Information 158 Ordering Information 162 Document History 163

Page 5 of 165

CYW4354

Overview

Overview

The Cypress CYW4354 single-chip device provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE a/b/g/n/ac MAC/baseband/radio, Bluetooth + EDR enhanced data rate , and FM receiver. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation.

Figure 2 on page 7 shows the interconnect of all the major physical blocks in the CYW4354 and their associated external interfaces, which are described in greater detail in the following sections.

Table Device Options and Features

Feature Package ball count PCIe USB2.0 Bluetooth HSIC I2S GPIO SDIO

WLBGA 192 pins Yes Multiplexed onto six parallel flash pins 11 Yes
395 bumps Yes No 16 Yes

WLCSP

Page 6 of 165

Figure CYW4354 Block Diagram

CYW4354

FM RX BT Digital IO

BT/FM

FMRX FM RF

FM Digital

IO Port Control

PTU UART

SLIMBus Debug UART

MEIF

I2S/PCM1

I2S/PCM2

GPIO SMPS Control

GNSS LNA ANT Control

Wake/Sleep Control Coex

Debug

AHB Bus Matrix ETM JTAG SDP

Cortex M3 AHB

AHB2 APB Bridge APB

WD Timer SW Timer GPIO Ctrl

RAM ROM Patch Inter Ctrl DMA Bus Arb

BT PHY

BT RF

BTFM Control Clock

Sleep Timer

Clock Management

PMU Controller

XO Buffer
SPI Interface The CYW4354 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates can be possible. The physical interface between the SPI master and the CYW4354 consists of the four SPI signals SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO and one interrupt signal SPI_INT . The SPI signals are muxed onto the UART signals, see Table The CYW4354 can be configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an activelow or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode and half-duplex handshaking is implemented between the SPI master and the CYW4354. The SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented in the higher layer protocols.

Table SPI to UART Signal Mapping

SPI_CLK SPI_CSB SPI_MISO SPI_MOSI SPI_INT

SPI Signals

UART_CTS_N UART_RTS_N UART_TXD UART_RXD BT_DEV_WAKE

UART Signals

SPI/UART Transport Detection The BT_HOST_WAKE BT_GPIO1 pin is also used for BT transport detection. The transport detection occurs during the power-up sequence. It selects either UART or SPI transport operation based on the following pin state
• If the BT_HOST_WAKE BT_GPIO1 pin is pulled low by an external pull-down during power-up, it selects the SPI transport interface.
• If the BT_HOST_WAKE BT_GPIO1 pin is not pulled low externally during power-up, then the default internal pull-up is detected
as a high and it selects the UART transport interface.

PCM Interface The CYW4354 supports two independent PCM interfaces that share the pins with the I2S interfaces. The PCM Interface on the CYW4354 can connect to linear PCM Codec devices in master or slave mode. In master mode, the CYW4354 generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYW4354. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.

Slot Mapping The CYW4354 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot.

Frame Synchronization The CYW4354 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot.

Page 29 of 165

CYW4354

Data Formatting The CYW4354 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYW4354 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

Wideband Speech Support When the host encodes Wideband Speech WBS packets in transparent mode, the encoded packets are transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16bit samples, resulting in a 64 Kbps bit rate. The CYW4354 also supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit data at 16 kHz 256 Kbps rate is transferred over the PCM bus.

Multiplexed Bluetooth and FM Over PCM In this mode of operation, the CYW4354 multiplexes both FM and Bluetooth audio PCM channels over the same interface, reducing the number of required I/Os. This mode of operation is initiated through an HCI command from the host. The format of the data stream consists of three channels a Bluetooth channel followed by two FM channels audio left and right . In this mode of operation, the bus data rate only supports 48 kHz operation per channel with 16 bits sent for each channel. This is done to allow the low data rate Bluetooth data to coexist in the same interface as the higher speed I2S data. To accomplish this, the Bluetooth data is repeated six times for 8 kHz data and three times for 16 kHz data. An initial sync pulse on the PCM_SYNC line is used to indicate the beginning of the frame. To support multiple Bluetooth audio streams within the Bluetooth channel, both 16 kHz and 8 kHz streams can be multiplexed. This mode of operation is only supported when the Bluetooth host is the master. Figure 9 shows the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased. To change between modes of operation, the transport must be halted and restarted in the new configuration.

Figure Functional Multiplex Data Diagram

BT SCO 1 Rx

BT SCO 2 Rx
1 Frame

BT SCO 3 Rx

PCM_OUT

BT SCO 1 Tx

BT SCO 2 Tx

BT SCO 3 Tx

FM Right

FM Left

PCM_IN

FM Right

FM Left

PCM_SYNC

PCM_CLK
16 bits per SCO frame

Each SCO channel duplicates the data 6 times. Each WBS frame duplicates the data three times per frame
16 bits per frame
16 bits per frame

Burst PCM Mode In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host.

Page 30 of 165

PCM Interface Timing Short Frame Sync, Master Mode

Figure PCM Timing Diagram Short Frame Sync, Master Mode

PCM_BCLK
Ordering Information

CYW4354XKUBG

CYW4354XKWBG

CYW4354ZKUBG

Package
192-ball WLBGA mm x mm, mm pitch 395-bump WLCSP mm x mm, mm pitch 192-ball WLBGA mm x mm, mm pitch

CYW4354

Description Dual-band GHz and 5 GHz WLAN + BT + FMRX

Operating Ambient Temperature
to +85°C to 185°F

Dual-band GHz and 5 GHz WLAN + BT + FMRX
to +85°C to 185°F

Dual-band GHz and 5 GHz WLAN
to +85°C to 185°F

Page 162 of 165

CYW4354

Document History

Document Title CYW4354 Single-Chip 5G Wi-Fi IEEE 802.11ac 2x2 MAC/Baseband/Radio with Integrated Bluetooth and FM Receiver Document Number 002-14809

Orig. of Change

Submission Date

Description of Change
07/31/13
4354-DS100-R Initial Release
4354-DS101-R
11/06/13

Updated
• Section 2 “Power Supplies and Power Management,” on page
• “WLAN Power Management” on page
• “Crystal Interface and Clock Generation” on page
• Table 4 “Crystal Oscillator and External Clock Requirements and

Performance,” on page 33 Frequency conditions.
• Figure 7 “Startup Signaling Sequence,” on page
• “Receiver Path” on page
• “Transmit Path” on page
• Section 13 “Pinout and Signal Descriptions,” on page
• Table 29 “GPIO Alternative Signal Functions,” on page
• Table 34 “Recommended Operating Conditions and DC Characteristics,” on
page 142 DC supply voltage for digital I/O minimum value .
• Table 42 “WLAN GHz Receiver Performance Specifications,” on page
163 SISO/MIMO RX sensitivity.
• Table 46 “WLAN 5 GHz Receiver Performance Specifications,” on page 180:
SISO/MIMO RX sensitivity.
• Table 51 “LDO3P3 Specifications,” on page
• Table 57 “Typical WLAN Power Consumption,” on page
• Table 58 “Bluetooth BLE and FM Current Consumption,” on page
• Section 22 “Package Information,” on page
• Section 23 “Mechanical Information,” on page
• Section 24 “Ordering Information,” on page

Added
• Figure 4 “Typical Power Topology for the CYW435X,” on page
• “External kHz Low-Power Oscillator” on page
• Table 30 “GPIO Status Vs. Test Modes,” on page
• Table 52 “LDO3P3_B Specifications,” on page
4354-DS102-R
12/12/13

Updated:
• The CYW4354 now supports PCI Express base specification v3.0 running at Gen1 speeds.
• “WLAN GHz Receiver Performance Specifications” on page 158 Note update.
• “WLAN GHz Transmitter Performance Specifications” on page 170 Note update.
• “WLAN 5 GHz Receiver Performance Specifications” on page 174 Note update.
• “WLAN 5 GHz Transmitter Performance Specifications” on page 187 Note update.
• “Package Thermal Characteristics” on page 219 Note update.
• Section 24 “Ordering Information,” on page
4354-DS103-R
12/20/13

Updated:
• Table 33 “Environmental Ratings,” on page 141 Ambient temperature range
for functional operation is now to +85°C.

Page 163 of 165

CYW4354

Document Title CYW4354 Single-Chip 5G Wi-Fi IEEE 802.11ac 2x2 MAC/Baseband/Radio with Integrated Bluetooth and FM Receiver Document Number 002-14809
4354-DS104-R

Updated:
• Table 4 “External kHz Sleep Clock Specifications,” on page 28
• Figure 33 “WLBGA Ball Map, x Array, 192-Balls, Bottom
03/24/14

View Balls Facing Up ,” on page 83
• Table 20 “395-Bump WLCSP Coordinates,” on page 90 Modified Bump 230,
see note at end of the Table
• Table 32 “Bluetooth Receiver RF Specifications,” on page 129 footnotes
modified

Table 50 “Bluetooth BLE and FM Current Consumption,” on page 167
4354-DS105-R

Updated:
• Table 4 “External kHz Sleep Clock Specifications,” on page 28
• Figure 34 “WLBGA Ball Map, x Array, 192-Ball, Bottom

View Balls Facing Up ,” on page 84
• Table 49 “Bluetooth BLE and FM Current Consumption,” on page 164
• “Receiver Path” on page 80
04/02/14
• Figure 32 “Radio Functional Block Diagram core 0 ,” on page 81
• Table 38 “WLAN GHz Receiver Performance Specifications,” on page 139
• Table 39 “WLAN GHz Transmitter Performance Specifications,” on page
• Table 40 “WLAN 5 GHz Receiver Performance Specifications,” on page 147
• Table 41 “WLAN 5 GHz Transmitter Performance Specifications,” on page
• General Spurious Emissions Specifications deleted
4354-DS106-R
05/20/14

Updated:
Section 24 “Ordering Information,” on page
4354-DS107-R

Updated
• “CYW4354 PMU Features” on page 22
• Figure 3 “Typical Power Topology for the CYW4354,” on page 23
• Table 18 “Pin List by Pin Number 192-Pin WLBGA Package ,” on page 85
06/30/14
• Table 19 “Pin List by Pin Name 192-Pin WLBGA Package ,” on page 88
• Table 20 “395-Bump WLCSP Coordinates,” on page 91
• Table 21 “WLCSP Signal Descriptions,” on page 102
• Table 60 “PCI Express Interface Parameters,” on page 175

Added
• “Electrostatic Discharge Specifications” on page 124
4354-DS108-R
08/08/14

Updated:

Changed document type from “Preliminary Data Sheet” to “Data Sheet”.
4354-DS109-R
10/15/14

Updated
• “I/O States” on page
<Cross-Ref>Figure 52 “WLBGA Keep-Out Areas for PCB Layout Top View,

Balls Facing Down ,” on page
5451155 UTSV 09/28/16

Converted to Cypress Template

Page 164 of 165

CYW4354

Sales, Solutions, and Legal Information

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYW4354XKUBGT Datasheet file may be downloaded here without warranties.

Datasheet ID: CYW4354XKUBGT 508254