CYW20715A1KUBXGT

CYW20715A1KUBXGT Datasheet

 CYW20715

Part	Datasheet
CYW20715A1KUBXGT	CYW20715A1KUBXGT (pdf)

PDF Datasheet Preview
 CYW20715 Single-Chip Bluetooth Transceiver and Baseband Processor The Cypress CYW20715 is a monolithic, single-chip, Bluetooth compliant, stand-alone baseband processor with an integrated GHz transceiver. Manufactured using the industry's most advanced 65 nm CMOS low-power process, the CYW20715 employs the highest level of integration, eliminating all critical external components, and thereby minimizing the device’s footprint and costs associated with the implementation of Bluetooth solutions. The CYW20715 is the optimal solution for voice and data applications that require a Bluetooth SIG standard Host Controller Interface HCI via UART H4 or H5 and PCM audio interface support. The CYW20715 radio transceiver’s enhanced radio performance meets the most stringent commercial temperature application requirements for compact integration into mobile handset and portable devices. The CYW20715 is fully compatible with all standard TCXO frequencies and provides full radio compatibility, enabling it to operate simultaneously with GPS and cellular radios. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number BCM20715 BCM20715A1KUBXG Cypress Part Number CYW20715 CYW20715A1KUBXG • Bluetooth + EDR compliant • Class 1 capable with built-in PA • Programmable output power control meets Class 1, Class 2, or Class 3 requirements • Use supply voltages up to 5.5V • Supports Cypress wide-band speech, SBC codec, and packet loss concealment. • Fractional-N synthesizer supports frequency references from 12 MHz to 52 MHz • Automatic frequency detection for standard crystal and TCXO values when an external kHz reference clock is provided. • Ultra-low power consumption • Supports serial flash interfaces • Available in 42-bump WLBGA package. • microprocessor with integrated ROM and RAM • Supports mobile without external memory • Mobile handsets and smart phones • Personal digital assistants • San Jose, CA 95134-1709 • 408-943-2600 PCM UART GPIO Memory SPI I2S TCXO LPO CYW20715 Figure System Block Diagram CYW20715 Peripheral Transport Unit PTU Radio Transceiver Microprocessor and Memory Unit uPU Bluetooth Baseband Core BBC Page 2 of 47 CYW20715 Contents Overview 4 Major Features 4 Block Diagram 6 Mobile Phone Usage Model 7 Integrated Radio Transceiver 8 Transmitter Path 8 Receiver Path 8 Local Oscillator Generation 8 Calibration 8 Internal LDO 9 Bluetooth Baseband Core 10 Transmit and Receive Functions 10 Bluetooth + EDR Features 10 Frequency Hopping Generator 11 Link Control Layer 11 Test Mode Support 11 Power Management Unit 11 Adaptive Frequency Hopping 13 Collaborative Coexistence 13 Serial Enhanced Coexistence Interface 14 Microprocessor Unit 15 NVRAM Configuration Data and Storage 15 EEPROM 15 External Reset 15 One-Time Programmable Memory 16 Peripheral Transport Unit 17 PCM Interface 17 HCI Transport Detection Configuration 19 UART Interface 19 SPI 20 Frequency References 21 Crystal Interface and Clock Generation 21 Crystal Oscillator 22 External Frequency Reference 22 Frequency Selection 23 Frequency Trimming 23 LPO Clock Interface 24 Pinout and Signal Descriptions 25 Pin Descriptions 25 Ball Grid Arrays 27 Electrical Characteristics 28 RF Specifications 33 Timing and AC Characteristics 36 Mechanical Information 43 Tape, Reel, and Packing Specification 44 Ordering Information 45 Document History 46 Page 3 of 38 CYW20715 Overview The Cypress CYW20715 complies with the Bluetooth Core Specification, version and is designed for use with a standard Host Controller Interface HCI UART. The combination of the Bluetooth Baseband Core BBC , a Peripheral Transport Unit PTU , and an microprocessor with on-chip ROM provides a complete lower layer Bluetooth protocol stack, including the Link Controller LC , Link Manager LM , and HCI. Major Features Major features of the CYW20715 include: • Support for Bluetooth + EDR, including the following options A whitelist size of Enhanced Power Control HCI Read Encryption Key Size command • Full support for Bluetooth + EDR additional features Secure Simple Pairing SSP Encryption Pause Resume EPR Enhance Inquiry Response EIR Link Supervision Time Out LSTO Sniff SubRating SSR Erroneous Data ED Packet Boundary Flag PBF • Built-in Low Drop-Out LDO regulators 2 to 5.5V input voltage range to 3.3V intermediate programmable output voltage • Integrated RF section Single-ended, RF interface Built-in TX/RX switch functionality TX Class 1 output power capability dBm RX sensitivity basic rate • Supports maximum Bluetooth data rates over HCI UART and SPI interfaces • Multipoint operation, with up to seven active slaves Maximum of seven simultaneous active ACL links Maximum of three simultaneous active SCO and eSCO links, with Scatternet support • Scatternet operation, with up to four active piconets with background scan and support for ScatterMode • High-speed HCI UART transport support H4 five-wire UART four signal wires, one ground wire H5 three-wire UART two signal wires, one ground wire Maximum UART baud rates of 4 Mbps Low-power out-of-band BT_WAKE and HOST_WAKE signaling VSC from host transport to UART Proprietary compressing scheme allows more than two simultaneous A2DP packets and up to five devices at a time • Channel Quality-Driven Data Rate CQDDR and packet type selection • Standard Bluetooth test modes • Extended radio and production test mode features • Full support for power savings modes Bluetooth standard Hold and Sniff Deep sleep modes and regulator shutdown Page 4 of 47 CYW20715 • Supports Wide-Band Speech WBS over PCM and Packet Loss Concealment PLC for better audio quality • 2-, 3-, and 4-wire coexistence • Power Amplifier PA shutdown for externally controlled coexistence, such as WIMAX • Built-in LPO clock or operation using an external LPO clock • TCXO input and auto-detection of all standard handset clock frequencies supports low-power crystal, which can be used during Power Saving mode with better timing accuracy • OR gate for combining a host clock request with a Bluetooth clock request operates even when the Bluetooth core logic is powered off • Larger patch RAM space to support future enhancements • Serial flash Interface with native support for devices from several manufacturers • One-Time Programmable OTP memory Page 5 of 47 Block Diagram Figure 2 shows the interconnect of the major CYW20715 physical blocks and associated external interfaces. Figure Functional Block Diagram CYW20715 JTAG Flash Address Decoder AHB2EBI External Bus I/F Trap & Patch AHB2APB AHB2MEM AHB2MEM PMU Control WD Timer GPIO+Aux Remap & Pause SW Timers ROM 384 KB RAM 112 KB HCI 3-Wire Transport UART H5 The CYW20715 supports H5 UART transport for serial UART communications. H5 reduces the number of signal lines required by eliminating CTS and RTS, when compared to H4. In addition, in-band sleep signaling is supported over the same interface so that the 4-wire UART and the 2-wire sleep signaling interface can be reduced to a 2-wire UART interface, saving four I/Os on the host. H5 requires the use of an external LPO. CTS must be pulled low. SPI The CYW20715 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates may be possible. The physical interface between the SPI master and the CYW20715 consists of the four SPI signals SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO and one interrupt signal SPI_INT . The CYW20715 can be configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an active-low or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode, halfduplex handshaking is implemented between the SPI master and the CYW20715. SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented in higher layer protocols. Page 20 of 47 CYW20715 Frequency References The CYW20715 uses two different frequency references for normal and low-power operational modes. An external crystal or frequency reference driven by a Temperature Compensated Crystal Oscillator TCXO signal is used to generate the radio frequencies and normal operation clocking. Either an external kHz or fully integrated internal Low-Power Oscillator LPO is used for lowpower mode timing. Crystal Interface and Clock Generation The CYW20715 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing, enabling it to operate from any of a multitude of frequency sources. The source can be external, such as a TCXO, or a crystal interfaced directly to the device. The default frequency reference setting is for a 20 MHz crystal or TCXO. The signal characteristics for the crystal interface are listed in Table Crystal Interface Signal Characteristics Parameter Acceptable frequencies Crystal load capacitance ESR Power dissipation Input signal amplitude Signal type Input impedance Phase noise 1 kHz 10 kHz 100 kHz 1 MHz Auto-detection frequencies when using external LPOc Tolerance without frequency trimmingd Initial frequency tolerance trimming range Crystal MHz in 2 ppma steps External Frequency Reference MHz in 2 ppma steps Units 12 typical 60 max 200 max 400 to 2000 mVp-p 2000 to 3300 requires a 10 pF DC blocking capacitor to attenuate the signal Square-wave or sine-wave dBc/Hz dBc/Hz dBc/Hz dBc/Hz 12, 13, 18, 12, 13, 18, 20, 24, 20, 24, 26, 26, and ±20 ±20 ±50 ±50 a. The frequency step size is approximately 80 Hz resolution. b. With a 26 MHz reference clock. For a 13 MHz clock, subtract 6 dB. For a 52 MHz clock, add 6 dB. c. Auto-detection of the frequency requires the crystal or external frequency reference to have less than ±50 ppm of variation and also requires an external LPO frequency which has less than ±250 ppm of variation at the time of detection. d. AT-Cut crystal or TXCO recommended. Page 21 of 47 CYW20715 Crystal Oscillator The CYW20715 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator, including all external components, is shown in Figure Figure Recommended Oscillator Configuration 0 to 18 pF* Crystal Oscillator XOUT 0 to 18 pF* *Capacitor value range depends on the manufacturer of the XTAL as well as board layout. GPIO/CLK_REQ TCXO-OR Function Out available on some packages. See Ordering Information on page VDDO GPIO TCXO-OR Function In available on some packages. See Ordering Information on page VDDO DETATCH/CARD_DETECT VDDO UART receive data VDDO UART transmit data VDDO UART request to send output VDDO UART clear to send input I2C clock I2C data VDDO Serial flash SPI clock VDDO Serial flash active-low chip select VDDO PCM/I2S data input Page 25 of 47 CYW20715 Table CYW20715 Signal Descriptions Cont. Signal PCM_OUT PCM_CLK PCM_SYNC COEX_IN COEX_OUT0 COEX_OUT1 OTP_DIS WLBGA 42-Bump E4 C4 A4 A2 Power Domain VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDTF VDDRF VDDPX VDDC VDDO NC VSS PCM/I2S data output PCM/I2S clock PCM sync/I2S word select Coexistence input Coexistence output Coexistence output OTP disable pin. By default, leave this pin floating. Supplies Radio PA supply Radio supply Radio RF PLL supply Core logic supply Core logic supply Digital I/O supply voltage No connect Ground Page 26 of 47 Ball Grid Arrays Figure 8 shows the top view of the 42-bump, x mm array. Figure 42-Bump x mm Array Top View 1234567 A B C D E F CYW20715 Table Ball-Out for the 42-Bump CYW20715A1KUBXG A VSS B N/C SPIM_CLK D SDA E SCL F VDDC OTP_DIS VSS UART_TXD UART_RXD SPIM_CS_N UART_RTS_N VDDC GPIO_1 GPIO_0 VDDO UART_CTS_N VSS PCM_SYNC LPO_IN PCM_CLK PCM_IN PCM_OUT GPIO_5 VBAT REG_EN RST_N GPIO_6 XOUT XIN VREGHV VSS TM2 RES VSS Ordering Information Part Number CYW20715A1KUBXG Package Type Commercial 42-bump WLBGA, mm x mm x mm. See Figure 17 on page CYW20715 Temp. Rating to +85°C Page 45 of 47 Document History Document Title CYW20715 Single-Chip Bluetooth Transceiver and Baseband Processor Document Number 002-14813 Orig. of Submission Change Description of Change 08/23/2013 20715-DS100-R Initial release 20715-DS101-R: 10/04/2013 Updated • UART Interface on page 19 supported baud rates. • Table 12 on page 5452890 UTSV 09/29/2016 Updated to Cypress Template CYW20715 Page 46 of 47 CYW20715 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Microcontrollers cypress.com/arm PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP Automotive Clocks & Buffers Interface Internet of Things Lighting & Power Control Memory cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/powerpsoc cypress.com/memory Cypress Developer Community Forums \| WICED IoT Forums \| Projects \| Video \| Blogs \| Training \| Components Technical Support cypress.com/support PSoC cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless/RF cypress.com/wireless

PDF Datasheet Preview

 CYW20715

Single-Chip Bluetooth Transceiver and Baseband Processor

The Cypress CYW20715 is a monolithic, single-chip, Bluetooth compliant, stand-alone baseband processor with an integrated GHz transceiver. Manufactured using the industry's most advanced 65 nm CMOS low-power process, the CYW20715 employs the highest level of integration, eliminating all critical external components, and thereby minimizing the device’s footprint and costs associated with the implementation of Bluetooth solutions. The CYW20715 is the optimal solution for voice and data applications that require a Bluetooth SIG standard Host Controller Interface HCI via UART H4 or H5 and PCM audio interface support. The CYW20715 radio transceiver’s enhanced radio performance meets the most stringent commercial temperature application requirements for compact integration into mobile handset and portable devices. The CYW20715 is fully compatible with all standard TCXO frequencies and provides full radio compatibility, enabling it to operate simultaneously with GPS and cellular radios.

Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.

Table Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number BCM20715 BCM20715A1KUBXG

Cypress Part Number CYW20715 CYW20715A1KUBXG
• Bluetooth + EDR compliant
• Class 1 capable with built-in PA
• Programmable output power control meets Class 1, Class 2,
or Class 3 requirements
• Use supply voltages up to 5.5V
• Supports Cypress wide-band speech, SBC
codec, and packet loss concealment.
• Fractional-N synthesizer supports frequency references from
12 MHz to 52 MHz
• Automatic frequency detection for standard crystal and TCXO values when an external kHz reference clock is provided.
• Ultra-low power consumption
• Supports serial flash interfaces
• Available in 42-bump WLBGA package.
• microprocessor with integrated ROM
and RAM
• Supports mobile without external memory
• Mobile handsets and smart phones
• Personal digital assistants
• San Jose, CA 95134-1709
• 408-943-2600

PCM UART GPIO Memory

SPI I2S

TCXO LPO

CYW20715

Figure System Block Diagram

CYW20715

Peripheral Transport Unit PTU

Radio Transceiver

Microprocessor and Memory Unit uPU

Bluetooth Baseband Core BBC

Page 2 of 47

CYW20715

Contents

Overview 4 Major Features 4 Block Diagram 6 Mobile Phone Usage Model 7

Integrated Radio Transceiver 8 Transmitter Path 8 Receiver Path 8 Local Oscillator Generation 8 Calibration 8 Internal LDO 9

Bluetooth Baseband Core 10 Transmit and Receive Functions 10 Bluetooth + EDR Features 10 Frequency Hopping Generator 11 Link Control Layer 11 Test Mode Support 11 Power Management Unit 11 Adaptive Frequency Hopping 13 Collaborative Coexistence 13 Serial Enhanced Coexistence Interface 14

Microprocessor Unit 15 NVRAM Configuration Data and Storage 15 EEPROM 15 External Reset 15

One-Time Programmable Memory 16 Peripheral Transport Unit 17
PCM Interface 17 HCI Transport Detection Configuration 19 UART Interface 19 SPI 20 Frequency References 21 Crystal Interface and Clock Generation 21 Crystal Oscillator 22 External Frequency Reference 22 Frequency Selection 23 Frequency Trimming 23 LPO Clock Interface 24 Pinout and Signal Descriptions 25 Pin Descriptions 25 Ball Grid Arrays 27 Electrical Characteristics 28 RF Specifications 33 Timing and AC Characteristics 36 Mechanical Information 43 Tape, Reel, and Packing Specification 44 Ordering Information 45 Document History 46

Page 3 of 38

CYW20715

Overview

The Cypress CYW20715 complies with the Bluetooth Core Specification, version and is designed for use with a standard Host Controller Interface HCI UART. The combination of the Bluetooth Baseband Core BBC , a Peripheral Transport Unit PTU , and an microprocessor with on-chip ROM provides a complete lower layer Bluetooth protocol stack, including the Link Controller LC , Link Manager LM , and HCI.

Major Features Major features of the CYW20715 include:
• Support for Bluetooth + EDR, including the following options A whitelist size of Enhanced Power Control HCI Read Encryption Key Size command
• Full support for Bluetooth + EDR additional features Secure Simple Pairing SSP Encryption Pause Resume EPR Enhance Inquiry Response EIR Link Supervision Time Out LSTO Sniff SubRating SSR Erroneous Data ED Packet Boundary Flag PBF
• Built-in Low Drop-Out LDO regulators 2 to 5.5V input voltage range to 3.3V intermediate programmable output voltage
• Integrated RF section Single-ended, RF interface Built-in TX/RX switch functionality TX Class 1 output power capability dBm RX sensitivity basic rate
• Supports maximum Bluetooth data rates over HCI UART and SPI interfaces
• Multipoint operation, with up to seven active slaves Maximum of seven simultaneous active ACL links Maximum of three simultaneous active SCO and eSCO links, with Scatternet support
• Scatternet operation, with up to four active piconets with background scan and support for ScatterMode
• High-speed HCI UART transport support H4 five-wire UART four signal wires, one ground wire H5 three-wire UART two signal wires, one ground wire Maximum UART baud rates of 4 Mbps Low-power out-of-band BT_WAKE and HOST_WAKE signaling VSC from host transport to UART Proprietary compressing scheme allows more than two simultaneous A2DP packets and up to five devices at a time
• Channel Quality-Driven Data Rate CQDDR and packet type selection
• Standard Bluetooth test modes
• Extended radio and production test mode features
• Full support for power savings modes Bluetooth standard Hold and Sniff Deep sleep modes and regulator shutdown

Page 4 of 47

CYW20715
• Supports Wide-Band Speech WBS over PCM and Packet Loss Concealment PLC for better audio quality
• 2-, 3-, and 4-wire coexistence
• Power Amplifier PA shutdown for externally controlled coexistence, such as WIMAX
• Built-in LPO clock or operation using an external LPO clock
• TCXO input and auto-detection of all standard handset clock frequencies supports low-power crystal, which can be used during

Power Saving mode with better timing accuracy
• OR gate for combining a host clock request with a Bluetooth clock request operates even when the Bluetooth core logic is powered
off
• Larger patch RAM space to support future enhancements
• Serial flash Interface with native support for devices from several manufacturers
• One-Time Programmable OTP memory

Page 5 of 47

Block Diagram Figure 2 shows the interconnect of the major CYW20715 physical blocks and associated external interfaces.

Figure Functional Block Diagram

CYW20715

JTAG Flash

Address Decoder

AHB2EBI

External Bus I/F

Trap & Patch

AHB2APB

AHB2MEM

AHB2MEM

PMU Control

WD Timer GPIO+Aux

Remap & Pause

SW Timers

ROM 384 KB

RAM 112 KB
HCI 3-Wire Transport UART H5 The CYW20715 supports H5 UART transport for serial UART communications. H5 reduces the number of signal lines required by eliminating CTS and RTS, when compared to H4. In addition, in-band sleep signaling is supported over the same interface so that the 4-wire UART and the 2-wire sleep signaling interface can be reduced to a 2-wire UART interface, saving four I/Os on the host. H5 requires the use of an external LPO. CTS must be pulled low. SPI The CYW20715 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates may be possible. The physical interface between the SPI master and the CYW20715 consists of the four SPI signals SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO and one interrupt signal SPI_INT . The CYW20715 can be configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an active-low or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode, halfduplex handshaking is implemented between the SPI master and the CYW20715. SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented in higher layer protocols.

Page 20 of 47

CYW20715

Frequency References

The CYW20715 uses two different frequency references for normal and low-power operational modes. An external crystal or frequency reference driven by a Temperature Compensated Crystal Oscillator TCXO signal is used to generate the radio frequencies and normal operation clocking. Either an external kHz or fully integrated internal Low-Power Oscillator LPO is used for lowpower mode timing.

Crystal Interface and Clock Generation The CYW20715 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing, enabling it to operate from any of a multitude of frequency sources. The source can be external, such as a TCXO, or a crystal interfaced directly to the device. The default frequency reference setting is for a 20 MHz crystal or TCXO. The signal characteristics for the crystal interface are listed in Table Crystal Interface Signal Characteristics

Parameter Acceptable frequencies Crystal load capacitance ESR Power dissipation Input signal amplitude

Signal type Input impedance

Phase noise 1 kHz 10 kHz 100 kHz 1 MHz Auto-detection frequencies when using external LPOc

Tolerance without frequency trimmingd Initial frequency tolerance trimming range

Crystal MHz in 2 ppma steps

External Frequency Reference MHz in 2 ppma steps

Units
12 typical
60 max
200 max
400 to 2000
mVp-p
2000 to 3300 requires a 10 pF DC
blocking capacitor to attenuate the
signal

Square-wave or sine-wave
dBc/Hz dBc/Hz dBc/Hz dBc/Hz
12, 13, 18, 12, 13, 18,
20, 24, 20, 24, 26,
26, and
±20
±20
±50
±50
a. The frequency step size is approximately 80 Hz resolution. b. With a 26 MHz reference clock. For a 13 MHz clock, subtract 6 dB. For a 52 MHz clock, add 6 dB. c. Auto-detection of the frequency requires the crystal or external frequency reference to have less than ±50 ppm of variation and also requires an external LPO frequency
which has less than ±250 ppm of variation at the time of detection. d. AT-Cut crystal or TXCO recommended.

Page 21 of 47

CYW20715

Crystal Oscillator The CYW20715 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator, including all external components, is shown in Figure

Figure Recommended Oscillator Configuration
0 to 18 pF*

Crystal Oscillator

XOUT
0 to 18 pF*
*Capacitor value range depends on the manufacturer of the XTAL as well as board layout.
GPIO/CLK_REQ TCXO-OR Function Out available on some packages. See Ordering Information on page

VDDO
GPIO TCXO-OR Function In available on some packages. See Ordering Information on page

VDDO DETATCH/CARD_DETECT

VDDO

UART receive data

VDDO UART transmit data

VDDO UART request to send output

VDDO

UART clear to send input I2C clock I2C data

VDDO Serial flash SPI clock

VDDO

Serial flash active-low chip select

VDDO PCM/I2S data input

Page 25 of 47

CYW20715

Table CYW20715 Signal Descriptions Cont.

Signal

PCM_OUT PCM_CLK PCM_SYNC COEX_IN COEX_OUT0 COEX_OUT1 OTP_DIS

WLBGA 42-Bump

E4 C4 A4 A2

Power Domain

VDDO

VDDO

VDDO

VDDO

VDDO

VDDO

VDDO

VDDTF VDDRF VDDPX VDDC VDDO NC VSS

PCM/I2S data output PCM/I2S clock PCM sync/I2S word select Coexistence input Coexistence output Coexistence output OTP disable pin. By default, leave this pin floating. Supplies Radio PA supply Radio supply Radio RF PLL supply Core logic supply Core logic supply Digital I/O supply voltage No connect Ground

Page 26 of 47

Ball Grid Arrays

Figure 8 shows the top view of the 42-bump, x mm array. Figure 42-Bump x mm Array Top View
1234567 A B C D E F

CYW20715

Table Ball-Out for the 42-Bump CYW20715A1KUBXG

A VSS B N/C SPIM_CLK D SDA E SCL F VDDC

OTP_DIS VSS UART_TXD UART_RXD SPIM_CS_N UART_RTS_N

VDDC GPIO_1 GPIO_0 VDDO UART_CTS_N VSS

PCM_SYNC LPO_IN PCM_CLK PCM_IN PCM_OUT GPIO_5

VBAT REG_EN RST_N GPIO_6 XOUT XIN

VREGHV VSS TM2 RES VSS
Ordering Information

Part Number CYW20715A1KUBXG

Package Type Commercial 42-bump WLBGA, mm x mm x mm. See Figure 17 on page

CYW20715

Temp. Rating to +85°C

Page 45 of 47

Document History

Document Title CYW20715 Single-Chip Bluetooth Transceiver and Baseband Processor Document Number 002-14813

Orig. of Submission

Change

Description of Change
08/23/2013
20715-DS100-R Initial release
20715-DS101-R:
10/04/2013

Updated
• UART Interface on page 19 supported baud rates.
• Table 12 on page
5452890 UTSV 09/29/2016 Updated to Cypress Template

CYW20715

Page 46 of 47

CYW20715

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Microcontrollers
cypress.com/arm

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive Clocks & Buffers Interface Internet of Things Lighting & Power Control Memory
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cypress.com/interface cypress.com/iot
cypress.com/powerpsoc cypress.com/memory

Cypress Developer Community Forums | WICED IoT Forums | Projects | Video | Blogs | Training | Components

Technical Support cypress.com/support

PSoC
cypress.com/psoc

Touch Sensing
cypress.com/touch

USB Controllers
cypress.com/usb

Wireless/RF
cypress.com/wireless

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Datasheet ID: CYW20715A1KUBXGT 508251