CYV15G0404DXB-BGC

CYV15G0404DXB-BGC Datasheet

CYV15G0404DXB

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CYV15G0404DXB-BGC	CYV15G0404DXB-BGC (pdf)

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CYV15G0404DXB Independent Clock Quad HOTLink II Transceiver with Reclocker • Synchronous LVTTL parallel interface • Quad channel transceiver for 195 to 1500 MBaud serial signaling rate Aggregate throughput of up to 12 Gbits/second • Second-generation technology • Compliant to multiple standards SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ESCON, and Gigabit Ethernet IEEE802.3z 10 bit uncoded data or 8B/10B coded data • Truly independent channels Each channel is able to • Perform reclocker function • Operate at a different signaling rate • Transport a different data format • JTAG boundary scan • Built In Self Test BIST for at-speed link testing • Link quality indicator by channel Analog signal detect Digital signal detect • Low power 3W at 3.3V typical • Single 3.3V supply • 256 ball thermally enhanced BGA • BiCMOS technology • JTAG device ID ‘0C811069’x Functional Description • Internal phase-locked loops PLLs with no external PLL components • Selectable differential PECL compatible serial inputs per channel Internal DC restoration • Redundant differential PECL compatible serial outputs per channel No external bias resistors required Signaling rate controlled edge rates Source matched for 50Ω transmission lines • MultiFrame Receive Framer provides alignment options Comma or full K28.5 detect Single or multibyte Framer for byte alignment Low latency option The CYV15G0404DXB Independent Clock Quad HOTLink II Transceiver is a point-to-point or point-to-multipoint communications building block enabling the transfer of data over a variety of high speed serial links including SMPTE 292, SMPTE 259, and DVB-ASI video applications. The signaling rate can be anywhere in the range of 195 to 1500 MBaud for each serial link. Each channel operates independently with its own reference clock allowing different rates. Each transmit channel accepts parallel characters in an input register, encodes each character for transport, and then converts it to serial data. Each receive channel accepts serial data and converts it to parallel data, decodes the data into characters, and presents these characters to an output register. The received serial data can also be reclocked and retransmitted through the serial outputs. Figure 1 illustrates typical connections between independent video coprocessors and corresponding CYV15G0404DXB chips. • Selectable input and output clocking options Figure HOTLink II System Connections Video Coprocessor Video Coprocessor Independent Channel CYV15G0404DXB Reclocker Serial Links Serial Links Serial Links Serial Links Cable Connections Independent Channel CYV15G0404DXB Reclocker • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CYV15G0404DXB The CYV15G0404DXB satisfies the SMPTE-259M and SMPTE-292M compliance according to SMPTE EG34-1999 Pathological Test Requirements. 8B/10B decoded, and checked for transmission errors. Recovered decoded characters are then written to an internal elasticity buffer, and presented to the destination host system. As a second generation HOTLink device, the CYV15G0404DXB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial link compatibility data, command, and BIST with other HOTLink devices. The transmit TX section of the CYV15G0404DXB Quad HOTLink II consists of four independent byte-wide channels. Each channel accepts either 8-bit data characters or preencoded 10-bit transmission characters. Data characters may be passed from the transmit input register to an integrated 8B/10B Encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from dual Positive ECL PECL compatible differential transmission-line drivers at a bit rate of either 10 or 20 times the input reference clock for that channel. The receive RX section of the CYV15G0404DXB Quad HOTLink II consists of four independent byte wide channels. Each channel accepts a serial bit stream from one of two PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. Each recovered bit stream is deserialized and framed into characters, The integrated 8B/10B encoder or decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface. The parallel IO interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. In addition to clocking the transmit path with a local reference clock, the receive interface may also be configured to present data relative to a recovered clock or to a local reference clock. Each transmit and receive channel contains an independent BIST pattern generator and checker. This BIST hardware allows at speed testing of the high speed serial data paths in each transmit and receive section, and across the interconnecting links. The CYV15G0404DXB is ideal for port applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers and switchers. CYV15G0404DXB Transceiver Logic Block Diagram TXDA[7:0] TXCTA[1:0] REFCLKA± RXDA[7:0] RXSTA[2:0] TXDB[7:0] TXCTB[1:0] REFCLKB± RXDB[7:0] RXSTB[2:0] TXDC[7:0] TXCTC[1:0] REFCLKC± RXDC[7:0] RXSTC[2:0] TXDD[7:0] TXCTD[1:0] REFCLKD± RXDD[7:0] RXSTD[2:0] The following information describes how the tables are used for both generating valid transmission characters encoding and checking the validity of received transmission characters decoding . It also specifies the ordering rules followed when transmitting the bits within a character and the characters within any higher level constructs specified by a standard. Transmission Order Within the definition of the 8B/10B transmission code, the bit positions of the transmission characters are labeled a, b, c, d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order. Note that bit i is transmitted between bit e and bit f, rather than in alphabetical order. Valid and Invalid Transmission Characters The following tables define the valid data characters and valid special characters K characters , respectively. The tables are used for both generating valid transmission characters and checking the validity of received transmission characters. In the tables, each valid-data-byte or special-character-code entry has two columns that represent two transmission characters. The two columns correspond to the current value of the running disparity. Running disparity is a binary parameter with either a negative or positive + value. After powering on, the transmitter may assume either a positive or negative value for its initial running disparity. Upon trans- Page 36 of 44 [+] Feedback CYV15G0404DXB mission of any transmission character, the transmitter selects the proper version of the transmission character based on the current running disparity value, and the transmitter calculates a new value for its running disparity based on the contents of the transmitted character. Special character codes C1.7 and C2.7 can be used to force the transmission of a specific special character with a specific running disparity as required for some special sequences in X3.230. transmitted, a new value of the running disparity is calculated. This new value is used as the transmitter’s current running disparity for the next valid data byte or Special Character byte encoded and transmitted. Table 12 shows naming notations and examples of valid transmission characters. Use of the Tables for Checking the Validity of Received Transmission Characters After powering on, the receiver may assume either a positive or negative value for its initial running disparity. Upon reception of any transmission character, the receiver decides whether the transmission character is valid or invalid according to the following rules and tables and calculates a new value for its running disparity based on the contents of the received character. The following rules for running disparity are used to calculate the new running disparity value for transmission characters that have been transmitted and received. Running disparity for a transmission character is calculated from subblocks, where the first six bits abcdei form one subblock and the second four bits fghj form the other subblock. Running disparity at the beginning of the 6-bit subblock is the running disparity at the end of the previous transmission character. running disparity at the beginning of the 4-bit subblock is the running disparity at the end of the 6-bit subblock. Running disparity at the end of the transmission character is the running disparity at the end of the 4-bit subblock. The column corresponding to the current value of the receiver’s running disparity is searched for the received transmission character. If the received transmission character is found in the proper column, then the transmission character is valid and the associated data byte or special character code is determined decoded . If the received transmission character is not found in that column, then the transmission character is invalid. This is a code violation. Independent of the transmission character’s validity, the received transmission character is used to calculate a new value of running disparity. The new value is used as the receiver’s current running disparity for the next received transmission character. Table Valid Transmission Characters Byte Name Data DIN or QOUT 765 43210 Hex Value D0.0 Running disparity for the subblocks is calculated as follows: Running disparity at the end of any subblock is positive if the subblock contains more ones than zeros. It is also positive at the end of the 6-bit subblock if the 6-bit subblock is 000111, and it is positive at the end of the 4-bit subblock if the 4-bit subblock is Running disparity at the end of any subblock is negative if the subblock contains more zeros than ones. It is also negative at the end of the 6-bit subblock if the 6-bit subblock is 111000, and it is negative at the end of the 4-bit subblock if the 4-bit subblock is Otherwise, running disparity at the end of the subblock is the same as at the beginning of the subblock. D1.0 000 00001 D2.0 000 00010 D5.2 010 00101 D30.7 111 11110 D31.7 Use of the Tables for Generating Transmission Characters The appropriate entry in Table 14 for the valid data byte or Table 15 for Special Character byte identify which transmission character is generated. The current value of the transmitter’s running disparity is used to select the transmission character from its corresponding column. For each transmission character Detection of a code violation does not necessarily show that the transmission character in which the code violation was detected is in error. Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the transmission character in which the error occurred. Table 12 shows an example of this behavior. Table Code Violations Resulting from Prior Errors Character Character Ordering Information Speed Standard Ordering Code CYV15G0404DXB-BGC CYV15G0404DXB-BGI Package Name Package Type BL256 256-Ball Thermally Enhanced Ball Grid Array 256-Ball Thermally Enhanced Ball Grid Array Operating Range Commercial Industrial Package Diagram 256-Lead L2 Ball Grid Array 27 x 27 x mm BL256 51-85123-*E Page 43 of 44 [+] Feedback CYV15G0404DXB Document History Page Document Title CYV15G0404DXB Independent Clock Quad HOTLink II Transceiver with Reclocker Document Number 38-02097 ECN NO. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE 231494 See ECN New Data Sheet 384307 See ECN tRXDv+, tTREFDS, tREFxDV+, tRST, tRISE, tFALL, tDJ 1845306 See ECN UKK/VED Added clarification for the necessity of JTAG controller reset and the methods to implement it. Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 44 of 44 IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines. HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CYV15G0404DXB

Independent Clock Quad HOTLink II Transceiver with Reclocker
• Synchronous LVTTL parallel interface
• Quad channel transceiver for 195 to 1500 MBaud serial signaling rate Aggregate throughput of up to 12 Gbits/second
• Second-generation technology
• Compliant to multiple standards SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ESCON, and Gigabit Ethernet IEEE802.3z 10 bit uncoded data or 8B/10B coded data
• Truly independent channels Each channel is able to
• Perform reclocker function
• Operate at a different signaling rate
• Transport a different data format
• JTAG boundary scan
• Built In Self Test BIST for at-speed link testing
• Link quality indicator by channel

Analog signal detect Digital signal detect
• Low power 3W at 3.3V typical
• Single 3.3V supply
• 256 ball thermally enhanced BGA
• BiCMOS technology
• JTAG device ID ‘0C811069’x

Functional Description
• Internal phase-locked loops PLLs with no external PLL components
• Selectable differential PECL compatible serial inputs per channel Internal DC restoration
• Redundant differential PECL compatible serial outputs per channel No external bias resistors required Signaling rate controlled edge rates Source matched for 50Ω transmission lines
• MultiFrame Receive Framer provides alignment options Comma or full K28.5 detect Single or multibyte Framer for byte alignment Low latency option

The CYV15G0404DXB Independent Clock Quad HOTLink II Transceiver is a point-to-point or point-to-multipoint communications building block enabling the transfer of data over a variety of high speed serial links including SMPTE 292, SMPTE 259, and DVB-ASI video applications. The signaling rate can be anywhere in the range of 195 to 1500 MBaud for each serial link. Each channel operates independently with its own reference clock allowing different rates. Each transmit channel accepts parallel characters in an input register, encodes each character for transport, and then converts it to serial data. Each receive channel accepts serial data and converts it to parallel data, decodes the data into characters, and presents these characters to an output register. The received serial data can also be reclocked and retransmitted through the serial outputs. Figure 1 illustrates typical connections between independent video coprocessors and corresponding CYV15G0404DXB chips.
• Selectable input and output clocking options

Figure HOTLink II System Connections

Video Coprocessor

Video Coprocessor

Independent Channel

CYV15G0404DXB Reclocker

Serial Links

Serial Links

Serial Links

Serial Links Cable

Connections

Independent Channel

CYV15G0404DXB Reclocker
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CYV15G0404DXB

The CYV15G0404DXB satisfies the SMPTE-259M and SMPTE-292M compliance according to SMPTE EG34-1999 Pathological Test Requirements.
8B/10B decoded, and checked for transmission errors. Recovered decoded characters are then written to an internal elasticity buffer, and presented to the destination host system.

As a second generation HOTLink device, the CYV15G0404DXB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial link compatibility data, command, and BIST with other HOTLink devices. The transmit TX section of the CYV15G0404DXB Quad HOTLink II consists of four independent byte-wide channels. Each channel accepts either 8-bit data characters or preencoded 10-bit transmission characters. Data characters may be passed from the transmit input register to an integrated 8B/10B Encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from dual Positive ECL PECL compatible differential transmission-line drivers at a bit rate of either 10 or 20 times the input reference clock for that channel.

The receive RX section of the CYV15G0404DXB Quad HOTLink II consists of four independent byte wide channels. Each channel accepts a serial bit stream from one of two PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. Each recovered bit stream is deserialized and framed into characters,

The integrated 8B/10B encoder or decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface.

The parallel IO interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. In addition to clocking the transmit path with a local reference clock, the receive interface may also be configured to present data relative to a recovered clock or to a local reference clock.

Each transmit and receive channel contains an independent BIST pattern generator and checker. This BIST hardware allows at speed testing of the high speed serial data paths in each transmit and receive section, and across the interconnecting links.

The CYV15G0404DXB is ideal for port applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers and switchers.

CYV15G0404DXB Transceiver Logic Block Diagram

TXDA[7:0] TXCTA[1:0] REFCLKA± RXDA[7:0] RXSTA[2:0] TXDB[7:0] TXCTB[1:0] REFCLKB± RXDB[7:0] RXSTB[2:0] TXDC[7:0] TXCTC[1:0] REFCLKC± RXDC[7:0] RXSTC[2:0] TXDD[7:0] TXCTD[1:0] REFCLKD± RXDD[7:0] RXSTD[2:0]
The following information describes how the tables are used for both generating valid transmission characters encoding and checking the validity of received transmission characters decoding . It also specifies the ordering rules followed when transmitting the bits within a character and the characters within any higher level constructs specified by a standard.

Transmission Order

Within the definition of the 8B/10B transmission code, the bit positions of the transmission characters are labeled a, b, c, d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order.

Note that bit i is transmitted between bit e and bit f, rather than in alphabetical order.

Valid and Invalid Transmission Characters

The following tables define the valid data characters and valid special characters K characters , respectively. The tables are used for both generating valid transmission characters and checking the validity of received transmission characters. In the tables, each valid-data-byte or special-character-code entry has two columns that represent two transmission characters. The two columns correspond to the current value of the running disparity. Running disparity is a binary parameter with either a negative or positive + value.

After powering on, the transmitter may assume either a positive or negative value for its initial running disparity. Upon trans-

Page 36 of 44
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CYV15G0404DXB
mission of any transmission character, the transmitter selects the proper version of the transmission character based on the current running disparity value, and the transmitter calculates a new value for its running disparity based on the contents of the transmitted character. Special character codes C1.7 and C2.7 can be used to force the transmission of a specific special character with a specific running disparity as required for some special sequences in X3.230.
transmitted, a new value of the running disparity is calculated. This new value is used as the transmitter’s current running disparity for the next valid data byte or Special Character byte encoded and transmitted. Table 12 shows naming notations and examples of valid transmission characters.

Use of the Tables for Checking the Validity of Received Transmission Characters

After powering on, the receiver may assume either a positive or negative value for its initial running disparity. Upon reception of any transmission character, the receiver decides whether the transmission character is valid or invalid according to the following rules and tables and calculates a new value for its running disparity based on the contents of the received character.

The following rules for running disparity are used to calculate the new running disparity value for transmission characters that have been transmitted and received.

Running disparity for a transmission character is calculated from subblocks, where the first six bits abcdei form one subblock and the second four bits fghj form the other subblock. Running disparity at the beginning of the 6-bit subblock is the running disparity at the end of the previous transmission character. running disparity at the beginning of the 4-bit subblock is the running disparity at the end of the 6-bit subblock. Running disparity at the end of the transmission character is the running disparity at the end of the 4-bit subblock.

The column corresponding to the current value of the receiver’s running disparity is searched for the received transmission character. If the received transmission character is found in the proper column, then the transmission character is valid and the associated data byte or special character code is determined decoded . If the received transmission character is not found in that column, then the transmission character is invalid. This is a code violation. Independent of the transmission character’s validity, the received transmission character is used to calculate a new value of running disparity. The new value is used as the receiver’s current running disparity for the next received transmission character.

Table Valid Transmission Characters

Byte Name

Data DIN or QOUT 765 43210

Hex Value

D0.0

Running disparity for the subblocks is calculated as follows:

Running disparity at the end of any subblock is positive if the subblock contains more ones than zeros. It is also positive at the end of the 6-bit subblock if the 6-bit subblock is 000111, and it is positive at the end of the 4-bit subblock if the 4-bit subblock is

Running disparity at the end of any subblock is negative if the subblock contains more zeros than ones. It is also negative at the end of the 6-bit subblock if the 6-bit subblock is 111000, and it is negative at the end of the 4-bit subblock if the 4-bit subblock is

Otherwise, running disparity at the end of the subblock is the same as at the beginning of the subblock.

D1.0
000 00001

D2.0
000 00010

D5.2
010 00101

D30.7
111 11110

D31.7

Use of the Tables for Generating Transmission Characters

The appropriate entry in Table 14 for the valid data byte or Table 15 for Special Character byte identify which transmission character is generated. The current value of the transmitter’s running disparity is used to select the transmission character from its corresponding column. For each transmission character

Detection of a code violation does not necessarily show that the transmission character in which the code violation was detected is in error. Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the transmission character in which the error occurred. Table 12 shows an example of this behavior.

Table Code Violations Resulting from Prior Errors

Character

Character
Ordering Information

Speed

Standard
Ordering Code

CYV15G0404DXB-BGC CYV15G0404DXB-BGI

Package Name

Package Type

BL256
256-Ball Thermally Enhanced Ball Grid Array 256-Ball Thermally Enhanced Ball Grid Array

Operating Range

Commercial

Industrial

Package Diagram
256-Lead L2 Ball Grid Array 27 x 27 x mm BL256
51-85123-*E

Page 43 of 44 [+] Feedback

CYV15G0404DXB

Document History Page

Document Title CYV15G0404DXB Independent Clock Quad HOTLink II Transceiver with Reclocker Document Number 38-02097

ECN NO.

ISSUE DATE

ORIG. OF CHANGE

DESCRIPTION OF CHANGE
231494 See ECN

New Data Sheet
384307 See ECN
tRXDv+, tTREFDS, tREFxDV+, tRST, tRISE, tFALL, tDJ
1845306 See ECN UKK/VED Added clarification for the necessity of JTAG controller reset and the
methods to implement it.

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 44 of 44

IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines. HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
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Datasheet ID: CYV15G0404DXB-BGC 508244