CYV15G0204TRB-BGC

CYV15G0204TRB-BGC Datasheet

CYV15G0204TRB

Part	Datasheet
CYV15G0204TRB-BGC	CYV15G0204TRB-BGC (pdf)

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CYV15G0204TRB Independent Clock HOTLink II Dual Serializer and Dual Reclocking Deserializer • Second-generation technology • Compliant to SMPTE 292M and SMPTE 259M video standards • Dual-channel video serializer plus dual channel video reclocking deserializer 195- to 1500-Mbps serial data signaling rate Simultaneous operation at different signaling rates • Supports reception of either or Gbps data rate with the same training clock • Supports half-rate and full-rate clocking • Internal phase-locked loops PLLs with no external PLL components • Selectable differential PECL-compatible serial inputs Internal DC-restoration • Redundant differential PECL-compatible serial outputs No external bias resistors required Signaling-rate controlled edge-rates Internal source termination • Synchronous LVTTL parallel interface • JTAG boundary scan • Built-In Self-Test BIST for at-speed link testing • Link Quality Indicator Analog signal detect Digital signal detect • Low-power 2.5W 3.3V typical • Single 3.3V supply • Thermally enhanced BGA • Pb-Free package option available • BiCMOS technology Functional Description The CYV15G0204TRB Independent Clock HOTLink II Dual Serializer and Dual Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. All transmit and receive channels are independent and can operate simultaneously at different rates. Each transmit channel accepts 10-bit parallel characters in an Input Register and converts them to serial data. Each receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1 illustrates typical connections between independent video coprocessors and corresponding CYV15G0204TRB chips. The CYV15G0204TRB satisfies the SMPTE 259M and SMPTE 292M compliance as per SMPTE EG34-1999 Pathological Test Requirements. As a second-generation HOTLink device, the CYV15G0204TRB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility data and BIST with other HOTLink devices. Each transmit TX channel of the CYV15G0204TRB HOTLink II device accepts scrambled 10-bit transmission characters. These characters are serialized and output from dual Positive ECL PECL compatible differential transmission-line drivers at a bit-rate of either 10- or 20-times the input reference clock for that channel. Independent Channel CYV15G0204TRB Device Reclocked Outputs Independent Channel CYV15G0204TRB Device Video Coprocessor Video Coprocessor Serial Links Reclocked Outputs Figure HOTLink II System Connections Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 [+] Feedback CYV15G0204TRB Each receive RX channel of the CYV15G0204TRB HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs. Also, the recovered serial data is deserialized and presented to the destination host system. Each transmit and receive channel contains an independent BIST pattern generator and checker, respectively. This BIST CYV15G0204TRB Logic Block Diagram hardware allows at-speed testing of the high-speed serial data paths in each transmit and receive section, and across the interconnecting links. The CYV15G0204TRB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multiformat routers, switchers, format converters, SDI monitors, cameras, and camera control units. TXDA[9:0] REFCLKA± TXDB[9:0] REFCLKB± RXDC[9:0] TRGCLKC± RXDD[9:0] TRGCLKD± Phase Align Buffer Serializer Ordering Information Speed Standard Ordering Code CYV15G0204TRB-BGC CYV15G0204TRB-BGXC Package Name BL256 BL256 Package Type 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Operating Range Commercial Commercial Package Diagram 256-Lead L2 Ball Grid Array 27 x 27 x mm BL256 51-85123-*E HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Page 29 of 30 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CYV15G0204TRB Document History Page Document Title CYV15G0204TRB Independent Clock HOTLink II Dual Serializer and Dual Reclocking Deserializer Document Number 38-02101 ECN NO. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE 244348 See ECN New Data Sheet 338721 See ECN Added Pb-Free package option availability 384307 See ECN Page 30 of 30 [+] Feedback

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CYV15G0204TRB

Independent Clock HOTLink II Dual Serializer and Dual Reclocking Deserializer
• Second-generation technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Dual-channel video serializer plus dual channel video
reclocking deserializer
195- to 1500-Mbps serial data signaling rate

Simultaneous operation at different signaling rates
• Supports reception of either or Gbps
data rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops PLLs with no external

PLL components
• Selectable differential PECL-compatible serial inputs

Internal DC-restoration
• Redundant differential PECL-compatible serial outputs

No external bias resistors required

Signaling-rate controlled edge-rates

Internal source termination
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test BIST for at-speed link testing
• Link Quality Indicator

Analog signal detect

Digital signal detect
• Low-power 2.5W 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
• BiCMOS technology

Functional Description

The CYV15G0204TRB Independent Clock HOTLink II Dual Serializer and Dual Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. All transmit and receive channels are independent and can operate simultaneously at different rates. Each transmit channel accepts 10-bit parallel characters in an Input Register and converts them to serial data. Each receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1 illustrates typical connections between independent video coprocessors and corresponding CYV15G0204TRB chips.

The CYV15G0204TRB satisfies the SMPTE 259M and SMPTE 292M compliance as per SMPTE EG34-1999 Pathological Test Requirements.

As a second-generation HOTLink device, the CYV15G0204TRB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility data and BIST with other HOTLink devices. Each transmit TX channel of the CYV15G0204TRB HOTLink II device accepts scrambled 10-bit transmission characters. These characters are serialized and output from dual Positive ECL PECL compatible differential transmission-line drivers at a bit-rate of either 10- or 20-times the input reference clock for that channel.

Independent Channel

CYV15G0204TRB Device

Reclocked Outputs

Independent Channel

CYV15G0204TRB Device

Video Coprocessor

Video Coprocessor

Serial Links

Reclocked Outputs

Figure HOTLink II System Connections

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600
[+] Feedback

CYV15G0204TRB

Each receive RX channel of the CYV15G0204TRB HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs. Also, the recovered serial data is deserialized and presented to the destination host system.

Each transmit and receive channel contains an independent BIST pattern generator and checker, respectively. This BIST

CYV15G0204TRB Logic Block Diagram
hardware allows at-speed testing of the high-speed serial data paths in each transmit and receive section, and across the interconnecting links.

The CYV15G0204TRB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multiformat routers, switchers, format converters, SDI monitors, cameras, and camera control units.

TXDA[9:0] REFCLKA± TXDB[9:0] REFCLKB± RXDC[9:0] TRGCLKC± RXDD[9:0] TRGCLKD±

Phase Align Buffer Serializer
Ordering Information

Speed Standard
Ordering Code CYV15G0204TRB-BGC CYV15G0204TRB-BGXC

Package Name

BL256

BL256

Package Type 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array

Operating Range

Commercial

Commercial

Package Diagram
256-Lead L2 Ball Grid Array 27 x 27 x mm BL256
51-85123-*E

HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.

Page 29 of 30

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CYV15G0204TRB

Document History Page

Document Title CYV15G0204TRB Independent Clock HOTLink II Dual Serializer and Dual Reclocking Deserializer Document Number 38-02101

ECN NO.

ISSUE DATE

ORIG. OF CHANGE

DESCRIPTION OF CHANGE
244348 See ECN

New Data Sheet
338721 See ECN

Added Pb-Free package option availability
384307 See ECN

Page 30 of 30 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYV15G0204TRB-BGC Datasheet file may be downloaded here without warranties.

Datasheet ID: CYV15G0204TRB-BGC 508242