CYV15G0204RB-BGC

CYV15G0204RB-BGC Datasheet


CYV15G0204RB

Part Datasheet
CYV15G0204RB-BGC CYV15G0204RB-BGC CYV15G0204RB-BGC (pdf)
Related Parts Information
CYV15G0204RB-BGXC CYV15G0204RB-BGXC CYV15G0204RB-BGXC
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CYV15G0204RB

Independent Clock Dual HOTLink II Reclocking Deserializer
• Second-generation technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Dual-channel video reclocking deserializer
195- to 1500-Mbps serial data signaling rate Simultaneous operation at different signaling rates
• Supports reception of either or Gbps data rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops PLLs with no external PLL components
• Selectable differential PECL-compatible serial inputs Internal DC-restoration
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test BIST for at-speed link testing
• Link Quality Indicator Analog signal detect Digital signal detect
• Low-power 2W 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
• BiCMOS technology

Functional Description

The CYV15G0204RB Independent Clock Dual HOTLink II Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292 and SMPTE 259 video applications. It supports signaling rates

Reclocked Output
in the range of 195 to 1500 Mbps per serial link. The two channels are independent and can simultaneously operate at different rates. Each receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1 illustrates typical connections between independent video co-processors and corresponding CYV15G0204RB Reclocking Deserializer and CYV15G0203TB Serializer chips.

The CYV15G0204RB satisfies the SMPTE-259M and SMPTE-292M compliance as per SMPTE EG34-1999 Pathological Test Requirements.

As a second-generation HOTLink device, the CYV15G0204RB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility data and BIST with other HOTLink devices.

Each channel of the CYV15G0204RB Dual HOTLink II device accepts a serial bit-stream from one of two selectable PECLcompatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs. Also, the recovered serial data is deserialized and presented to the destination host system.

Each channel contains an independent BIST pattern checker. This BIST hardware allows at-speed testing of the high-speed serial data paths in each receive section of this device, each transmit section of a connected HOTLink II device, and across the interconnecting links.

The CYV15G0204RB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multiformat routers, switchers, format converters, SDI monitors, and camera control units.

Video Coprocessor

Video Coprocessor

Independent Channel

CYV15G0203TB Serializer

Serial Links

Independent Channel

CYV15G0204RB Reclocking Deserializer

Reclocked Output

Figure HOTLink II System Connections

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600
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CYV15G0204RB Deserializing Reclocker Logic Block Diagram

CYV15G0204RB

RXDA[9:0] TRGCLKA± RXDB[9:0] TRGCLKB±

Deserializer

Deserializer

Reclocker

Reclocker RX

ROUTA1± ROUTA2±

INA1± INA2± ROUTB1± ROUTB2± INB1± INB2±

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CYV15G0204RB

Reclocking Deserializer Path Block Diagram

TRGRATEA

TRGCLKA

SDASEL[2..1]A[1:0] LDTDEN

INSELA
Ordering Information

Speed Standard
Ordering Code CYV15G0204RB-BGC CYV15G0204RB-BGXC

Package Name

BL256

BL256

Package Type 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array

Operating Range

Commercial

Commercial

Package Diagram
256-Lead L2 Ball Grid Array 27 x 27 x mm BL256
51-85123-*E

HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.

Page 23 of 24

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CYV15G0204RB

Document History Page

Document Title CYV15G0204RB Independent Clock Dual HOTLink II Deserializing Reclocker Document Number 38-02103

ECN NO.

ISSUE DATE

ORIG. OF CHANGE

DESCRIPTION OF CHANGE
246850 See ECN

New Data Sheet
338721 See ECN

Added Pb-Free package option availability
384307 See ECN

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Datasheet ID: CYV15G0204RB-BGC 508241