5962F1120101QXA

5962F1120101QXA Datasheet

250 5962F1120101QXA

Part	Datasheet
5962F1120101QXA	5962F1120101QXA (pdf)

Related Parts	Information
5962F1120201QXA	5962F1120201QXA

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CYRS1542AV18 CYRS1544AV18 72-Mbit II+ SRAM Two-Word Burst Architecture with RadStop Technology 72-Mbit II+ SRAM Two-Word Burst Architecture with RadStop Technology Radiation Performance Radiation Data • Total Dose =300 Krad • Soft error rate both Heavy Ion and proton Heavy ions 1 x 10-10 upsets/bit-day with an external SECDED EDAC Controller • Neutrons = x 1014 N/cm2 • Dose rate = x 109 rad Si /sec • Dose rate survivability rad Si /sec = x rad Si /sec • Latch up immunity = 120 MeV.cm2/mg 125 °C Prototyping Options • Non qualified CYPT1542AV18 and CTPT1544AV18 devices with same functional and timing characteristics in a 165-ball Ceramic Column Grid Array CCGA package • Separate independent read and write data ports Supports concurrent transactions • 250-MHz clock for high bandwidth • Two-word burst on all accesses • Double data rate DDR interfaces on both read and write ports at 250 MHz data transferred at 500 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Echo clocks CQ and CQ simplify data capture in high speed systems • Single multiplexed address input bus latches address inputs for both read and write ports • Separate port selects for depth expansion • Synchronous internally self-timed writes • II operates with cycle read latency when delay lock loop DLL is enabled • Available in x 18 and x 36 configurations • Full data coherency, providing most current data • Core VDD = V I/O VDDQ = V to VDD • Available in 165-ball CCGA 21 x 25 x mm • HSTL inputs and variable drive HSTL output buffers • JTAG compatible test access port • DLL for accurate data placement Configurations CYRS1542AV18 4 M x 18 CYRS1544AV18 2 M x 36 Functional Description The CYRS1542AV18 and CYRS1544AV18 are synchronous pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with RadStop technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques. The QDR II+ architecture consists of two separate ports to access the memory the read port and the write port. The read port has dedicated data output bus to support read operations and the write port has dedicated data input bus to support write operations. QDR II+ architecture completely eliminates the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read are latched on the rising edges of the input K clock whereas addresses for write are latched on the falling edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of each another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit words for CYRS1542AV18, or two 36-bit words for CYRS1544AV18 that burst sequentially into or out of the device. Since data can be transferred on every rising edge of both input clocks K and K# , memory bandwidth is maximized while simplifying system design by eliminating bus “turnarounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks as well. Reads and writes are conducted with on-chip synchronous self-timed circuitry. For a complete list of related resources, click here. Selection Guide Description Maximum operating frequency Maximum operating current concurrent R/W 250 MHz Unit 250 MHz x 18 1700 mA x 36 1700 • San Jose, CA 95134-1709 • 408-943-2600 CYRS1542AV18 CYRS1544AV18 Logic Block Diagram CYRS1542AV18 D[17:0] A 20:0 21 Address Register Power Up Sequence 21 DLL Constraints 21 Maximum Ratings 22 Operating Range 22 Electrical Characteristics 22 DC Electrical Characteristics 22 AC Electrical Characteristics 23 Radiation Performance 23 Capacitance 23 Thermal Resistance 23 AC Test Loads and Waveforms 24 Switching Characteristics 25 Switching Waveforms 26 Ordering Information 27 Ordering Code Definitions 27 Package Diagram 28 Acronyms 29 Document Conventions 29 Units of Measure 29 Glossary 30 Document History Page 31 Sales, Solutions, and Legal Information 34 Worldwide Sales and Design Support 34 Products 34 Solutions 34 Cypress Developer Community 34 Technical Support 34 Page 3 of 34 CYRS1542AV18 CYRS1544AV18 Manufacturing Flow Step Screen Method Requirement 1 Wafer lot acceptance test TM 5007 2 Internal visual 2010, Condition A 100% 3 Serialization 100% 4 Temperature cycling 1010, Condition C, 50 cycles minimum 100% 5 Constant acceleration 2001, YI orientation only 100% Condition TBD package in design 7 Particle impact noise detection PIND 2020 Condition A 100% 8 Radiographic X-ray 2012, one view Y-1 orientation only 9 Pre burn in electrical parameters In accordance with applicable Cypress specification 100% 10 Dynamic burn in 1015, Condition D 100% 240 hours at 125 °C or 120 hours at 150 °C minimum 11 Interim post dynamic burn in electricals In accordance with applicable Cypress device specifications 100% 12 Static burn in 1015, Condition C, 72 hours at 150 °C or 144 hours at 125 °C minimum 100% 13 Interim post static burn in electricals Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for x 18 option , contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 250 CYRS1542AV18-250GCMB 250 CYRS1544AV18-250GCMB 250 CYPT1542AV18-250GCMB 250 CYPT1544AV18-250GCMB 250 5962F1120101QXA 250 5962F1120101VXA 250 5962F1120201QXA 250 5962F1120201VXA 72M QDR II+, x 18, Burst of 2 72M QDR II+, x 36, Burst of 2 72M QDR II+, x 18, Burst of 2, Prototype 72M QDR II+, x 36, Burst of 2, Prototype 72M QDR II+, x 18, Burst of 2, DLAM Part 72M QDR II+, x 18, Burst of 2, DLAM Part 72M QDR II+, x 36, Burst of 2, DLAM Part 72M QDR II+, x 36, Burst of 2, DLAM Part Package Diagram Package Type Operating Range 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military 001-58969 165-ball CCGA 21 x 25 x mm Military Ordering Code Definitions CY XX 154X A V18 - 250 GC M B Page 27 of 34 CYRS1542AV18 CYRS1544AV18 Package Diagram Figure 165-ball Ceramic Column Grid Array CCGA 21 x 25 mm Package Outline, 001-58969 001-58969 *D Page 28 of 34 Acronyms Acronym byte write select CCGA ceramic column grid array double error detection delay lock loop double data rate DSCC defense supply center columbus EDAC error detection and correction HSTL high speed transceiver logic input/output JTAG Joint Test Action Group least significant bit LSBU logical single-bit upsets LMBU logical multi-bit upsets most significant bit percent defect allowable PIND particle impact noise detection percent defective allowable quad data rate read port select single error correction single event latch up SRAM static random access memory test access port values for tCO parameter under Output Time parameter . Updated Ordering Information Added 200-MHz part numbers CYRS1542AV18-250GCMB, CYRS1544AV18-250GCMB for Burst 2 mode . Updated Package Diagram. Added Units of Measure. 3281455 06/13/2011 HRP Changed status from Advanced to Final. Updated Configurations corrected typo . Updated Selection Guide. Updated DC Electrical Characteristics maximum current limit values for the parameters IDD and ISB1 based on device characterization . Updated Radiation Performance Limits of Radiation Data based on RHA qualification. Updated Thermal Resistance. Updated Switching Characteristics Minimum and Maximum timing values for the parameters tco, tDOH, tCCQO, tCQOH based on device characterization . Updated Ordering Information Removed x 18 option from ordering table . Updated Package Diagram. Changed DLL lockup cycles from 2048 to 10240 throughout document. Updated in new template. 3471321 12/21/2011 HRP Updated Identification Register Definitions Replaced the value of Cypress device ID 28:12 from 11010011010010100 to 11010010100010100 for CYRS1542AV18 and replaced the value of Cypress device ID 28:12 from 11010011010100100 to 11010010100100100 for CYRS1544AV18 . 3524961 02/14/2012 HRP Updated Prototyping Options under Radiation Performance. Added two devices . Updated Application Example. Updated Truth Table. Updated Maximum Ratings. Updated Radiation Performance. Updated Capacitance. Updated Thermal Resistance. Updated Switching Characteristics. Updated Ordering Information Removed 200 MHz speed part CYRS1544AV18-200GCMB . 3537277 02/29/2012 HRP Updated Radiation Data under Radiation Performance. Updated Ordering Information Removed the part number CYRS1544AV18-250GCMB and added the part numbers CYRS1543AV18-250GCMB, CYRS1545AV18-250GCMB, CYPT1543AV18-250GCMB, CYPT1545AV18-250GCMB, 5962F1120201VXA and 5962F1120202VXA . 3580538 04/12/2012 HRP Updated Ordering Information Updated part numbers . 3617759 05/15/2012 HRP Updated Radiation Performance Updated Prototyping Options . Updated Ordering Information Added part 5962F1120101VXA . Updated Glossary. Page 31 of 34 CYRS1542AV18 CYRS1544AV18 Document History Page continued Document Title CYRS1542AV18/CYRS1544AV18, 72-Mbit II+ SRAM Two-Word Burst Architecture with RadStop Technology Document Number 001-60006 ECN No. Submission Date Orig. of Change Description of Change 3640834 06/08/2012 HRP Updated Radiation Performance Updated Prototyping Options . Renamed the section Class V Flow as Manufacturing Flow. Updated Glossary. 3857750 01/04/2013 HRP Updated Ordering Information Updated part numbers . 3900846 02/11/2013 HRP Updated Neutron Soft Error Immunity Changed value of Test Conditions of SEL parameter from 85 °C to 125 °C . Updated Pin Definitions Changed Pin Name from A to A[x:0] . Updated Functional Overview Updated Qualification and Screening Replaced Class V with Class Q . 3934155 03/15/2013 MISA Updated Selection Guide: Changed Maximum operating current concurrent R/W corresponding to “x 18” for 250 MHz frequency from 1650 mA to 1700 mA. Changed Maximum operating current concurrent R/W corresponding to “x 36” for 250 MHz frequency from 1650 mA to 1700 mA. Updated Electrical Characteristics Updated DC Electrical Characteristics Changed maximum value of IDD parameter corresponding to “x 18” for 250 MHz frequency from 1650 mA to 1700 mA. Changed maximum value of IDD parameter corresponding to “x 36” for 250 MHz frequency from 1650 mA to 1700 mA. Changed maximum value of ISB1 parameter corresponding to “x 18” for 250 MHz frequency from 600 mA to 660 mA. Changed maximum value of ISB1 parameter corresponding to “x 36” for 250 MHz frequency from 550 mA to 660 mA. Removed 200 MHz frequency related information. Updated Switching Characteristics Changed maximum value of tCO and tCHQV parameters from ns to ns. Changed minimum value of tDOH and tCHQX parameters from ns to ns. Changed maximum value of tCCQO and tCHCQV parameters from ns to ns. Changed minimum value of tCQOH and tCHCQX parameters from ns to ns. Removed 200 MHz frequency related information. 4286754 02/21/2014 MISA Updated Functional Overview: Updated Qualification and Screening: Replaced “Class Q” with “Class Q, Class V”. Updated Ordering Information Updated part numbers . Updated to new template. Page 32 of 34 CYRS1542AV18 CYRS1544AV18 Document History Page continued Document Title CYRS1542AV18/CYRS1544AV18, 72-Mbit II+ SRAM Two-Word Burst Architecture with RadStop Technology Document Number 001-60006 ECN No. Submission Date Orig. of Change Description of Change 4618500 01/09/2015 PRIT Updated Radiation Performance: Updated Radiation Data Updated 2nd bulleted point. Updated Prototyping Options Updated 1st bulleted point. Updated Functional Description: Updated description. Added “For a complete list of related resources, click here.” at the end. Updated Pin Definitions: Updated description of CQ and CQ pins. Updated Functional Overview: Updated description. Updated Read Operations: Updated description. Updated Write Operations: Updated description. Updated Application Example: Updated Figure Page 33 of 34 CYRS1542AV18 CYRS1544AV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Solutions Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP Interface Lighting & Power Control Memory PSoC

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CYRS1542AV18 CYRS1544AV18
72-Mbit II+ SRAM Two-Word Burst Architecture with RadStop Technology
72-Mbit II+ SRAM Two-Word Burst Architecture with RadStop Technology

Radiation Performance

Radiation Data
• Total Dose =300 Krad
• Soft error rate both Heavy Ion and proton

Heavy ions 1 x 10-10 upsets/bit-day with an external SECDED EDAC Controller
• Neutrons = x 1014 N/cm2
• Dose rate = x 109 rad Si /sec
• Dose rate survivability rad Si /sec = x rad Si /sec
• Latch up immunity = 120 MeV.cm2/mg 125 °C

Prototyping Options
• Non qualified CYPT1542AV18 and CTPT1544AV18 devices with same functional and timing characteristics in a 165-ball Ceramic Column Grid Array CCGA package
• Separate independent read and write data ports Supports concurrent transactions
• 250-MHz clock for high bandwidth
• Two-word burst on all accesses
• Double data rate DDR interfaces on both read and write ports at 250 MHz data transferred at 500 MHz
• Two input clocks K and K for precise DDR timing SRAM uses rising edges only
• Echo clocks CQ and CQ simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• II operates with cycle read latency when delay lock
loop DLL is enabled
• Available in x 18 and x 36 configurations
• Full data coherency, providing most current data
• Core VDD = V I/O VDDQ = V to VDD
• Available in 165-ball CCGA 21 x 25 x mm
• HSTL inputs and variable drive HSTL output buffers
• JTAG compatible test access port
• DLL for accurate data placement

Configurations

CYRS1542AV18 4 M x 18

CYRS1544AV18 2 M x 36

Functional Description

The CYRS1542AV18 and CYRS1544AV18 are synchronous pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with RadStop technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.

The QDR II+ architecture consists of two separate ports to access the memory the read port and the write port. The read port has dedicated data output bus to support read operations and the write port has dedicated data input bus to support write operations. QDR II+ architecture completely eliminates the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read are latched on the rising edges of the input K clock whereas addresses for write are latched on the falling edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of each another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit words for CYRS1542AV18, or two 36-bit words for CYRS1544AV18 that burst sequentially into or out of the device. Since data can be transferred on every rising edge of both input clocks K and K# , memory bandwidth is maximized while simplifying system design by eliminating bus “turnarounds”.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks as well. Reads and writes are conducted with on-chip synchronous self-timed circuitry.

For a complete list of related resources, click here.

Selection Guide

Description Maximum operating frequency Maximum operating current concurrent R/W
250 MHz Unit 250 MHz
x 18 1700 mA x 36 1700
• San Jose, CA 95134-1709
• 408-943-2600

CYRS1542AV18 CYRS1544AV18

Logic Block Diagram CYRS1542AV18

D[17:0]

A 20:0 21

Address Register
Power Up Sequence 21 DLL Constraints 21 Maximum Ratings 22 Operating Range 22 Electrical Characteristics 22 DC Electrical Characteristics 22 AC Electrical Characteristics 23 Radiation Performance 23 Capacitance 23 Thermal Resistance 23 AC Test Loads and Waveforms 24 Switching Characteristics 25 Switching Waveforms 26 Ordering Information 27 Ordering Code Definitions 27 Package Diagram 28 Acronyms 29 Document Conventions 29 Units of Measure 29 Glossary 30 Document History Page 31 Sales, Solutions, and Legal Information 34 Worldwide Sales and Design Support 34 Products 34 Solutions 34 Cypress Developer Community 34 Technical Support 34

Page 3 of 34

CYRS1542AV18 CYRS1544AV18

Manufacturing Flow

Step

Screen

Method

Requirement
1 Wafer lot acceptance test

TM 5007
2 Internal visual
2010, Condition A
100%
3 Serialization
100%
4 Temperature cycling
1010, Condition C, 50 cycles minimum
100%
5 Constant acceleration
2001, YI orientation only
100%

Condition TBD package in design
7 Particle impact noise detection PIND
2020 Condition A
100%
8 Radiographic X-ray
2012, one view Y-1 orientation only
9 Pre burn in electrical parameters

In accordance with applicable Cypress specification
100%
10 Dynamic burn in
1015, Condition D
100%
240 hours at 125 °C or 120 hours at 150 °C minimum
11 Interim post dynamic burn in electricals

In accordance with applicable Cypress device specifications
100%
12 Static burn in
1015, Condition C, 72 hours at 150 °C or 144 hours at 125 °C minimum
100%
13 Interim post static burn in electricals
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for x 18 option , contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
250 CYRS1542AV18-250GCMB
250 CYRS1544AV18-250GCMB
250 CYPT1542AV18-250GCMB
250 CYPT1544AV18-250GCMB
250 5962F1120101QXA
250 5962F1120101VXA
250 5962F1120201QXA
250 5962F1120201VXA
72M QDR II+, x 18, Burst of 2
72M QDR II+, x 36, Burst of 2
72M QDR II+, x 18, Burst of 2, Prototype
72M QDR II+, x 36, Burst of 2, Prototype
72M QDR II+, x 18, Burst of 2, DLAM Part
72M QDR II+, x 18, Burst of 2, DLAM Part
72M QDR II+, x 36, Burst of 2, DLAM Part
72M QDR II+, x 36, Burst of 2, DLAM Part

Package Diagram

Package Type

Operating Range
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
001-58969 165-ball CCGA 21 x 25 x mm Military
Ordering Code Definitions CY XX 154X A V18 - 250 GC M B

Page 27 of 34

CYRS1542AV18 CYRS1544AV18

Package Diagram

Figure 165-ball Ceramic Column Grid Array CCGA 21 x 25 mm Package Outline, 001-58969
001-58969 *D

Page 28 of 34

Acronyms

Acronym
byte write select

CCGA
ceramic column grid array
double error detection
delay lock loop
double data rate

DSCC
defense supply center columbus

EDAC
error detection and correction

HSTL
high speed transceiver logic
input/output

JTAG

Joint Test Action Group
least significant bit

LSBU
logical single-bit upsets

LMBU
logical multi-bit upsets
most significant bit
percent defect allowable

PIND
particle impact noise detection
percent defective allowable
quad data rate
read port select
single error correction
single event latch up

SRAM
static random access memory
test access port
values for tCO parameter under Output Time parameter . Updated Ordering Information Added 200-MHz part numbers

CYRS1542AV18-250GCMB, CYRS1544AV18-250GCMB for Burst 2 mode .

Updated Package Diagram.

Added Units of Measure.
3281455 06/13/2011

HRP Changed status from Advanced to Final.

Updated Configurations corrected typo .

Updated Selection Guide.

Updated DC Electrical Characteristics maximum current limit values for the
parameters IDD and ISB1 based on device characterization . Updated Radiation Performance Limits of Radiation Data based on RHA
qualification.

Updated Thermal Resistance.

Updated Switching Characteristics Minimum and Maximum timing values for
the parameters tco, tDOH, tCCQO, tCQOH based on device characterization . Updated Ordering Information Removed x 18 option from ordering table .

Updated Package Diagram.

Changed DLL lockup cycles from 2048 to 10240 throughout document.

Updated in new template.
3471321 12/21/2011

HRP Updated Identification Register Definitions Replaced the value of Cypress
device ID 28:12 from 11010011010010100 to 11010010100010100 for

CYRS1542AV18 and replaced the value of Cypress device ID 28:12 from
11010011010100100 to 11010010100100100 for CYRS1544AV18 .
3524961 02/14/2012 HRP Updated Prototyping Options under Radiation Performance. Added two
devices .

Updated Application Example.

Updated Truth Table.

Updated Maximum Ratings.

Updated Radiation Performance.

Updated Capacitance.

Updated Thermal Resistance.

Updated Switching Characteristics.
Updated Ordering Information Removed 200 MHz speed part

CYRS1544AV18-200GCMB .
3537277 02/29/2012 HRP Updated Radiation Data under Radiation Performance.
Updated Ordering Information Removed the part number

CYRS1544AV18-250GCMB and added the part numbers

CYRS1543AV18-250GCMB,

CYRS1545AV18-250GCMB,

CYPT1543AV18-250GCMB,

CYPT1545AV18-250GCMB,
5962F1120201VXA and 5962F1120202VXA .
3580538 04/12/2012 HRP Updated Ordering Information Updated part numbers .
3617759 05/15/2012 HRP Updated Radiation Performance Updated Prototyping Options .
Updated Ordering Information Added part 5962F1120101VXA .

Updated Glossary.

Page 31 of 34

CYRS1542AV18 CYRS1544AV18

Document History Page continued

Document Title CYRS1542AV18/CYRS1544AV18, 72-Mbit II+ SRAM Two-Word Burst Architecture with RadStop Technology Document Number 001-60006

ECN No.

Submission Date

Orig. of Change

Description of Change
3640834 06/08/2012 HRP Updated Radiation Performance Updated Prototyping Options .

Renamed the section Class V Flow as Manufacturing Flow.

Updated Glossary.
3857750 01/04/2013 HRP Updated Ordering Information Updated part numbers .
3900846 02/11/2013

HRP Updated Neutron Soft Error Immunity Changed value of Test Conditions of

SEL parameter from 85 °C to 125 °C .

Updated Pin Definitions Changed Pin Name from A to A[x:0] .

Updated Functional Overview Updated Qualification and Screening Replaced Class V with Class Q .
3934155 03/15/2013 MISA Updated Selection Guide:

Changed Maximum operating current concurrent R/W corresponding to
“x 18” for 250 MHz frequency from 1650 mA to 1700 mA.

Changed Maximum operating current concurrent R/W corresponding to
“x 36” for 250 MHz frequency from 1650 mA to 1700 mA.

Updated Electrical Characteristics Updated DC Electrical Characteristics Changed maximum value of IDD parameter corresponding to “x 18” for 250 MHz frequency from 1650 mA to 1700 mA. Changed maximum value of IDD parameter corresponding to “x 36” for 250 MHz frequency from 1650 mA to 1700 mA. Changed maximum value of ISB1 parameter corresponding to “x 18” for 250 MHz frequency from 600 mA to 660 mA. Changed maximum value of ISB1 parameter corresponding to “x 36” for 250 MHz frequency from 550 mA to 660 mA. Removed 200 MHz frequency related information.

Updated Switching Characteristics Changed maximum value of tCO and tCHQV parameters from ns to ns. Changed minimum value of tDOH and tCHQX parameters from ns to ns. Changed maximum value of tCCQO and tCHCQV parameters from ns to ns. Changed minimum value of tCQOH and tCHCQX parameters from ns to ns. Removed 200 MHz frequency related information.
4286754 02/21/2014 MISA Updated Functional Overview:

Updated Qualification and Screening:

Replaced “Class Q” with “Class Q, Class V”.
Updated Ordering Information Updated part numbers .

Updated to new template.

Page 32 of 34

CYRS1542AV18 CYRS1544AV18

Document History Page continued

Document Title CYRS1542AV18/CYRS1544AV18, 72-Mbit II+ SRAM Two-Word Burst Architecture with RadStop Technology Document Number 001-60006

ECN No.

Submission Date

Orig. of Change

Description of Change
4618500 01/09/2015 PRIT Updated Radiation Performance:

Updated Radiation Data Updated 2nd bulleted point.

Updated Prototyping Options Updated 1st bulleted point.

Updated Functional Description:

Updated description.

Added “For a complete list of related resources, click here.” at the end.

Updated Pin Definitions:

Updated description of CQ and CQ pins.

Updated Functional Overview:

Updated description.

Updated Read Operations:

Updated description.

Updated Write Operations:

Updated description.

Updated Application Example:

Updated Figure

Page 33 of 34

CYRS1542AV18 CYRS1544AV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products

Solutions

Automotive
cypress.com/go/automotive
psoc.cypress.com/solutions

Clocks & Buffers
cypress.com/go/clocks

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Interface Lighting & Power Control

Memory PSoC

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 5962F1120101QXA Datasheet file may be downloaded here without warranties.

Datasheet ID: 5962F1120101QXA 508230