CYRF69313-40LTXC

CYRF69313-40LTXC Datasheet

CYRF69313

Part	Datasheet
CYRF69313-40LTXC	CYRF69313-40LTXC (pdf)

Related Parts	Information
CYRF69313-40LFXC	CYRF69313-40LFXC

PDF Datasheet Preview
CYRF69313 Programmable Radio-on-Chip LPstar Programmable Radio-on-Chip LPstar • Radio System-on-Chip, with built-in 8-bit MCU in a single device. • Operates in the unlicensed worldwide Industrial, Scientific, and Medical ISM band GHz to GHz . • On Air compatible with second generation radio WirelessUSB LP and PRoC LP. • Pin-to-pin compatible with PRoC LP except the pin 31 and pin Intelligent • M8C based 8-bit CPU, optimized for human interface devices HID applications • 256 bytes of SRAM • 8 Kbytes of flash memory with EEPROM emulation • In-System reprogrammable through pins • CPU speed up to 12 MHz • 16-bit free running timer • Low power wakeup timer • 12-bit programmable interval timer with interrupts • Watchdog timer Low Power • 21 mA operating current Transmit at dBm • Sleep current less than 1 µA • Operating voltage from V to V DC • Fast startup and fast channel changes • Supports coin-cell operated applications Reliable and Robust • Receive sensitivity typical dBm • AutoRate dynamic data rate reception Enables data reception for any of the supported bit rates automatically. DSSS 250 Kbps , GFSK 1 Mbps • Operating temperature from 0 °C to 70 °C • Closed-loop frequency synthesis for minimal frequency drift Simple Development • Auto transaction sequencer ATS MCU can stay sleeping longer to save power • Framing, length, CRC16, and Auto ACK • Separate 16 byte transmit and receive FIFOs • Receive signal strength indication RSSI • Built-in serial peripheral interface SPI control while in sleep mode • Advanced development tools based on Cypress’s Tools • Flexible I/O • 2 mA source current on all GPIO pins. Configurable 8 mA or 50 mA/pin current sink on designated pins • Each GPIO pin supports high impedance inputs, configurable pull-up, open-drain output, CMOS/TTL inputs, and CMOS output • Maskable interrupts on all I/O pins BOM Savings • Low external component count • Small footprint 40-pin QFN 6 mm x 6 mm • GPIOs that require no external components • Operates off a single crystal • Integrated V regulator • Integrated pull-up on USB Specification Compliance • Conforms to USB specification version • Conforms to USB HID specification version • Supports one low speed USB device address • Supports one control endpoint and two data end points • Integrated USB transceiver Applications • Wireless keyboards and mice • Presentation tools • Wireless gamepads • Remote controls • Toys • Fitness • San Jose, CA 95134-1709 • 408-943-2600 Logic Block Diagram Vbus 1ohm CYRF69313 MOSI SCK nSS RST VBat2 VBat1 VBat0 VCC4 VCC3 VCC2 VCC1 P1.2 / VReg VDD_MICRO Microcontroller P0_1,3,4,7 4 P1_6:7 2 Function P1.5/MOSI P1.4/SCK P2_0:1 2 P1.3/nSS D+/D2 GND Xtal RESV GND VSS RFbias Radio Function Clock Architecture Description 26 CPU Clock During Sleep Mode 32 Reset 32 Power-on Reset 34 Watchdog Timer Reset 34 Sleep Mode 34 Sleep Sequence 34 Wakeup Sequence 35 Low Power in Sleep Mode 35 Power-on Reset Control 37 POR Compare State 37 ECO Trim Register 37 General-Purpose I/O Ports 38 Port Data Registers 38 GPIO Port Configuration 39 GPIO Configurations for Low Power Mode 43 Serial Peripheral Interface SPI 44 SPI Data Register 45 SPI Configure Register 45 Timer Registers 47 Registers 47 Interrupt Controller 50 Architectural Description 50 Interrupt Processing 51 Interrupt Latency 51 Interrupt Registers 51 USB Transceiver 56 USB Transceiver Configuration 56 USB Serial Interface Engine SIE 56 USB Device 57 Endpoint 0 Mode 58 Endpoint Data Buffers 60 USB Mode Tables 61 Mode Column 61 Encoding Column 61 SETUP, IN, and OUT Columns 61 Details of Mode for Differing Traffic Conditions 62 Register Summary 64 Radio Function Register Descriptions 66 Absolute Maximum Ratings 67 DC Characteristics 67 RF Characteristics 69 AC Test Loads and Waveforms for Digital Pins 70 AC Characteristics 71 Switching Waveforms 72 Ordering Information 76 Ordering Code Definitions 76 Package Handling 77 Package Diagrams 77 Acronyms 79 Document Conventions 79 Units of Measure 79 Document History Page 80 Page 3 of 81 Sales, Solutions, and Legal Information 81 Worldwide Sales and Design Support 81 Products 81 Solutions 81 Cypress Developer Community 81 Technical Support 81 CYRF69313 Page 4 of 81 CYRF69313 Functional Description PRoC LPstar devices are integrated radio and microcontroller functions in the same package to provide a dual role single-chip solution. Communication between the microcontroller and the radio is via the SPI interface between both functions. Functional Overview The CYRF69313 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69313 is designed to implement low cost wireless systems operating in the worldwide GHz Industrial, Scientific, and Medical ISM frequency band GHz . GHz Radio Function The SoC contains a GHz, 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication RSSI , and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels regulations may limit the use of some of these channels in certain jurisdictions . The baseband performs DSSS spreading/despreading, Start of Packet SOP , End of Packet EOP detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge ACK handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. This enables the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both. It changes to lower data rates at longer distances or in high interference environments or both. USB Microcontroller Function The microcontroller function is based on the powerful CYRF69313 microcontroller. It is an 8-bit Flash programmable microcontroller with integrated low speed USB interface. The microcontroller has up to 14 GPIO pins to support USB, PS/2 and other applications. Each GPIO port supports high impedance inputs, configurable pull-up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port The microcontroller features an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements 24 MHz ± The PRoC LPstar has up to 8 Kbytes of Flash for user’s firmware code and up to 256 bytes of RAM for stack space and user variables. Backward Compatibility The CYRF69313 IC is fully interoperable with the main modes of the second generation Cypress radio SoC namely the CYRF6936, CYRF69103 and CYRF69213. CYRF69313 IC device may transmit data to or receive data from a second generation device, or both. Page 5 of 81 Pinouts CYRF69313 Figure 40-pin QFN pinout NC 31 P1.6 32 VIO 33 RST 34 P1.7 35 VDD_1.8 36 GND 37 P0.7 38 VBAT0 39 V CC 40 Corner tabs P0.4 1 XTAL 2 VCC 3 P0.3 4 P0.1 5 VBAT1 6 VCC 7 P2.1 8 VBAT2 9 RFBIAS 10 CYRF69313 PRoC LPstar * E- PAD Bottom Side 30 XOUT/ GPIO 29 MISO / GPIO 28 P1. 5 / MOSI 27 IRQ / GPIO 26 P1. 4 / SCK 25 P1. 3 / SS 24 P1. 2 23 VDD_ Micro 22 P1.1/D21 P1.0/D+ 20 NC 19 RESV 18 NC 17 NC 16 VCC 15 P2.0 14 NC 13 RFN 12 GND 11 RFP Pin Configuration Name Function P0.4 Individually configured GPIO Ordering Information Package 40-pin Pb-free QFN 6 x 6 mm Sawn 40-pin Pb-free QFN 6 x 6 mm Punch Ordering Part Number CYRF69313-40LTXC CYRF69313-40LFXC Ordering Code Definitions CY RF 69313 - 40 LX X C In Production NRND Status Temperature Range C = Commercial Pb-free Package Type LX = LT or LF LT = QFN Sawn Type LF = QFN Punch Type No of pins in package 40-pin Marketing Code RF = Wireless radio frequency product line Company ID CY = Cypress Page 76 of 81 CYRF69313 Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may degrade device reliability. Table Package Handling Parameter TBAKETEMP tBAKETIME Description Bake Temperature Bake Time Min see package label Unit see package label °C hours Package Diagrams Figure 40-pin QFN 6 x 6 x mm LT40B x mm E-Pad Sawn Package Outline, 001-13190 001-13190 H Page 77 of 81 CYRF69313 Package Diagrams continued Figure 40-pin QFN 6 x 6 mm LF40A/LY40A x E-Pad Punch Package Outline, 001-12917 [16] 001-12917 D Note Not Recommended for New Design. Page 78 of 81 Acronyms Table Acronyms Used in this Document Acronym Acknowledge packet received, no errors Bit Error Rate Bill Of Materials CMOS Complementary Metal Oxide Semiconductor Cyclic Redundancy Check Forward Error Correction Frame Error Rate GFSK Gaussian Frequency-Shift Keying 3532316 KKCN 02/28/2012 Updated Ordering Information Added MPN CYRF69313-40LTXC and Ordering Code Definitions. Added Package Handling. Updated Package Diagrams Added spec 3735882 ANKC 09/06/2012 Updated Ordering Information No change in part numbers, included a column “Status” . and referred the same note in Figure Updated in new template. 3983055 ANKC 04/27/2013 Updated Pin Configuration Updated Name and Function of Pin 21 and Pin Updated Package Diagrams Replaced spec 001-44328 F with spec 001-13190 H . 4316770 ANKC 03/21/2014 Updated Memory Organization: Updated Data Memory Organization: Updated Figure Updated in new template. Page 80 of 81 CYRF69313 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Solutions Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP Interface Lighting & Power Control Memory PSoC cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/psoc Cypress Developer Community \| Forums \| Blogs \| Video \| Training Technical Support cypress.com/go/support Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.

PDF Datasheet Preview

CYRF69313

Programmable Radio-on-Chip LPstar

Programmable Radio-on-Chip LPstar
• Radio System-on-Chip, with built-in 8-bit MCU in a single device.
• Operates in the unlicensed worldwide Industrial, Scientific, and Medical ISM band GHz to GHz .
• On Air compatible with second generation radio WirelessUSB LP and PRoC LP.
• Pin-to-pin compatible with PRoC LP except the pin 31 and pin

Intelligent
• M8C based 8-bit CPU, optimized for human interface devices

HID applications
• 256 bytes of SRAM
• 8 Kbytes of flash memory with EEPROM emulation
• In-System reprogrammable through pins
• CPU speed up to 12 MHz
• 16-bit free running timer
• Low power wakeup timer
• 12-bit programmable interval timer with interrupts
• Watchdog timer

Low Power
• 21 mA operating current Transmit at dBm
• Sleep current less than 1 µA
• Operating voltage from V to V DC
• Fast startup and fast channel changes
• Supports coin-cell operated applications

Reliable and Robust
• Receive sensitivity typical dBm
• AutoRate dynamic data rate reception

Enables data reception for any of the supported bit rates automatically.

DSSS 250 Kbps , GFSK 1 Mbps
• Operating temperature from 0 °C to 70 °C
• Closed-loop frequency synthesis for minimal frequency drift

Simple Development
• Auto transaction sequencer ATS MCU can stay sleeping
longer to save power
• Framing, length, CRC16, and Auto ACK
• Separate 16 byte transmit and receive FIFOs
• Receive signal strength indication RSSI
• Built-in serial peripheral interface SPI control while in sleep
mode
• Advanced development tools based on Cypress’s Tools
• Flexible I/O
• 2 mA source current on all GPIO pins. Configurable 8 mA or
50 mA/pin current sink on designated pins
• Each GPIO pin supports high impedance inputs, configurable
pull-up, open-drain output, CMOS/TTL inputs, and CMOS output
• Maskable interrupts on all I/O pins

BOM Savings
• Low external component count
• Small footprint 40-pin QFN 6 mm x 6 mm
• GPIOs that require no external components
• Operates off a single crystal
• Integrated V regulator
• Integrated pull-up on

USB Specification Compliance
• Conforms to USB specification version
• Conforms to USB HID specification version
• Supports one low speed USB device address
• Supports one control endpoint and two data end points
• Integrated USB transceiver

Applications
• Wireless keyboards and mice
• Presentation tools
• Wireless gamepads
• Remote controls
• Toys
• Fitness
• San Jose, CA 95134-1709
• 408-943-2600

Logic Block Diagram

Vbus
1ohm

CYRF69313

MOSI SCK nSS

RST VBat2 VBat1 VBat0 VCC4 VCC3 VCC2 VCC1

P1.2 / VReg

VDD_MICRO

Microcontroller

P0_1,3,4,7 4

P1_6:7 2

Function

P1.5/MOSI P1.4/SCK

P2_0:1 2

P1.3/nSS

D+/D2

GND Xtal RESV GND VSS

RFbias

Radio Function
Clock Architecture Description 26 CPU Clock During Sleep Mode 32 Reset 32 Power-on Reset 34 Watchdog Timer Reset 34 Sleep Mode 34 Sleep Sequence 34 Wakeup Sequence 35 Low Power in Sleep Mode 35 Power-on Reset Control 37 POR Compare State 37 ECO Trim Register 37 General-Purpose I/O Ports 38 Port Data Registers 38 GPIO Port Configuration 39 GPIO Configurations for Low Power Mode 43 Serial Peripheral Interface SPI 44 SPI Data Register 45 SPI Configure Register 45 Timer Registers 47 Registers 47 Interrupt Controller 50 Architectural Description 50 Interrupt Processing 51 Interrupt Latency 51 Interrupt Registers 51 USB Transceiver 56 USB Transceiver Configuration 56 USB Serial Interface Engine SIE 56 USB Device 57 Endpoint 0 Mode 58 Endpoint Data Buffers 60 USB Mode Tables 61 Mode Column 61 Encoding Column 61 SETUP, IN, and OUT Columns 61 Details of Mode for Differing Traffic Conditions 62 Register Summary 64 Radio Function Register Descriptions 66 Absolute Maximum Ratings 67 DC Characteristics 67 RF Characteristics 69 AC Test Loads and Waveforms for Digital Pins 70 AC Characteristics 71 Switching Waveforms 72 Ordering Information 76 Ordering Code Definitions 76 Package Handling 77 Package Diagrams 77 Acronyms 79 Document Conventions 79 Units of Measure 79 Document History Page 80

Page 3 of 81

Sales, Solutions, and Legal Information 81 Worldwide Sales and Design Support 81 Products 81 Solutions 81 Cypress Developer Community 81 Technical Support 81

CYRF69313

Page 4 of 81

CYRF69313

Functional Description

PRoC LPstar devices are integrated radio and microcontroller functions in the same package to provide a dual role single-chip solution.

Communication between the microcontroller and the radio is via the SPI interface between both functions.

Functional Overview

The CYRF69313 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69313 is designed to implement low cost wireless systems operating in the worldwide GHz Industrial, Scientific, and Medical ISM frequency band GHz .

GHz Radio Function

The SoC contains a GHz, 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication RSSI , and SPI interface for data transfer and device configuration.

The radio supports 98 discrete 1 MHz channels regulations may limit the use of some of these channels in certain jurisdictions .

The baseband performs DSSS spreading/despreading, Start of Packet SOP , End of Packet EOP detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge ACK handshake packets whenever a valid packet is received.

When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. This enables the implementation of mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both. It changes to lower data rates at longer distances or in high interference environments or both.

USB Microcontroller Function

The microcontroller function is based on the powerful CYRF69313 microcontroller. It is an 8-bit Flash programmable microcontroller with integrated low speed USB interface.

The microcontroller has up to 14 GPIO pins to support USB, PS/2 and other applications. Each GPIO port supports high impedance inputs, configurable pull-up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port

The microcontroller features an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements 24 MHz ±

The PRoC LPstar has up to 8 Kbytes of Flash for user’s firmware code and up to 256 bytes of RAM for stack space and user variables.

Backward Compatibility The CYRF69313 IC is fully interoperable with the main modes of the second generation Cypress radio SoC namely the CYRF6936, CYRF69103 and CYRF69213.

CYRF69313 IC device may transmit data to or receive data from a second generation device, or both.

Page 5 of 81

Pinouts

CYRF69313

Figure 40-pin QFN pinout

NC 31 P1.6 32

VIO 33 RST 34 P1.7 35 VDD_1.8 36 GND 37 P0.7 38 VBAT0 39 V CC 40

Corner tabs

P0.4 1 XTAL 2

VCC 3 P0.3 4 P0.1 5 VBAT1 6 VCC 7 P2.1 8 VBAT2 9 RFBIAS 10

CYRF69313 PRoC LPstar
* E- PAD Bottom Side
30 XOUT/ GPIO 29 MISO / GPIO 28 P1. 5 / MOSI 27 IRQ / GPIO 26 P1. 4 / SCK 25 P1. 3 / SS 24 P1. 2 23 VDD_ Micro 22 P1.1/D21 P1.0/D+
20 NC 19 RESV 18 NC 17 NC 16 VCC 15 P2.0 14 NC 13 RFN 12 GND 11 RFP

Pin Configuration

Name

Function

P0.4 Individually configured GPIO
Ordering Information

Package 40-pin Pb-free QFN 6 x 6 mm Sawn 40-pin Pb-free QFN 6 x 6 mm Punch
Ordering Part Number CYRF69313-40LTXC CYRF69313-40LFXC
Ordering Code Definitions CY RF 69313 - 40 LX X C

In Production NRND

Status

Temperature Range C = Commercial Pb-free

Package Type LX = LT or LF LT = QFN Sawn Type LF = QFN Punch Type

No of pins in package 40-pin

Marketing Code RF = Wireless radio frequency product line

Company ID CY = Cypress

Page 76 of 81

CYRF69313

Package Handling

Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may degrade device reliability.

Table Package Handling

Parameter TBAKETEMP tBAKETIME

Description Bake Temperature Bake Time

Min see package label

Unit
see package label °C
hours

Package Diagrams

Figure 40-pin QFN 6 x 6 x mm LT40B x mm E-Pad Sawn Package Outline, 001-13190
001-13190 *H

Page 77 of 81

CYRF69313

Package Diagrams continued

Figure 40-pin QFN 6 x 6 mm LF40A/LY40A x E-Pad Punch Package Outline, 001-12917 [16]
001-12917 *D

Note Not Recommended for New Design.

Page 78 of 81

Acronyms

Table Acronyms Used in this Document

Acronym

Acknowledge packet received, no errors

Bit Error Rate

Bill Of Materials

CMOS Complementary Metal Oxide Semiconductor

Cyclic Redundancy Check

Forward Error Correction

Frame Error Rate

GFSK

Gaussian Frequency-Shift Keying
3532316 KKCN 02/28/2012 Updated Ordering Information Added MPN CYRF69313-40LTXC and
Ordering Code Definitions.

Added Package Handling.

Updated Package Diagrams Added spec
3735882 ANKC 09/06/2012 Updated Ordering Information No change in part numbers, included a column
“Status” .
and referred the same note in Figure

Updated in new template.
3983055 ANKC 04/27/2013 Updated Pin Configuration Updated Name and Function of Pin 21 and Pin

Updated Package Diagrams Replaced spec 001-44328 *F with spec
001-13190 *H .
4316770 ANKC 03/21/2014 Updated Memory Organization:

Updated Data Memory Organization:

Updated Figure

Updated in new template.

Page 80 of 81

CYRF69313

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products

Solutions

Automotive
cypress.com/go/automotive
psoc.cypress.com/solutions

Clocks & Buffers
cypress.com/go/clocks

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Interface Lighting & Power Control

Memory PSoC
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/psoc

Cypress Developer Community | Forums | Blogs | Video | Training

Technical Support cypress.com/go/support

Touch Sensing
cypress.com/go/touch

USB Controllers
cypress.com/go/USB

Wireless/RF
cypress.com/go/wireless

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYRF69313-40LTXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CYRF69313-40LTXC 508224