CYRF69303-40LFXC

CYRF69303-40LFXC Datasheet

CYRF69303

Part	Datasheet
CYRF69303-40LFXC	CYRF69303-40LFXC (pdf)

PDF Datasheet Preview
CYRF69303 Programmable Radio-on-Chip LPstar • Radio System-on-Chip with built-in 8-bit MCU in a single device. • Operates in the unlicensed worldwide Industrial, Scientific, and Medical ISM band GHz to GHz . • On Air compatible with second generation radio WirelessUSB LP and PRoC LP. • Pin-to-pin compatible with PRoC LP except the Pin31 and Pin37. Intelligent • M8C based 8-bit CPU, optimized for human interface devices HID applications • 256 bytes of SRAM • 8 Kbytes of flash memory with EEPROM emulation • In-system reprogrammable through pins • CPU speed up to 12 MHz • 16-bit free running timer • Low power wakeup timer • 12-bit programmable interval timer with interrupts • Watchdog timer Low Power • 21 mA operating current Transmit at dBm • Sleep current less than 1 • Operating voltage from V to V DC • Fast startup and fast channel changes • Supports coin cell operated applications Reliable & Robust • Receive sensitivity typical dBm • AutoRate - Dynamic Data Rate Reception Enables data reception for any of the supported bit rates automatically. DSSS 250 Kbps , GFSK 1 Mbps • Operating temperature from 0 °C to 70 °C • Closed-loop frequency synthesis for minimal frequency drift Simple Development • Auto transaction sequencer ATS MCU can remain in sleep state longer to save power • Framing, length, CRC16, and Auto ACK • Separate 16 byte transmit and receive FIFOs • Receive signal strength indication RSSI • Built-in serial peripheral interface SPI control while in Sleep Mode • Advanced development tools based on Cypress’s tools • Flexible I/O • 2 mA source current on all GPIO pins. Configurable 8 mA or 50 mA/pin current sink on designated pins • Each GPIO pin supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output • Maskable interrupts on all I/O pins BOM Savings • Low external component count • Small footprint 40-pin QFN 6 mm x 6 mm • GPIOs that require no external components • Operates off a single crystal Applications • Wireless keyboards and mice • Presentation tools • Wireless gamepads • Remote controls • Toys • Fitness • San Jose, CA 95134-1709 • 408-943-2600 Logic Block Diagram VDD_MICRO Microcontroller Function P0_1,3,4,7 4 P1_0:2,6:7 5 P2_0:1 2 P1.5/MOSI P1.4/SCK P1.3/nSS GND Xtal RESV GND Vdd MOSI SCK nSS RST VBat2 VBat1 VBat0 CYRF69303 VCC4 VCC3 VCC2 VCC1 Radio Function RFbias RFp RFn IRQ/GPIO MISO/GPIO XOUT/GPIO 12 MHz Page 2 of 66 CYRF69303 Contents Functional Description 4 Functional Overview 4 GHz Radio Function 4 Data Transmission Modes 4 Microcontroller Function 4 Backward Compatibility 4 Pinouts 5 Functional Block Overview 6 GHz Radio 6 Frequency Synthesizer 6 Baseband and Framer 6 Packet Buffers and Radio Configuration Registers 7 Auto Transaction Sequencer ATS 7 Interrupts 7 Clocks 8 GPIO Interface 8 Power-on Reset 8 Timers 8 Power Management 8 Low Noise Amplifier LNA and Received Signal Strength Indication RSSI 9 SPI Interface 9 Three-Wire SPI Interface 9 4-Wire SPI Interface 9 SPI Communication and Transactions 10 SPI I/O Voltage References 10 SPI Connects to External Devices 10 CPU Architecture 11 CPU Registers 11 Flags Register 11 Accumulator Register 12 Index Register 12 Stack Pointer Register 12 CPU Program Counter High Register 12 CPU Program Counter Low Register 12 Addressing Modes 13 Source Immediate 13 Source Direct 13 Source Indexed 13 Destination Direct 13 Destination Indexed 14 Destination Direct Source Immediate 14 Destination Indexed Source Immediate 14 Destination Direct Source Direct 14 Source Indirect Post Increment 15 Destination Indirect Post Increment 15 Instruction Set Summary 16 Memory Organization 17 Flash Program Memory Organization 17 Data Memory Organization 18 Flash 18 SROM 18 SROM Function Descriptions 19 Clocking 22 SROM Table Read Description 23 Clock Architecture Description 24 CPU Clock During Sleep Mode 28 Reset 29 Power-on Reset 30 Watchdog Timer Reset 30 Sleep Mode 30 Sleep Sequence 30 Low Power in Sleep Mode 31 Wakeup Sequence 31 Power-on Reset Control 32 POR Compare State 33 ECO Trim Register 33 General-Purpose I/O Ports 33 Port Data Registers 33 GPIO Port Configuration 34 GPIO Configurations for Low Power Mode 40 Serial Peripheral Interface SPI 41 SPI Data Register 42 SPI Configure Register 42 SPI Interface Pins 44 Timer Registers 44 Registers 44 Interrupt Controller 47 Architectural Description 47 Interrupt Processing 48 Interrupt Latency 48 Interrupt Registers 48 Microcontroller Function Register Summary 51 Radio Function Register Summary 53 Absolute Maximum Ratings 54 DC Characteristics T = 25 °C 54 AC Characteristics 56 RF Characteristics 60 Ordering Information 62 Ordering Code Definitions 62 Package Handling 63 Package Diagram 63 Acronyms 65 Document Conventions 65 Document History Page 66 Sales, Solutions, and Legal Information 66 Worldwide Sales and Design Support 66 Products 66 PSoC Solutions 66 Page 3 of 66 CYRF69303 Functional Description PRoC LPstar devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution. Communication between the microcontroller and the radio is through the radio’s SPI interface. Functional Overview The CYRF69303 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69303 is designed to implement low-cost wireless systems operating in the worldwide GHz Industrial, Scientific, and Medical ISM frequency band GHz to GHz . GHz Radio Function The SoC contains a GHz, 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, received signal strength indication RSSI , and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels regulations may limit the use of some of these channels in certain jurisdictions . The baseband performs DSSS spreading/despreading, Start of Packet SOP , End of Packet EOP detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge ACK handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. This enables the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both. It changes to lower data rates at longer distances or in high interference environments or both. Data Transmission Modes The radio supports two different data transmission modes: • In GFSK mode, data is transmitted at 1 Mbps, without any DSSS • In DSSS mode eight bits 8DR, 32 chip are encoded in each derived code symbol transmitted, resulting in effective 250 kbps data rate. 32 chip Pseudo Noise PN codes are supported. The two data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all sent in the same mode. In general, DSSS reduce packet error rate in any environment. Microcontroller Function The MCU function is an 8-bit Flash-programmable microcontroller. The instruction set is optimized specifically for HID and a variety of other embedded applications. The MCU function has up to 8 Kbytes of Flash for user’s code and up to 256 bytes of RAM for stack space and user variables. In addition, the MCU function includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free Running Timer, and 12-bit Programmable Interrupt Timer. The microcontroller has 15 GPIO pins grouped into multiple ports. With the exception of the four radio function GPIOs, each GPIO port supports high impedance inputs, configurable pull-up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port GPIO Port 0 has two dedicated pins that have independent interrupt vectors P0.3 - P0.4 . The microcontroller features an internal oscillator. Backward Compatibility The CYRF69303 IC is fully interoperable with the main modes of the second generation Cypress radio SoC namely the CYRF6936, CYRF69103 and CYRF69213. CYRF69303 IC device may transmit data to or receive data from a second generation device, or both. Page 4 of 66 Pinouts Figure Pin Diagram NC 31 P1.6 32 VIO 33 RST 34 P1.7 35 VDD_1.8 36 GND 37 P0.7 38 VBAT0 39 Vcc 40 Corner tabs P0.4 1 XTAL 2 VCC 3 P0.3 4 P0.1 5 VBAT1 6 VCC 7 P2.1 8 VBAT2 9 RFBIAS 10 CYRF69303 PRoC LPstar * E-PAD Bottom Side 30 XOUT / GPIO 29 MISO / GPIO 28 P1.5 / MOSI 27 IRQ / GPIO 26 P1.4 / SCK 25 P1.3 / SS 24 P1.2 23 VDD_Micro 22 P1.1 21 P1.0 CYRF69303 20 NC 19 RESV 18 NC 17 NC 16 VCC 15 P2.0 14 NC 13 RFN 12 GND 11 RFP Table Pin Definitions Ordering Information Package 40-pin Pb-free Punch-QFN 6 x 6 mm 40-pin Pb-free Sawn-QFN 6 x 6 mm Ordering Code Definitions CY RF 40 LF/T X C Ordering Part Number CYRF69303-40LFXC CYRF69303-40LTXC Temperature range Commercial X = Pb-free 40-pin QFN package F = Punch, T = Sawn Part number Marketing code RF = Wireless radio frequency product line Company ID CY = Cypress CYRF69303 Page 62 of 66 CYRF69303 Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may degrade device reliability. Table Package Handling Parameter TBAKETEMP tBAKETIME Description Bake Temperature Bake Time Min see package label Unit see package label °C hours Package Diagram Figure 40-Pin Pb-free Punch-QFN 6 x 6 mm SOLDERABLE EXPOSED PAD 001-12917 C Page 63 of 66 Figure 40-Pin Pb-free Sawn-QFN 6 x 6 mm CYRF69303 001-44328 F Page 64 of 66 CYRF69303 Acronyms Table Acronyms Used in this Document Acronym ACK BER BOM CMOS CRC FEC FER GFSK HBM ISM IRQ MCU NRZ PLL QFN RSSI RF Rx Tx Description Acknowledge packet received, no errors Bit error rate Bill of materials complementary metal oxide semiconductor cyclic redundancy check forward error correction frame error rate Gaussian frequency-shift keying Human body model Industrial, scientific, and medical interrupt request microcontroller unit non return to zero phase-locked loop Quad flat no-leads received signal strength indication radio frequency receive transmit Document Conventions Units of Measure Table Units of Measure Symbol °C dB Unit of Measure degree Celsius decibels dBc dBm Hz decibel relative to carrier decibel-milliwatt hertz KB Kbit kHz MHz mA 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microsecond microvolt microvolts root-mean-square microwatt milliampere millisecond millivolt 02/28/2012 Updated Ordering Information CYRF69303-40LTXC and Ordering Code 3532316 KKCN Definitions. Added Package Diagram Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks and Buffers Interface Lighting and Power Control Memory Optical and Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 66 of 66

PDF Datasheet Preview

CYRF69303

Programmable Radio-on-Chip LPstar
• Radio System-on-Chip with built-in 8-bit MCU in a single device.
• Operates in the unlicensed worldwide Industrial, Scientific, and Medical ISM band GHz to GHz .
• On Air compatible with second generation radio WirelessUSB LP and PRoC LP.
• Pin-to-pin compatible with PRoC LP except the Pin31 and Pin37.

Intelligent
• M8C based 8-bit CPU, optimized for human interface devices

HID applications
• 256 bytes of SRAM
• 8 Kbytes of flash memory with EEPROM emulation
• In-system reprogrammable through pins
• CPU speed up to 12 MHz
• 16-bit free running timer
• Low power wakeup timer
• 12-bit programmable interval timer with interrupts
• Watchdog timer

Low Power
• 21 mA operating current Transmit at dBm
• Sleep current less than 1
• Operating voltage from V to V DC
• Fast startup and fast channel changes
• Supports coin cell operated applications

Reliable & Robust
• Receive sensitivity typical dBm
• AutoRate - Dynamic Data Rate Reception Enables data reception for any of the supported bit rates automatically. DSSS 250 Kbps , GFSK 1 Mbps
• Operating temperature from 0 °C to 70 °C
• Closed-loop frequency synthesis for minimal frequency drift

Simple Development
• Auto transaction sequencer ATS MCU can remain in sleep
state longer to save power
• Framing, length, CRC16, and Auto ACK
• Separate 16 byte transmit and receive FIFOs
• Receive signal strength indication RSSI
• Built-in serial peripheral interface SPI control while in Sleep

Mode
• Advanced development tools based on Cypress’s tools
• Flexible I/O
• 2 mA source current on all GPIO pins. Configurable 8 mA or
50 mA/pin current sink on designated pins
• Each GPIO pin supports high impedance inputs, configurable
pull up, open drain output, CMOS/TTL inputs, and CMOS output
• Maskable interrupts on all I/O pins

BOM Savings
• Low external component count
• Small footprint 40-pin QFN 6 mm x 6 mm
• GPIOs that require no external components
• Operates off a single crystal

Applications
• Wireless keyboards and mice
• Presentation tools
• Wireless gamepads
• Remote controls
• Toys
• Fitness
• San Jose, CA 95134-1709
• 408-943-2600

Logic Block Diagram

VDD_MICRO

Microcontroller Function

P0_1,3,4,7 4

P1_0:2,6:7 5

P2_0:1 2

P1.5/MOSI P1.4/SCK P1.3/nSS

GND Xtal RESV GND Vdd

MOSI SCK nSS

RST VBat2 VBat1 VBat0

CYRF69303

VCC4 VCC3 VCC2 VCC1

Radio Function

RFbias RFp RFn

IRQ/GPIO MISO/GPIO XOUT/GPIO
12 MHz

Page 2 of 66

CYRF69303

Contents

Functional Description 4 Functional Overview 4

GHz Radio Function 4 Data Transmission Modes 4 Microcontroller Function 4 Backward Compatibility 4 Pinouts 5 Functional Block Overview 6 GHz Radio 6 Frequency Synthesizer 6 Baseband and Framer 6 Packet Buffers and Radio Configuration Registers 7 Auto Transaction Sequencer ATS 7 Interrupts 7 Clocks 8 GPIO Interface 8 Power-on Reset 8 Timers 8 Power Management 8 Low Noise Amplifier LNA and Received Signal Strength Indication RSSI 9 SPI Interface 9 Three-Wire SPI Interface 9 4-Wire SPI Interface 9 SPI Communication and Transactions 10 SPI I/O Voltage References 10 SPI Connects to External Devices 10 CPU Architecture 11 CPU Registers 11 Flags Register 11 Accumulator Register 12 Index Register 12 Stack Pointer Register 12 CPU Program Counter High Register 12 CPU Program Counter Low Register 12 Addressing Modes 13 Source Immediate 13 Source Direct 13 Source Indexed 13 Destination Direct 13 Destination Indexed 14 Destination Direct Source Immediate 14 Destination Indexed Source Immediate 14 Destination Direct Source Direct 14 Source Indirect Post Increment 15 Destination Indirect Post Increment 15 Instruction Set Summary 16 Memory Organization 17 Flash Program Memory Organization 17 Data Memory Organization 18
Flash 18 SROM 18 SROM Function Descriptions 19 Clocking 22 SROM Table Read Description 23 Clock Architecture Description 24 CPU Clock During Sleep Mode 28 Reset 29 Power-on Reset 30 Watchdog Timer Reset 30 Sleep Mode 30 Sleep Sequence 30 Low Power in Sleep Mode 31 Wakeup Sequence 31 Power-on Reset Control 32 POR Compare State 33 ECO Trim Register 33 General-Purpose I/O Ports 33 Port Data Registers 33 GPIO Port Configuration 34 GPIO Configurations for Low Power Mode 40 Serial Peripheral Interface SPI 41 SPI Data Register 42 SPI Configure Register 42 SPI Interface Pins 44 Timer Registers 44 Registers 44 Interrupt Controller 47 Architectural Description 47 Interrupt Processing 48 Interrupt Latency 48 Interrupt Registers 48 Microcontroller Function Register Summary 51 Radio Function Register Summary 53 Absolute Maximum Ratings 54 DC Characteristics T = 25 °C 54 AC Characteristics 56 RF Characteristics 60 Ordering Information 62 Ordering Code Definitions 62 Package Handling 63 Package Diagram 63 Acronyms 65 Document Conventions 65 Document History Page 66 Sales, Solutions, and Legal Information 66 Worldwide Sales and Design Support 66 Products 66 PSoC Solutions 66

Page 3 of 66

CYRF69303

Functional Description

PRoC LPstar devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution.

Communication between the microcontroller and the radio is through the radio’s SPI interface.

Functional Overview

The CYRF69303 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69303 is designed to implement low-cost wireless systems operating in the worldwide GHz Industrial, Scientific, and Medical ISM frequency band GHz to GHz .

GHz Radio Function

The SoC contains a GHz, 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, received signal strength indication RSSI , and SPI interface for data transfer and device configuration.

The radio supports 98 discrete 1 MHz channels regulations may limit the use of some of these channels in certain jurisdictions .

The baseband performs DSSS spreading/despreading, Start of Packet SOP , End of Packet EOP detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge ACK handshake packets whenever a valid packet is received.

When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. This enables the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both. It changes to lower data rates at longer distances or in high interference environments or both.

Data Transmission Modes

The radio supports two different data transmission modes:
• In GFSK mode, data is transmitted at 1 Mbps, without any DSSS
• In DSSS mode eight bits 8DR, 32 chip are encoded in each derived code symbol transmitted, resulting in effective 250 kbps data rate.
32 chip Pseudo Noise PN codes are supported. The two data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all sent in the same mode. In general, DSSS reduce packet error rate in any environment.

Microcontroller Function

The MCU function is an 8-bit Flash-programmable microcontroller. The instruction set is optimized specifically for HID and a variety of other embedded applications.

The MCU function has up to 8 Kbytes of Flash for user’s code and up to 256 bytes of RAM for stack space and user variables.

In addition, the MCU function includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free Running Timer, and 12-bit Programmable Interrupt Timer.

The microcontroller has 15 GPIO pins grouped into multiple ports. With the exception of the four radio function GPIOs, each GPIO port supports high impedance inputs, configurable pull-up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port GPIO Port 0 has two dedicated pins that have independent interrupt vectors P0.3 - P0.4 .

The microcontroller features an internal oscillator.

Backward Compatibility

The CYRF69303 IC is fully interoperable with the main modes of the second generation Cypress radio SoC namely the CYRF6936, CYRF69103 and CYRF69213.

CYRF69303 IC device may transmit data to or receive data from a second generation device, or both.

Page 4 of 66

Pinouts

Figure Pin Diagram

NC 31 P1.6 32

VIO 33 RST 34 P1.7 35 VDD_1.8 36 GND 37 P0.7 38 VBAT0 39 Vcc 40

Corner tabs

P0.4 1 XTAL 2

VCC 3 P0.3 4 P0.1 5 VBAT1 6 VCC 7 P2.1 8 VBAT2 9 RFBIAS 10

CYRF69303 PRoC LPstar
* E-PAD Bottom Side
30 XOUT / GPIO 29 MISO / GPIO 28 P1.5 / MOSI 27 IRQ / GPIO 26 P1.4 / SCK 25 P1.3 / SS 24 P1.2 23 VDD_Micro 22 P1.1 21 P1.0

CYRF69303
20 NC 19 RESV 18 NC 17 NC 16 VCC 15 P2.0 14 NC 13 RFN 12 GND 11 RFP

Table Pin Definitions
Ordering Information

Package 40-pin Pb-free Punch-QFN 6 x 6 mm 40-pin Pb-free Sawn-QFN 6 x 6 mm
Ordering Code Definitions CY RF 40 LF/T X C
Ordering Part Number CYRF69303-40LFXC CYRF69303-40LTXC

Temperature range Commercial X = Pb-free 40-pin QFN package F = Punch, T = Sawn Part number

Marketing code RF = Wireless radio frequency product line

Company ID CY = Cypress

CYRF69303

Page 62 of 66

CYRF69303

Package Handling

Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may degrade device reliability.

Table Package Handling

Parameter TBAKETEMP tBAKETIME

Description Bake Temperature Bake Time

Min see package label

Unit
see package label °C
hours

Package Diagram

Figure 40-Pin Pb-free Punch-QFN 6 x 6 mm

SOLDERABLE EXPOSED PAD
001-12917 *C

Page 63 of 66

Figure 40-Pin Pb-free Sawn-QFN 6 x 6 mm

CYRF69303
001-44328 *F

Page 64 of 66

CYRF69303

Acronyms

Table Acronyms Used in this Document

Acronym ACK BER BOM CMOS CRC FEC FER GFSK HBM ISM IRQ MCU NRZ PLL QFN RSSI RF Rx Tx

Description Acknowledge packet received, no errors Bit error rate Bill of materials complementary metal oxide semiconductor cyclic redundancy check forward error correction frame error rate Gaussian frequency-shift keying Human body model Industrial, scientific, and medical interrupt request microcontroller unit non return to zero phase-locked loop Quad flat no-leads received signal strength indication radio frequency receive transmit

Document Conventions

Units of Measure

Table Units of Measure

Symbol °C dB

Unit of Measure degree Celsius decibels
dBc dBm Hz
decibel relative to carrier decibel-milliwatt hertz

KB Kbit kHz MHz mA
1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microsecond microvolt microvolts root-mean-square microwatt milliampere
millisecond
millivolt
02/28/2012 Updated Ordering Information CYRF69303-40LTXC and Ordering Code
3532316

KKCN

Definitions.

Added Package Diagram

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks and Buffers Interface Lighting and Power Control

Memory Optical and Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 66 of 66

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Datasheet ID: CYRF69303-40LFXC 508223