CYV15G0403DXB-BGXC

CYV15G0403DXB-BGXC Datasheet


CYP15G0403DXB CYV15G0403DXB CYW15G0403DXB

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CYV15G0403DXB-BGXC CYV15G0403DXB-BGXC CYV15G0403DXB-BGXC (pdf)
Related Parts Information
CYP15G0403DXB-BGXC CYP15G0403DXB-BGXC CYP15G0403DXB-BGXC
CYP15G0403DXB-BGXI CYP15G0403DXB-BGXI CYP15G0403DXB-BGXI
CYV15G0403DXB-BGI CYV15G0403DXB-BGI CYV15G0403DXB-BGI
CYP15G0403DXB-BGI CYP15G0403DXB-BGI CYP15G0403DXB-BGI
CYP15G0403DXB-BGC CYP15G0403DXB-BGC CYP15G0403DXB-BGC
CYV15G0403DXB-BGC CYV15G0403DXB-BGC CYV15G0403DXB-BGC
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CYP15G0403DXB CYV15G0403DXB CYW15G0403DXB

Independent Clock Quad HOTLink II Transceiver
• Second-generation technology
• Compliant to multiple standards

ESCON, DVB-ASI, SMPTE-292M, SMPTE-259M, Fibre Channel and Gigabit Ethernet IEEE802.3z

CPRI compliant

CYW15G0403DXB compliant to OBSAI-RP3
8B/10B coded data or 10 bit uncoded data
• Quad channel transceiver operates from 195 to
1500 MBaud serial data rate CYW15G0403DXB operates from 195 to 1540 MBaud

Aggregate throughput of up to 12 Gbits/second
• Second-generation HOTLink technology
• Truly independent channels

Each channel can operate at a different signaling rate Each channel can transport a different type of data
• Selectable input/output clocking options
• Internal phase-locked loops PLLs with no external PLL components
• Dual differential PECL-compatible serial inputs per channel
• Internal DC-restoration
• Dual differential PECL-compatible serial outputs per channel Source matched for 50Ω transmission lines No external bias resistors required Signaling-rate controlled edge-rates
• MultiFrame Receive Framer provides alignment options Bit and byte alignment Comma or Full K28.5 detect Single or Multi-byte Framer for byte alignment Low-latency option
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test BIST for at-speed link testing
• Compatible with Fiber-optic modules Copper cables Circuit board traces
• Per-channel Link Quality Indicator

Analog signal detect

Digital signal detect
• Low-power 3W 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb-Free package option available
• BiCMOS technology

Functional Description

The CYP V 15G0403DXB[1] Independent Clock Quad HOTLink II Transceiver is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links like optical fiber, balanced, and unbalanced copper transmission lines. The signaling rate can be anywhere in the range of 195 to 1500 MBaud per serial link. Each channel operates independently with its own reference clock allowing different rates. Each transmit channel accepts parallel characters in an Input Register, encodes each character for transport, and then converts it to serial data. Each receive channel accepts serial data and converts it to parallel data, decodes the data into characters, and presents these characters to an Output Register. Figure 1 on page 2 illustrates typical connections between independent host systems and corresponding CYP V W 15G0403DXB chips The CYW15G0403DXB[1] operates from 195 to 1540 MBaud, which includes operation at the OBSAI RP3 datarate of both 1536 MBaud and 768 MBaud.

The CYV15G0403DXB satisfies the SMPTE-259M and SMPTE-292M compliance as per SMPTE EG34-1999 Pathological Test Requirements.

As a second-generation HOTLink device, the CYP V W 15G0403DXB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility data, command, and BIST with other HOTLink devices. The transmit TX section of the CYP V W 15G0403DXB Quad HOTLink II consists of four independent byte-wide channels. Each channel can accept either 8-bit data characters or preencoded 10-bit transmission characters. Data characters may be passed from the Transmit Input Register to an integrated 8B/10B Encoder to improve their serial transmission characteristics. These encoded characters are then serialized and output from dual Positive ECL PECL compatible differential transmission-line drivers at a bit-rate of either 10 or 20 times the input reference clock for that channel.

Note

CYV15G0403DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0403DXB refers to OBSAI RP3 compliant devices maximum operating data rate is 1540 MBaud . CYP15G0403DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and also OBSAI RP3 operating datarate of 1536 MBaud. CYP V W 15G0403DXB refers to all three devices.
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
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System Host

System Host

Figure HOTLink II System Connections

Serial Links

Independent CYP V W 15G0403DXB

Serial Links

Serial Links Backplane or

Cabled Connections Serial Links

Independent CYP V W 15G0403DXB

The receive RX section of the CYP V W 15G0403DXB Quad HOTLink II consists of four independent byte-wide channels. Each channel accepts a serial bit-stream from one of two PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. Each recovered bit-stream is deserialized and framed into characters, 8B/10B decoded, and checked for transmission errors. Recovered decoded characters are then written to an internal Elasticity Buffer, and presented to the destination host system.

The integrated 8B/10B encoder/decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface.

The parallel I/O interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. In addition to clocking the transmit path with a local reference clock, the receive interface may also be configured to present data relative to a recovered clock or to a local reference clock.

Each transmit and receive channel contains an independent BIST pattern generator and checker. This BIST hardware allows at-speed testing of the high-speed serial data paths in each transmit and receive section, and across the interconnecting links.

The CYP V W 15G0403DXB is ideal for port applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-protocol routers, aggregation equipment, and switches.
The following information describes how the tables are used for both generating valid Transmission Characters encoding and checking the validity of received Transmission Characters decoding . It also specifies the ordering rules followed when transmitting the bits within a character and the characters within any higher-level constructs specified by a standard.

Transmission Order

Within the definition of the 8B/10B Transmission Code, the bit positions of the Transmission Characters are labeled a, b, c, d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order.

Note that bit i is transmitted between bit e and bit f, rather than in alphabetical order.

Valid and Invalid Transmission Characters

The following tables define the valid Data Characters and valid Special Characters K characters , respectively. The tables are used for both generating valid Transmission Characters and checking the validity of received Transmission Characters. In the tables, each Valid-Data-byte or Special-Character-code entry has two columns that represent two Transmission Characters. The two columns correspond to the current value of the running disparity. Running disparity is a binary parameter with either a negative or positive + value.

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After powering on, the Transmitter may assume either a positive or negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter selects the proper version of the Transmission Character based on the current running disparity value, and the Transmitter calculates a new value for its running disparity based on the contents of the transmitted character. Special Character codes C1.7 and C2.7 can be used to force the transmission of a specific Special Character with a specific running disparity as required for some special sequences in X3.230.

After powering on, the Receiver may assume either a positive or negative value for its initial running disparity. Upon reception of any Transmission Character, the Receiver decides whether the Transmission Character is valid or invalid according to the following rules and tables and calculates a new value for its Running Disparity based on the contents of the received character.

The following rules for running disparity are used to calculate the new running-disparity value for Transmission Characters that have been transmitted and received.

Running disparity for a Transmission Character is calculated from sub-blocks, where the first six bits abcdei form one sub-block and the second four bits fghj form the other sub-block. Running disparity at the beginning of the 6-bit sub-block is the running disparity at the end of the previous Transmission Character. Running disparity at the beginning of the 4-bit sub-block is the running disparity at the end of the 6-bit sub-block. Running disparity at the end of the Transmission Character is the running disparity at the end of the 4-bit sub-block.

Running disparity for the sub-blocks is calculated as follows:

Running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. It is also positive at the end of the 6-bit sub-block if the 6-bit sub-block is 000111, and it is positive at the end of the 4-bit sub-block if the 4-bit sub-block is

Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. It is also negative at the end of the 6-bit sub-block if the 6-bit sub-block is 111000, and it is negative at the end of the 4-bit sub-block if the 4-bit sub-block is

Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block.

Use of the Tables for Generating Transmission Characters

The appropriate entry in Table 15 for the Valid Data byte or Table 16 for Special Character byte identify which Transmission Character is generated. The current value of the Transmitter’s running disparity is used to select the Transmission Character from its corresponding column. For each

Transmission Character transmitted, a new value of the running disparity is calculated. This new value is used as the Transmitter’s current running disparity for the next Valid Data byte or Special Character byte encoded and transmitted. Table 13 shows naming notations and examples of valid transmission characters.

Use of the Tables for Checking the Validity of Received Transmission Characters

The column corresponding to the current value of the Receiver’s running disparity is searched for the received Transmission Character. If the received Transmission Character is found in the proper column, then the Transmission Character is valid and the associated Data byte or Special Character code is determined decoded . If the received Transmission Character is not found in that column, then the Transmission Character is invalid. This is called a code violation. Independent of the Transmission Character’s validity, the received Transmission Character is used to calculate a new value of running disparity. The new value is used as the Receiver’s current running disparity for the next received Transmission Character.

Table 13.Valid Transmission Characters

Byte Name

Data DIN or QOUT 765 43210

D0.0

Hex Value 00

D1.0
000 00001

D2.0
000 00010

D5.2
010 00101

D30.7
111 11110

D31.7

Detection of a code violation does not necessarily show that the Transmission Character in which the code violation was detected is in error. Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the Transmission Character in which the error occurred. Table 14 shows an example of this behavior.

Table 14.Code Violations Resulting from Prior Errors

Character

Character

Character
Ordering Information

Speed

Standard OBSAI Standard OBSAI
Ordering Code

CYP15G0403DXB-BGC CYP15G0403DXB-BGI CYV15G0403DXB-BGC CYV15G0403DXB-BGI CYW15G0403DXB-BGC CYW15G0403DXB-BGI CYP15G0403DXB-BGXC CYP15G0403DXB-BGXI CYV15G0403DXB-BGXC CYV15G0403DXB-BGXI CYW15G0403DXB-BGXC CYW15G0403DXB-BGXI

Package Name BL256

Package Type
256-Ball Thermally Enhanced Ball Grid Array 256-Ball Thermally Enhanced Ball Grid Array 256-Ball Thermally Enhanced Ball Grid Array 256-Ball Thermally Enhanced Ball Grid Array 256-Ball Thermally Enhanced Ball Grid Array 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array

Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial

Package Diagram

Figure 256-Lead L2 Ball Grid Array 27 x 27 x mm BL256

A1 CORNER I.D.

TOP VIEW

REF.
0.20 4X A

BOTTOM VIEW BALL SIDE
Ø0.75±0.15 256X
20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1

R Max 4X

MIN.

A1 CORNER I.D.

SIDE VIEW
26°

TYP.

SEATING PLANE

MIN TOP OF MOLD COMPOUND TO TOP OF BALLS

SECTION A-A
51-85123-*E

HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks of Cypress Semiconductor. CPRI is a trademark of Siemens AG. IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines. All product and company names mentioned in this document may be the trademarks of their respective holders.

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Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page

Document Title CYP V W 15G0403DXB Independent Clock Quad HOTLink II Transceiver Document Number 38-02065

ECN NO.

ISSUE DATE

ORIG. OF CHANGE

DESCRIPTION OF CHANGE
118422
09/24/02

New Data Sheet
125289 04/04/03

Redefined device
More datasheets: CY22M1LCALGXC-00 | CY22M1LCALGXI-00 | CY22M1SCALGXC-00 | PT2559B-F | NFS110-7902PJ | NFS110-7915J | NFS110-7912J | NFS110-7924J | CYP15G0403DXB-BGXC | CYP15G0403DXB-BGXI


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Datasheet ID: CYV15G0403DXB-BGXC 508214