CYW15G0401DXB-BGXC

CYW15G0401DXB-BGXC Datasheet

CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB

Part	Datasheet
CYW15G0401DXB-BGXC	CYW15G0401DXB-BGXC (pdf)

Related Parts	Information
CYP15G0401DXB-BGI	CYP15G0401DXB-BGI
CYP15G0401DXB-BGC	CYP15G0401DXB-BGC

PDF Datasheet Preview
CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Quad HOTLink II Transceiver • Second-generation technology • Compliant to multiple standards ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet IEEE802.3z CPRI compliant CYW15G0401DXB compliant to OBSAI-RP3 CYV15G0401DXB compliant to SMPTE 259M and SMPTE 292M 8B/10B encoded or 10-bit unencoded data • Quad channel transceiver operates from 195 to 1500 MBaud serial data rate CYW15G0401DXB operates from 195 to 1540 MBaud Aggregate throughput of 12 GBits/second • Selectable parity check/generate • Selectable multi-channel bonding options Four 8-bit channels Two 16-bit channels One 32-bit channel N x 32-bit channel support inter-chip • Skew alignment support for multiple bytes of offset • Selectable input/output clocking options • MultiFrame Receive Framer Bit and Byte alignment Comma or full K28.5 detect Single- or multi-byte framer for byte alignment Low-latency option • Synchronous LVTTL parallel interface • Optional Elasticity Buffer in Receive Path • Optional Phase Align Buffer in Transmit Path • Internal phase-locked loops PLLs with no external PLL components • Dual differential PECL-compatible serial inputs per channel Internal DC-restoration • Dual differential PECL-compatible serial outputs per channel Source matched for transmission lines No external bias resistors required Signaling-rate controlled edge-rates • Compatible with fiber-optic modules copper cables circuit board traces • JTAG boundary scan • Built-In Self-Test BIST for at-speed link testing • Per-channel Link Quality Indicator Analog signal detect Digital signal detect • Low power 2.5W 3.3V typical • Single 3.3V supply • 256-ball thermally enhanced BGA • Pb-free package option available • BiCMOS technology Functional Description The CYP V 15G0401DXB[1] Quad HOTLink II Transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links optical fiber, balanced, and unbalanced copper transmission lines at signaling speeds ranging from 195-to-1500 MBaud per serial link. Serial Links System Host CYP V W 15G0401DXB CYP V W 15G0401DXB System Host Serial Links Serial Links Serial Links Backplane or Cabled Connections Figure HOTLink II System Connections Note: CYV15G0401DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0401DXB refers to OBSAI RP3 compliant devices maximum operating data rate is 1540 MBaud . CYP15G0401DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and also OBSAI RP3 operating datarate of 1536 MBaud. CYP V W 15G0401DXB refers to all three devices. Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB The following information describes how the tables are used for both generating valid Transmission Characters encoding and checking the validity of received Transmission Characters decoding . It also specifies the ordering rules to be followed when transmitting the bits within a character and the characters within any higher-level constructs specified by a standard. Transmission Order Within the definition of the 8B/10B Transmission Code, the bit positions of the Transmission Characters are labeled a, b, c, d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order. Note that bit i is transmitted between bit e and bit f, rather than in alphabetical order. Valid and Invalid Transmission Characters The following tables define the valid Data Characters and valid Special Characters K characters , respectively. The tables are used for both generating valid Transmission Characters and checking the validity of received Transmission Characters. In the tables, each Valid-Data-byte or Special-Character-code entry has two columns that represent two Transmission Characters. The two columns correspond to the current value of the running disparity. Running disparity is a binary parameter with either a negative or positive + value. After powering on, the Transmitter may assume either a positive or negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter will select the proper version of the Transmission Character based on the current running disparity value, and the Trans- Page 44 of 53 CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB mitter calculates a new value for its running disparity based on the contents of the transmitted character. Special Character codes C1.7 and C2.7 can be used to force the transmission of a specific Special Character with a specific running disparity as required for some special sequences in X3.230. After powering on, the Receiver may assume either a positive or negative value for its initial running disparity. Upon reception of any Transmission Character, the Receiver decides whether the Transmission Character is valid or invalid according to the following rules and tables and calculates a new value for its Running Disparity based on the contents of the received character. The following rules for running disparity are used to calculate the new running-disparity value for Transmission Characters that have been transmitted and received. Running disparity for a Transmission Character is calculated from sub-blocks, where the first six bits abcdei form one sub-block and the second four bits fghj form the other sub-block. Running disparity at the beginning of the six-bit sub-block is the running disparity at the end of the previous Transmission Character. Running disparity at the beginning of the four-bit sub-block is the running disparity at the end of the six-bit sub-block. Running disparity at the end of the Transmission Character is the running disparity at the end of the four-bit sub-block. Running disparity for the sub-blocks is calculated as follows: Running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. It is also positive at the end of the six-bit sub-block if the six-bit sub-block is 000111, and it is positive at the end of the four-bit sub-block if the four-bit sub-block is Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. It is also negative at the end of the six-bit sub-block if the six-bit sub-block is 111000, and it is negative at the end of the six-bit sub-block if the four-bit sub-block is Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block. Use of the Tables for Generating Transmission Characters The appropriate entry in Table 28 for the Valid Data byte or Table 29 for Special Character byte identify which Transmission Character is to be generated. The current value of the Transmitter’s running disparity is used to select the Transmission Character from its corresponding column. For each Transmission Character transmitted, a new value of the running disparity is calculated. This new value is used as the Transmitter’s current running disparity for the next Valid Data byte or Special Character byte to be encoded and transmitted. Table 26 shows naming notations and examples of valid transmission characters. Use of the Tables for Checking the Validity of Received Transmission Characters The column corresponding to the current value of the Receiver’s running disparity is searched for the received Transmission Character. If the received Transmission Character is found in the proper column, then the Transmission Character is valid and the associated Data byte or Special Character code is determined decoded . If the received Transmission Character is not found in that column, then the Transmission Character is invalid. This is called a code violation. Independent of the Transmission Character’s validity, the received Transmission Character is used to calculate a new value of running disparity. The new value is used as the Receiver’s current running disparity for the next received Transmission Character. Table Valid Transmission Characters Byte Name Data DIN or QOUT 765 43210 Hex Value D0.0 D1.0 000 00001 D2.0 000 00010 D5.2 010 00101 D30.7 111 11110 D31.7 Detection of a code violation does not necessarily show that the Transmission Character in which the code violation was detected is in error. Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the Transmission Character in which the error occurred. Table 27 shows an example of this behavior. Table Code Violations Resulting from Prior Errors Character Character Character Ordering Information Speed Standard OBSAI Standard OBSAI Ordering Code CYP15G0401DXB-BGC CYP15G0401DXB-BGI CYV15G0401DXB-BGC CYV15G0401DXB-BGI CYW15G0401DXB-BGC CYW15G0401DXB-BGI CYP15G0401DXB-BGXC CYP15G0401DXB-BGXI CYV15G0401DXB-BGXC CYV15G0401DXB-BGXI CYW15G0401DXB-BGXC CYW15G0401DXB-BGXI Package Name BL256 Package Type 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Package Diagram Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 256-Lead L2 Ball Grid Array 27 x 27 x mm BL256 A1 CORNER I.D. TOP VIEW REF. 0.20 4X A BOTTOM VIEW BALL SIDE Ø0.75±0.15 256X 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 R Max 4X MIN. A1 CORNER I.D. SIDE VIEW 26° TYP. SEATING PLANE MIN TOP OF MOLD COMPOUND TO TOP OF BALLS 51-85123-E HOTLink is a registered trademark, and HOTLink II, and MultiFrame are trademarks, of Cypress Semiconductor. CPRI is a trademark of Siemens AG. IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines. All product and company names mentioned in this document are the trademarks of their respective holders. Page 51 of 53 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB Document History Page Document Title CYP V W 15G0401DXB Quad HOTLink II Transceiver Document Number 38-02002 Issue Date Orig. of Change Description of Change * 105840 03/21/01 SZV Change from Spec number 38-00876 to 38-02002 A 108025 06/20/01 AMV Changed Marketing part number B 108437 07/19/01 TME Change Marketing part number from CYP15G0401DX to CYP15G0401 *C 112986 11/12/01 TPS Changed common mode input information and duty cycle of transmit clocks Updated max voltage power and release under ecn control Changed the wording of REFCLK input coupling on both inputs for LVTTL clock input Addition of TXCLKO+ and the TXCLKO+ specs Changed the TXCLKO clock output to refect the new timing Changed the Half Clock drawing so that the viald time was at clock edges Changed the input power Changed the spec for the serial output levels at the different terminations Changed the common mode input range of the serial input Increased the Serial input current under the conditions of VCC and min Added to the Duty cycle of the transmit and receiver clock signals The rise time of the serial inputs and receiver were changed The half rate timing drawing changed from not valid at clock edges to viald at clock edges Added new timing line for status valid time of half clock signals Max voltage reduced from 4.2V to 3.8V Matched the common specs with the family of parts 2/26/02 TPS Changed many names from lower case to upper case

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CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB

Quad HOTLink II Transceiver
• Second-generation technology
• Compliant to multiple standards

ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet IEEE802.3z

CPRI compliant

CYW15G0401DXB compliant to OBSAI-RP3 CYV15G0401DXB compliant to SMPTE 259M and

SMPTE 292M 8B/10B encoded or 10-bit unencoded data
• Quad channel transceiver operates from 195 to 1500 MBaud serial data rate CYW15G0401DXB operates from 195 to 1540 MBaud

Aggregate throughput of 12 GBits/second
• Selectable parity check/generate
• Selectable multi-channel bonding options

Four 8-bit channels

Two 16-bit channels

One 32-bit channel

N x 32-bit channel support inter-chip
• Skew alignment support for multiple bytes of offset
• Selectable input/output clocking options
• MultiFrame Receive Framer

Bit and Byte alignment

Comma or full K28.5 detect

Single- or multi-byte framer for byte alignment

Low-latency option
• Synchronous LVTTL parallel interface
• Optional Elasticity Buffer in Receive Path
• Optional Phase Align Buffer in Transmit Path
• Internal phase-locked loops PLLs with no external PLL components
• Dual differential PECL-compatible serial inputs per channel Internal DC-restoration
• Dual differential PECL-compatible serial outputs per channel Source matched for transmission lines

No external bias resistors required

Signaling-rate controlled edge-rates
• Compatible with
fiber-optic modules
copper cables
circuit board traces
• JTAG boundary scan
• Built-In Self-Test BIST for at-speed link testing
• Per-channel Link Quality Indicator

Analog signal detect

Digital signal detect
• Low power 2.5W 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb-free package option available
• BiCMOS technology

Functional Description

The CYP V 15G0401DXB[1] Quad HOTLink II Transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links optical fiber, balanced, and unbalanced copper transmission lines at signaling speeds ranging from 195-to-1500 MBaud per serial link.

Serial Links

System Host

CYP V W 15G0401DXB CYP V W 15G0401DXB

System Host

Serial Links

Serial Links

Serial Links Backplane or

Cabled Connections

Figure HOTLink II System Connections

Note:

CYV15G0401DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0401DXB refers to OBSAI RP3 compliant devices maximum operating data rate is 1540 MBaud . CYP15G0401DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and also OBSAI RP3 operating datarate of 1536 MBaud. CYP V W 15G0401DXB refers to all three devices.

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB
The following information describes how the tables are used for both generating valid Transmission Characters encoding and checking the validity of received Transmission Characters decoding . It also specifies the ordering rules to be followed when transmitting the bits within a character and the characters within any higher-level constructs specified by a standard.

Transmission Order

Within the definition of the 8B/10B Transmission Code, the bit positions of the Transmission Characters are labeled a, b, c, d, e, i, f, g, h, j. Bit “a” is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order.

Note that bit i is transmitted between bit e and bit f, rather than in alphabetical order.

Valid and Invalid Transmission Characters

The following tables define the valid Data Characters and valid Special Characters K characters , respectively. The tables are used for both generating valid Transmission Characters and checking the validity of received Transmission Characters. In the tables, each Valid-Data-byte or Special-Character-code entry has two columns that represent two Transmission Characters. The two columns correspond to the current value of the running disparity. Running disparity is a binary parameter with either a negative or positive + value.

After powering on, the Transmitter may assume either a positive or negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter will select the proper version of the Transmission Character based on the current running disparity value, and the Trans-

Page 44 of 53

CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB
mitter calculates a new value for its running disparity based on the contents of the transmitted character. Special Character codes C1.7 and C2.7 can be used to force the transmission of a specific Special Character with a specific running disparity as required for some special sequences in X3.230.

After powering on, the Receiver may assume either a positive or negative value for its initial running disparity. Upon reception of any Transmission Character, the Receiver decides whether the Transmission Character is valid or invalid according to the following rules and tables and calculates a new value for its Running Disparity based on the contents of the received character.

The following rules for running disparity are used to calculate the new running-disparity value for Transmission Characters that have been transmitted and received.

Running disparity for a Transmission Character is calculated from sub-blocks, where the first six bits abcdei form one sub-block and the second four bits fghj form the other sub-block. Running disparity at the beginning of the six-bit sub-block is the running disparity at the end of the previous Transmission Character. Running disparity at the beginning of the four-bit sub-block is the running disparity at the end of the six-bit sub-block. Running disparity at the end of the Transmission Character is the running disparity at the end of the four-bit sub-block.

Running disparity for the sub-blocks is calculated as follows:

Running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. It is also positive at the end of the six-bit sub-block if the six-bit sub-block is 000111, and it is positive at the end of the four-bit sub-block if the four-bit sub-block is

Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. It is also negative at the end of the six-bit sub-block if the six-bit sub-block is 111000, and it is negative at the end of the six-bit sub-block if the four-bit sub-block is

Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block.

Use of the Tables for Generating Transmission Characters

The appropriate entry in Table 28 for the Valid Data byte or Table 29 for Special Character byte identify which Transmission Character is to be generated. The current value of the Transmitter’s running disparity is used to select the Transmission Character from its corresponding column. For each Transmission Character transmitted, a new value of the running disparity is calculated. This new value is used as the Transmitter’s current running disparity for the next Valid Data
byte or Special Character byte to be encoded and transmitted. Table 26 shows naming notations and examples of valid transmission characters.

Use of the Tables for Checking the Validity of Received Transmission Characters

The column corresponding to the current value of the Receiver’s running disparity is searched for the received Transmission Character. If the received Transmission Character is found in the proper column, then the Transmission Character is valid and the associated Data byte or Special Character code is determined decoded . If the received Transmission Character is not found in that column, then the Transmission Character is invalid. This is called a code violation. Independent of the Transmission Character’s validity, the received Transmission Character is used to calculate a new value of running disparity. The new value is used as the Receiver’s current running disparity for the next received Transmission Character.

Table Valid Transmission Characters

Byte Name

Data DIN or QOUT 765 43210

Hex Value

D0.0

D1.0
000 00001

D2.0
000 00010

D5.2
010 00101

D30.7
111 11110

D31.7

Detection of a code violation does not necessarily show that the Transmission Character in which the code violation was detected is in error. Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the Transmission Character in which the error occurred. Table 27 shows an example of this behavior.

Table Code Violations Resulting from Prior Errors

Character

Character

Character
Ordering Information

Speed Standard OBSAI Standard OBSAI
Ordering Code CYP15G0401DXB-BGC CYP15G0401DXB-BGI CYV15G0401DXB-BGC CYV15G0401DXB-BGI CYW15G0401DXB-BGC CYW15G0401DXB-BGI CYP15G0401DXB-BGXC CYP15G0401DXB-BGXI CYV15G0401DXB-BGXC CYV15G0401DXB-BGXI CYW15G0401DXB-BGXC CYW15G0401DXB-BGXI

Package Name BL256

Package Type 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array Pb-free 256-ball Thermally Enhanced Ball Grid Array

Package Diagram

Operating Range

Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
256-Lead L2 Ball Grid Array 27 x 27 x mm BL256

A1 CORNER I.D.

TOP VIEW

REF.
0.20 4X A

BOTTOM VIEW BALL SIDE
Ø0.75±0.15 256X
20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1

R Max 4X

MIN.

A1 CORNER I.D.

SIDE VIEW
26°

TYP.

SEATING PLANE

MIN TOP OF MOLD COMPOUND TO TOP OF BALLS
51-85123-*E

HOTLink is a registered trademark, and HOTLink II, and MultiFrame are trademarks, of Cypress Semiconductor. CPRI is a trademark of Siemens AG. IBM and ESCON are registered trademarks, and FICON is a trademark, of International Business Machines. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 51 of 53

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CYP15G0401DXB CYV15G0401DXB CYW15G0401DXB

Document History Page

Document Title CYP V W 15G0401DXB Quad HOTLink II Transceiver Document Number 38-02002

Issue Date

Orig. of Change

Description of Change
** 105840 03/21/01

SZV Change from Spec number 38-00876 to 38-02002
*A 108025 06/20/01 AMV Changed Marketing part number
*B 108437 07/19/01

TME Change Marketing part number from CYP15G0401DX to CYP15G0401
*C 112986 11/12/01

TPS Changed common mode input information and duty cycle of transmit clocks Updated max voltage power and release under ecn control Changed the wording of REFCLK input coupling on both inputs for LVTTL clock input Addition of TXCLKO+ and the TXCLKO+ specs Changed the TXCLKO clock output to refect the new timing Changed the Half Clock drawing so that the viald time was at clock edges Changed the input power Changed the spec for the serial output levels at the different terminations Changed the common mode input range of the serial input Increased the Serial input current under the conditions of VCC and min Added to the Duty cycle of the transmit and receiver clock signals The rise time of the serial inputs and receiver were changed The half rate timing drawing changed from not valid at clock edges to viald at clock edges Added new timing line for status valid time of half clock signals Max voltage reduced from 4.2V to 3.8V Matched the common specs with the family of parts
2/26/02

TPS Changed many names from lower case to upper case

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Datasheet ID: CYW15G0401DXB-BGXC 508213