CYD36S18V18-200BGXC

CYD36S18V18-200BGXC Datasheet

CYDXXS72V18 CYDXXS36V18 CYDXXS18V18

Part	Datasheet
CYD36S18V18-200BGXC	CYD36S18V18-200BGXC (pdf)

Related Parts	Information
CYD09S36V18-200BBXC	CYD09S36V18-200BBXC
CYD09S18V18-200BBXC	CYD09S18V18-200BBXC
CYD36S18V18-167BGXC	CYD36S18V18-167BGXC
CYD36S36V18-167BGXC	CYD36S36V18-167BGXC
CYD36S36V18-200BGXC	CYD36S36V18-200BGXC

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CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM • True dual port memory enables simultaneous access the shared array from each port • Synchronous pipelined operation with single data rate SDR operation on each port SDR interface at 200 MHz Up to Gb/s bandwidth 200 MHz x 72-bit x 2 ports • Selectable pipelined or flow-through mode • V or V core power supply • Commercial and Industrial temperature • IEEE JTAG boundary scan • Available in 484-ball PBGA x 72 and 256-ball FBGA x 36 and x 18 packages • FullFlex72 family 36-Mbit 512 K x 72 CYD36S72V18 18-Mbit 256 K x 72 CYD18S72V18 9-Mbit 128 K x 72 CYD09S72V18 • FullFlex36 family 36-Mbit 1 M x 36 CYD36S36V18 18-Mbit 512 K x 36 CYD18S36V18 9-Mbit 256 K x 36 CYD09S36V18 2-Mbit 64 K x 36 CYD02S36V18 • FullFlex18 family 36-Mbit 2 M x 18 CYD36S18V18 18-Mbit 1 M x 18 CYD18S18V18 9-Mbit 512 K x 18 CYD09S18V18 • Built in deterministic access control to manage address collisions Deterministic flag output upon collision detection Collision detection on back-to-back clock cycles First busy address readback • Advanced features for improved high speed data transfer and flexibility Variable impedance matching VIM Echo clocks Selectable LVTTL V , Extended HSTL V to V , V LVCMOS, or V LVCMOS IO on each port Burst counters for sequential memory access Mailbox with interrupt flags for message passing Dual chip enables for easy depth expansion Functional Description The FullFlex dual port SRAM families consist of 2-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power V or V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode. The advanced features include the following: • Built in deterministic access control to manage address collisions during simultaneous access to the same memory location • Variable impedance matching VIM to improve data transmission by matching the output driver impedance to the line impedance • Echo clocks to improve data transfer To reduce the static power consumption, chip enables power down the internal circuitry. The number of latency cycles before a change in CE0 or CE1 enables or disables the databus matches the number of cycles of read latency selected for the device. For a valid write or read to occur, activate both chip enable inputs on a port. Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally. Additional device features include a mask register and a mirror register to control counter increments and wrap around. The counter interrupt CNTINT flags notify the host that the counter reaches maximum count value on the next clock cycle. The host reads the burst counter internal address, mask register address, and busy address on the address lines. The host also loads the counter with the address stored in the mirror register by using the retransmit functionality. Mailbox interrupt flags are used for message passing, and JTAG boundary scan and asynchronous Master Reset MRST are also available. The Logic Block Diagram on page 2 shows these features. The FullFlex72 is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 are available in 256-ball fine pitch BGA package except the 36-Mbit devices which are offered in 484-ball plastic BGA package. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Logic Block Diagram The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows [1, 2, 3] FTSELL CQENL PORTSTD[1:0]L CONFIG Block CONFIG Block DQ[71:0]L BE [7:0]L CE0L CE1L OEL R/WL CQ1L CQ0L IO Control IO Control Dual Port Array FTSELR CQENR PORTSTD[1:0]R DQ [71:0]R BE [7:0]R Switching Characteristics 26 Switching Waveforms 29 Ordering Information 43 512 K x 72 36-Mbit V/1.5 V Synchronous CYD36S72V18 Dual Port SRAM 43 256 K x 72 18-Mbit V/1.5 V Synchronous CYD18S72V18 Dual Port SRAM 43 128 K x 72 9-Mbit V/1.5 V Synchronous CYD09S72V18 Dual Port SRAM 43 1024 K x 36-Mbit V/1.5 V Synchronous CYD36S36V18 Dual Port SRAM 43 512 K x 36 18-Mbit V/1.5 V Synchronous CYD18S36V18 Dual Port SRAM 43 256 K x 36 9-Mbit V/1.5 V Synchronous CYD09S36V18 Dual Port SRAM 44 64 K x 36 2-Mbit V or V Synchronous CYD02S36V18 Dual Port SRAM 44 2048 K x 18 36-Mbit V/1.5 V Synchronous CYD36S18V18 Dual Port SRAM 45 1024 K x 18-Mbit V/1.5 V Synchronous CYD18S18V18 Dual Port SRAM 45 512 K x 18 9-Mbit V/1.5 V Synchronous CYD09S18V18 Dual Port SRAM 45 Ordering Code Definitions 45 Package Diagrams 46 Acronyms 49 Document Conventions 49 Units of Measure 49 Document History Page 50 Sales, Solutions, and Legal Information 53 Worldwide Sales and Design Support 53 Products 53 PSoC Solutions 53 Page 3 of 53 [+] Feedback CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Figure FullFlex72 SDR 484-ball BGA Pinout Top View 11 12 21 22 A DNU DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ51R DQ54R DQ57R DQ59R DQ61R DNU B DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R C DQ65L DQ64L VSS D DQ67L DQ66L VSS DQ56L DQ53L DQ50L DQ47L DQ44L DQ41L DQ38L DQ38R DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R VSS CQ1L VSS LOWSPDL PORTSTD0L ZQ0L[4] BUSYL CNTINTL PORTSTD1L DNU CQ1R VSS DQ64R DQ65R DQ66R DQ67R E DQ69L DQ68L VDDIOL VSS VDDIOL VTTL VDDIOR DNU VSS VDDIOR DQ68R DQ69R F DQ71L DQ70L CE1L CE0L VDDIOL VCORE VDDIOR CE0R CE1R DQ70R DQ71R G A0L A1L RETL BE4L VDDIOL VREFL VSS VSS VREFR VDDIOR BE4R RETR A1R A0R H A2L A3L WRPL BE5L VDDIOL VSS VSS VDDIOR BE5R WRPR A3R A2R J A4L K A6L A5L READYL BE6L VDDIOL VSS A7L ZQ1L[4, 5] BE7L VTTL VCORE VSS VSS VDDIOR BE6R READYR A5R A4R VSS VCORE VDDIOR BE7R ZQ1R[4, 5] A7R A6R L A8L A9L OEL VTTL VCORE VSS VSS VCORE VTTL OER A9R A8R M A10L A11L VSS BE3L VTTL VCORE VSS VSS VCORE VTTL BE3R VSS A11R A10R N A12L A13L ADSL BE2L VDDIOL VCORE VSS VSS VCORE VTTL BE2R ADSR A13R A12R P A14L A15L CNT/MSKL BE1L VDDIOL VSS R A16L[8] A17L[7] CNTENL BE0L VDDIOL VSS T A18L[6] DNU CNTRSTL INTL VDDIOL VREFL VSS VDDIOR BE1R CNT/MSKR A15R A14R VSS VDDIOR BE0R CNTENR A17R[7] A16R[8] VREFR VDDIOR INTR CNTRSTR DNU A18R[6] U DQ35L DQ34L R/WL CQENL VDDIOL VCORE VDDIOR CQENR R/WR DQ34R DQ35R V DQ33L DQ32L FTSELL VDDIOL W DQ31L DQ30L VSS MRST DNU VSS VDDIOL VTTL VDDIOR TRST VDDIOR FTSELR DQ32R DQ33R CQ0L DNU PORTSTD1R CNTINTR BUSYR ZQ0R[4] PORTSTD0R LOWSPDR VSS CQ0R VSS TDO DQ30R DQ31R Y DQ29L DQ28L VSS DQ20L DQ17L DQ14L DQ11L DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11R DQ14R DQ17R DQ20R TMS TCK DQ28R DQ29R AA DQ27L DQ26L DQ24L DQ22L DQ19L DQ16L DQ13L DQ10L DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10R DQ13R DQ16R DQ19R DQ22R DQ24R DQ26R DQ27R AB DNU DQ25L DQ23L DQ21L DQ18L DQ15L DQ12L DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12R DQ15R DQ18R DQ21R DQ23R DQ25R DNU Ordering Information 512 K x 72 36-Mbit V/1.5 V Synchronous CYD36S72V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD36S72V18-200BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial 167 CYD36S72V18-167BGXI 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Industrial 256 K x 72 18-Mbit V/1.5 V Synchronous CYD18S72V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD18S72V18-200BGXI 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Industrial 200 CYD18S72V18-200BGI 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Industrial 167 CYD18S72V18-167BGXC 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Commercial 167 CYD18S72V18-167BGC 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Commercial 167 CYD18S72V18-167BGI 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Industrial 128 K x 72 9-Mbit V/1.5 V Synchronous CYD09S72V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD09S72V18-200BGXI 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Industrial 167 CYD09S72V18-167BBXC 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Commercial 1024 K x 36-Mbit V/1.5 V Synchronous CYD36S36V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD36S36V18-200BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial 167 CYD36S36V18-167BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial 167 CYD36S36V18-167BGXI 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Industrial 512 K x 36 18-Mbit V/1.5 V Synchronous CYD18S36V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD18S36V18-200BBAXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial 167 CYD18S36V18-167BBAI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Industrial Page 43 of 53 [+] Feedback CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Ordering Information continued 256 K x 36 9-Mbit V/1.5 V Synchronous CYD09S36V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD09S36V18-200BBXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial 200 CYD09S36V18-200BBXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial 167 CYD09S36V18-167BBXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial 64 K x 36 2-Mbit V or V Synchronous CYD02S36V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type 200 CYD02S36V18-200BBC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Operating Range Commercial Page 44 of 53 [+] Feedback CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Ordering Information continued 2048 K x 18 36-Mbit V/1.5 V Synchronous CYD36S18V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD36S18V18-200BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial 167 CYD36S18V18-167BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial 167 CYD36S18V18-167BGXI 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Industrial 1024 K x 18-Mbit V/1.5 V Synchronous CYD18S18V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD18S18V18-200BBAXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial 200 CYD18S18V18-200BBAXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial 167 CYD18S18V18-167BBAXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial 512 K x 18 9-Mbit V/1.5 V Synchronous CYD09S18V18 Dual Port SRAM Speed MHz Ordering Code Package Diagram Package Type Operating Range 200 CYD09S18V18-200BBXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial 200 CYD09S18V18-200BBXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial 167 CYD09S18V18-167BBXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial Ordering Code Definitions CY DXX SXX V18 - XXX X Temperature Range X = C or I C = Commercial I = Industrial Pb-free Package Type XXX = BG or BB or BBA BG, BB, BBA = Ball Grid Array Speed Grade XXX = 167 MHz or 200 MHz V18 = V SXX = Data Width DXX = Density in Mb CY = Cypress Page 45 of 53 [+] Feedback CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Package Diagrams Figure 256-ball FBGA 17 x 17 x mm BB256/BW0BD Package Outline, 51-85108 51-85108 I Page 46 of 53 [+] Feedback CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Package Diagrams continued Figure 484-ball PBGA 23 x 23 x mm BY484 Package Outline, 51-85218 51-85218 A Page 47 of 53 [+] Feedback CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Package Diagrams continued Figure 484-ball PBGA 27 x 27 x mm BY484S Package Outline, 001-07825 001-07825 *A Page 48 of 53 [+] Feedback Acronyms Acronym ball grid array CMOS complementary metal oxide semiconductor delay lock loop FBGA fine pitch ball gird array HSTL high speed transceiver logic input/output single data rate SRAM static random access memory test clock test data-in test data-out test mode select variable impedance matching CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Document Conventions Units of Measure Symbol °C MHz µA mA ms mV ns pF V W Unit of Measure degree Celsius megahertz microampere milliampere millisecond millivolt nanosecond picofarad volt watt YDT Changed ordering information with Pb-free part numbers Removed VC_SEL Added IO and core voltage adders Removed references to bin drop for LVTTL/2.5 V LVCMOS and V core modes Updated Cin and Cout Updated ICC, ISB1, ISB2 and ISB3 tables Updated busy address read back timing diagram Added HTSL input waveform Removed HSTL AC from DC tables Added 484-ball 27 mm x 27 mm x mm PBGA package 470031 SEE ECN YDT Changed VOL of V LVCMOS to V Updated tRSF VREF is DNU when HSTL is not used Formatted pin description table Changed VDDIO pins for 36M x 36 and 36M x 18 pinouts Changed 36M x 72 JTAG IDCODE 500001 SEE ECN YDT DLL Change, added Clock Input Cycle to Cycle Jitter Modified DLL description Changed Input Capacitance Table Changed tCCS number Added note 31 627539 SEE ECN QSL change all NC to DNU corrected switching waveform for CQEN = High from both Pipeline and Flow through mode to only pipeline mode Modified master reset description Modified switching characteristics tables, extracted signals effected by the DLL into one table and combine all other signals into one table updated package name Added footnote for tHD, tHAC and tSAC changed note 26 description 2505003 See ECN VKN / Modified footnote #1 AESA Removed 250 MHz speed bin Added 2-Mbit part and it’s related information Changed ball name ZQ1 to DNU for 18M and lesser density devices Added 256-ball 17 x 17 mm BGA package for 18M Made PORTSTD[1:0] left and right pins driven only by LVTTL reference level For V LVCMOS level, Changed VIH min from V to times VDDIO and changed VIL max from V to times VDDIO Changed tHD, tHAC specs for 36M from ns/0.7 ns to ns See footnote# Updated Ordering Information table Page 51 of 53 [+] Feedback CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Document History Page continued Document Title CYDXXS72V18/CYDXXS36V18/CYDXXS18V18, FullFlex Synchronous SDR Dual Port SRAM Document Number 38-06082 ECN NO. Submission Date Orig. of Change Description of Change 2898491 07/01/2010 RAME Modified “Counter Load Operation” section on page 12 and in Table7 on page Corrected typo in Table by making LowSPD = 0 for tCD1 spec in the description. Modified figure on page Removed inactive parts from Ordering Information. Updated Packaging Information. Corrected “Counter Interrupt operation” Section in Page 14 of the data sheet Updated ordering information with the parts, CYD02S36V18-200BBC and CYD36S72V18-167BGI. 2995098 07/28/2010 RAME Updated Ordering Information and added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits. 3267210 05/26/2011 ADMU Updated Electrical Characteristics on page 21 Removed 133 MHz speed bin . Updated Switching Characteristics on page 26 Removed 133 MHz speed bin . Removed information for 4Mb devices. Updated Ordering Information. 3357888 08/30/2011 ADMU Added Thermal Resistance. Updated Pin configuration Figure 1 through 3349458 10/28/2011 ADMU Minor edits in Figure 5 removed overbars in balls C5 and C12 . Updated Package Diagrams. Page 52 of 53 [+] Feedback CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 53 of 53 [+] Feedback

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CYDXXS72V18 CYDXXS36V18 CYDXXS18V18

FullFlex Synchronous SDR Dual Port SRAM

FullFlex Synchronous SDR Dual Port SRAM
• True dual port memory enables simultaneous access the shared array from each port
• Synchronous pipelined operation with single data rate SDR operation on each port SDR interface at 200 MHz Up to Gb/s bandwidth 200 MHz x 72-bit x 2 ports
• Selectable pipelined or flow-through mode
• V or V core power supply
• Commercial and Industrial temperature
• IEEE JTAG boundary scan
• Available in 484-ball PBGA x 72 and 256-ball FBGA x 36 and x 18 packages
• FullFlex72 family 36-Mbit 512 K x 72 CYD36S72V18 18-Mbit 256 K x 72 CYD18S72V18 9-Mbit 128 K x 72 CYD09S72V18
• FullFlex36 family 36-Mbit 1 M x 36 CYD36S36V18 18-Mbit 512 K x 36 CYD18S36V18 9-Mbit 256 K x 36 CYD09S36V18 2-Mbit 64 K x 36 CYD02S36V18
• FullFlex18 family 36-Mbit 2 M x 18 CYD36S18V18 18-Mbit 1 M x 18 CYD18S18V18 9-Mbit 512 K x 18 CYD09S18V18
• Built in deterministic access control to manage address collisions Deterministic flag output upon collision detection Collision detection on back-to-back clock cycles First busy address readback
• Advanced features for improved high speed data transfer and flexibility Variable impedance matching VIM Echo clocks Selectable LVTTL V , Extended HSTL V to V , V LVCMOS, or V LVCMOS IO on each port Burst counters for sequential memory access Mailbox with interrupt flags for message passing Dual chip enables for easy depth expansion

Functional Description

The FullFlex dual port SRAM families consist of 2-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power V or V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode.

The advanced features include the following:
• Built in deterministic access control to manage address collisions during simultaneous access to the same memory location
• Variable impedance matching VIM to improve data transmission by matching the output driver impedance to the line impedance
• Echo clocks to improve data transfer

To reduce the static power consumption, chip enables power down the internal circuitry. The number of latency cycles before a change in CE0 or CE1 enables or disables the databus matches the number of cycles of read latency selected for the device. For a valid write or read to occur, activate both chip enable inputs on a port.

Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally.

Additional device features include a mask register and a mirror register to control counter increments and wrap around. The counter interrupt CNTINT flags notify the host that the counter reaches maximum count value on the next clock cycle. The host reads the burst counter internal address, mask register address, and busy address on the address lines. The host also loads the counter with the address stored in the mirror register by using the retransmit functionality. Mailbox interrupt flags are used for message passing, and JTAG boundary scan and asynchronous Master Reset MRST are also available. The Logic Block Diagram on page 2 shows these features.

The FullFlex72 is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 are available in 256-ball fine pitch BGA package except the 36-Mbit devices which are offered in 484-ball plastic BGA package.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CYDXXS72V18 CYDXXS36V18 CYDXXS18V18

Logic Block Diagram

The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows [1, 2, 3]

FTSELL CQENL PORTSTD[1:0]L

CONFIG Block

CONFIG Block

DQ[71:0]L BE [7:0]L

CE0L CE1L OEL

R/WL CQ1L CQ0L

IO Control

IO Control

Dual Port Array

FTSELR CQENR PORTSTD[1:0]R

DQ [71:0]R BE [7:0]R
Switching Characteristics 26 Switching Waveforms 29 Ordering Information 43
512 K x 72 36-Mbit V/1.5 V Synchronous CYD36S72V18 Dual Port SRAM 43
256 K x 72 18-Mbit V/1.5 V Synchronous CYD18S72V18 Dual Port SRAM 43
128 K x 72 9-Mbit V/1.5 V Synchronous CYD09S72V18 Dual Port SRAM 43
1024 K x 36-Mbit V/1.5 V Synchronous CYD36S36V18 Dual Port SRAM 43
512 K x 36 18-Mbit V/1.5 V Synchronous CYD18S36V18 Dual Port SRAM 43
256 K x 36 9-Mbit V/1.5 V Synchronous CYD09S36V18 Dual Port SRAM 44
64 K x 36 2-Mbit V or V Synchronous CYD02S36V18 Dual Port SRAM 44
2048 K x 18 36-Mbit V/1.5 V Synchronous CYD36S18V18 Dual Port SRAM 45
1024 K x 18-Mbit V/1.5 V Synchronous CYD18S18V18 Dual Port SRAM 45
512 K x 18 9-Mbit V/1.5 V Synchronous CYD09S18V18 Dual Port SRAM 45
Ordering Code Definitions 45 Package Diagrams 46 Acronyms 49 Document Conventions 49

Units of Measure 49 Document History Page 50 Sales, Solutions, and Legal Information 53

Worldwide Sales and Design Support 53 Products 53 PSoC Solutions 53

Page 3 of 53 [+] Feedback

CYDXXS72V18 CYDXXS36V18 CYDXXS18V18

Figure FullFlex72 SDR 484-ball BGA Pinout Top View
11 12
21 22

A DNU DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ51R DQ54R DQ57R DQ59R DQ61R DNU

B DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R

C DQ65L DQ64L VSS D DQ67L DQ66L VSS

DQ56L DQ53L DQ50L DQ47L DQ44L DQ41L DQ38L DQ38R DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R VSS CQ1L VSS LOWSPDL PORTSTD0L ZQ0L[4] BUSYL CNTINTL PORTSTD1L DNU CQ1R VSS

DQ64R DQ65R DQ66R DQ67R

E DQ69L DQ68L VDDIOL VSS VDDIOL VTTL VDDIOR DNU VSS VDDIOR DQ68R DQ69R

F DQ71L DQ70L CE1L CE0L VDDIOL VCORE VDDIOR CE0R CE1R DQ70R DQ71R

G A0L A1L RETL BE4L VDDIOL VREFL VSS

VSS VREFR VDDIOR BE4R RETR A1R A0R

H A2L A3L WRPL BE5L VDDIOL VSS

VSS VDDIOR BE5R WRPR A3R A2R

J A4L K A6L

A5L READYL BE6L VDDIOL VSS A7L ZQ1L[4, 5] BE7L VTTL VCORE VSS

VSS VDDIOR BE6R READYR A5R A4R VSS VCORE VDDIOR BE7R ZQ1R[4, 5] A7R A6R

L A8L A9L

OEL VTTL VCORE VSS

VSS VCORE VTTL OER

A9R A8R

M A10L A11L VSS BE3L VTTL VCORE VSS

VSS VCORE VTTL BE3R VSS A11R A10R

N A12L A13L ADSL BE2L VDDIOL VCORE VSS

VSS VCORE VTTL BE2R ADSR A13R A12R

P A14L A15L CNT/MSKL BE1L VDDIOL VSS R A16L[8] A17L[7] CNTENL BE0L VDDIOL VSS T A18L[6] DNU CNTRSTL INTL VDDIOL VREFL

VSS VDDIOR BE1R CNT/MSKR A15R A14R VSS VDDIOR BE0R CNTENR A17R[7] A16R[8] VREFR VDDIOR INTR CNTRSTR DNU A18R[6]

U DQ35L DQ34L R/WL CQENL VDDIOL VCORE VDDIOR CQENR R/WR DQ34R DQ35R

V DQ33L DQ32L FTSELL VDDIOL W DQ31L DQ30L VSS MRST

DNU VSS

VDDIOL VTTL VDDIOR TRST VDDIOR FTSELR DQ32R DQ33R

CQ0L DNU PORTSTD1R CNTINTR BUSYR ZQ0R[4] PORTSTD0R LOWSPDR VSS CQ0R VSS

TDO DQ30R DQ31R

Y DQ29L DQ28L VSS DQ20L DQ17L DQ14L DQ11L DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11R DQ14R DQ17R DQ20R TMS TCK DQ28R DQ29R

AA DQ27L DQ26L DQ24L DQ22L DQ19L DQ16L DQ13L DQ10L DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10R DQ13R DQ16R DQ19R DQ22R DQ24R DQ26R DQ27R

AB DNU DQ25L DQ23L DQ21L DQ18L DQ15L DQ12L DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12R DQ15R DQ18R DQ21R DQ23R DQ25R DNU
Ordering Information
512 K x 72 36-Mbit V/1.5 V Synchronous CYD36S72V18 Dual Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
200 CYD36S72V18-200BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial
167 CYD36S72V18-167BGXI 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Industrial
256 K x 72 18-Mbit V/1.5 V Synchronous CYD18S72V18 Dual Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
200 CYD18S72V18-200BGXI
51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Industrial
200 CYD18S72V18-200BGI
51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch

Industrial
167 CYD18S72V18-167BGXC 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Commercial
167 CYD18S72V18-167BGC
51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch

Commercial
167 CYD18S72V18-167BGI
51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch

Industrial
128 K x 72 9-Mbit V/1.5 V Synchronous CYD09S72V18 Dual Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
200 CYD09S72V18-200BGXI
51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Industrial
167 CYD09S72V18-167BBXC 51-85218 484-ball Grid Array 23 mm x 23 mm with mm pitch Pb-free Commercial
1024 K x 36-Mbit V/1.5 V Synchronous CYD36S36V18 Dual Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
200 CYD36S36V18-200BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial
167 CYD36S36V18-167BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial
167 CYD36S36V18-167BGXI 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Industrial
512 K x 36 18-Mbit V/1.5 V Synchronous CYD18S36V18 Dual Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
200 CYD18S36V18-200BBAXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial
167 CYD18S36V18-167BBAI
51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch

Industrial

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CYDXXS72V18 CYDXXS36V18 CYDXXS18V18
Ordering Information continued
256 K x 36 9-Mbit V/1.5 V Synchronous CYD09S36V18 Dual Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
200 CYD09S36V18-200BBXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial
200 CYD09S36V18-200BBXI
51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial
167 CYD09S36V18-167BBXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial
64 K x 36 2-Mbit V or V Synchronous CYD02S36V18 Dual Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type
200 CYD02S36V18-200BBC
51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch

Operating Range

Commercial

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CYDXXS72V18 CYDXXS36V18 CYDXXS18V18
Ordering Information continued
2048 K x 18 36-Mbit V/1.5 V Synchronous CYD36S18V18 Dual Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
200 CYD36S18V18-200BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial
167 CYD36S18V18-167BGXC 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Commercial
167 CYD36S18V18-167BGXI 001-07825 484-ball Grid Array 27 mm x 27 mm with mm pitch Pb-free Industrial
1024 K x 18-Mbit V/1.5 V Synchronous CYD18S18V18 Dual Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
200 CYD18S18V18-200BBAXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial
200 CYD18S18V18-200BBAXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial
167 CYD18S18V18-167BBAXI 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial
512 K x 18 9-Mbit V/1.5 V Synchronous CYD09S18V18 Dual Port SRAM

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
200 CYD09S18V18-200BBXC 51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Commercial
200 CYD09S18V18-200BBXI
51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial
167 CYD09S18V18-167BBXI
51-85108 256-ball Grid Array 17 mm x 17 mm with mm pitch Pb-free Industrial
Ordering Code Definitions CY DXX SXX V18 - XXX X

Temperature Range X = C or I C = Commercial I = Industrial Pb-free Package Type XXX = BG or BB or BBA BG, BB, BBA = Ball Grid Array Speed Grade XXX = 167 MHz or 200 MHz V18 = V SXX = Data Width DXX = Density in Mb CY = Cypress

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CYDXXS72V18 CYDXXS36V18 CYDXXS18V18

Package Diagrams

Figure 256-ball FBGA 17 x 17 x mm BB256/BW0BD Package Outline, 51-85108
51-85108 *I

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CYDXXS72V18 CYDXXS36V18 CYDXXS18V18

Package Diagrams continued

Figure 484-ball PBGA 23 x 23 x mm BY484 Package Outline, 51-85218
51-85218 *A

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CYDXXS72V18 CYDXXS36V18 CYDXXS18V18

Package Diagrams continued

Figure 484-ball PBGA 27 x 27 x mm BY484S Package Outline, 001-07825
001-07825 *A

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Acronyms

Acronym
ball grid array

CMOS complementary metal oxide semiconductor
delay lock loop

FBGA
fine pitch ball gird array

HSTL
high speed transceiver logic
input/output
single data rate

SRAM
static random access memory
test clock
test data-in
test data-out
test mode select
variable impedance matching

CYDXXS72V18 CYDXXS36V18 CYDXXS18V18

Document Conventions

Units of Measure

Symbol °C MHz µA mA ms mV ns pF V W

Unit of Measure degree Celsius megahertz microampere milliampere millisecond millivolt nanosecond picofarad volt watt
YDT Changed ordering information with Pb-free part numbers

Removed VC_SEL

Added IO and core voltage adders

Removed references to bin drop for LVTTL/2.5 V LVCMOS and V core
modes

Updated Cin and Cout Updated ICC, ISB1, ISB2 and ISB3 tables

Updated busy address read back timing diagram

Added HTSL input waveform

Removed HSTL AC from DC tables Added 484-ball 27 mm x 27 mm x mm PBGA package
470031 SEE ECN

YDT Changed VOL of V LVCMOS to V

Updated tRSF

VREF is DNU when HSTL is not used

Formatted pin description table

Changed VDDIO pins for 36M x 36 and 36M x 18 pinouts

Changed 36M x 72 JTAG IDCODE
500001 SEE ECN

YDT DLL Change, added Clock Input Cycle to Cycle Jitter

Modified DLL description

Changed Input Capacitance Table

Changed tCCS number

Added note 31
627539 SEE ECN

QSL change all NC to DNU
corrected switching waveform for CQEN = High from both Pipeline and Flow
through mode to only pipeline mode

Modified master reset description

Modified switching characteristics tables, extracted signals effected by the DLL
into one table and combine all other signals into one table
updated package name

Added footnote for tHD, tHAC and tSAC
changed note 26 description
2505003 See ECN

VKN / Modified footnote #1

AESA Removed 250 MHz speed bin

Added 2-Mbit part and it’s related information

Changed ball name ZQ1 to DNU for 18M and lesser density devices

Added 256-ball 17 x 17 mm BGA package for 18M

Made PORTSTD[1:0] left and right pins driven only by LVTTL reference level

For V LVCMOS level, Changed VIH min from V to times VDDIO and changed VIL max from V to times VDDIO Changed tHD, tHAC specs for 36M from ns/0.7 ns to ns See footnote#
Updated Ordering Information table

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CYDXXS72V18 CYDXXS36V18 CYDXXS18V18

Document History Page continued

Document Title CYDXXS72V18/CYDXXS36V18/CYDXXS18V18, FullFlex Synchronous SDR Dual Port SRAM Document Number 38-06082

ECN NO.

Submission Date

Orig. of Change

Description of Change
2898491 07/01/2010 RAME Modified “Counter Load Operation” section on page 12 and in Table7 on page

Corrected typo in Table by making LowSPD = 0 for tCD1 spec in the description.

Modified figure on page
Removed inactive parts from Ordering Information.

Updated Packaging Information.

Corrected “Counter Interrupt operation” Section in Page 14 of the data sheet
Updated ordering information with the parts, CYD02S36V18-200BBC and

CYD36S72V18-167BGI.
2995098 07/28/2010 RAME Updated Ordering Information and added Ordering Code Definitions.

Added Acronyms and Units of Measure.

Minor edits.
3267210 05/26/2011 ADMU Updated Electrical Characteristics on page 21 Removed 133 MHz speed bin .

Updated Switching Characteristics on page 26 Removed 133 MHz speed bin .

Removed information for 4Mb devices.
Updated Ordering Information.
3357888 08/30/2011 ADMU Added Thermal Resistance.

Updated Pin configuration Figure 1 through
3349458 10/28/2011 ADMU Minor edits in Figure 5 removed overbars in balls C5 and C12 .

Updated Package Diagrams.

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CYDXXS72V18 CYDXXS36V18 CYDXXS18V18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYD36S18V18-200BGXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CYD36S18V18-200BGXC 508197