CD4046BCN

CD4046BCN Datasheet

CD4046BC Micropower Phase-Locked Loop

Part	Datasheet
CD4046BCN	CD4046BCN (pdf)

Related Parts	Information
CD4046BCM	CD4046BCM

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CD4046BC Micropower Phase-Locked Loop CD4046BC Micropower Phase-Locked Loop The CD4046BC micropower phase-locked loop PLL consists of a low power, linear, voltage-controlled oscillator VCO , a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the signal input for a small voltage signal. Phase comparator I, an exclusive OR gate, provides a digital error signal phase comp. I Out and maintains 90° phase shifts at the VCO center frequency. Between signal input and comparator input both at 50% duty cycle , it may lock onto the signal input frequencies that are close to harmonics of the VCO center frequency. Phase comparator II is an edge-controlled digital memory network. It provides a digital error signal phase comp. II Out and lock-in signal phase pulses to indicate a locked condition and maintains a 0° phase shift between signal input and comparator input. The linear voltage-controlled oscillator VCO produces an output signal VCO Out whose frequency is determined by the voltage at the VCOIN input, and the capacitor and resistors connected to pin C1A, C1B, R1 and R2. The source follower output of the VCOIN demodulator Out is used with an external resistor of 10 or more. The INHIBIT input, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode is provided for power supply regulation, if necessary. s Wide supply voltage range 3.0V to 18V s Low dynamic power consumption 70 µW typ. at fo = 10 kHz, VDD = 5V s VCO frequency MHz typ. at VDD = 10V s Low frequency drift 0.06%/°C at VDD = 10V with temperature s High VCO linearity 1% typ. • FM demodulator and modulator • Frequency synthesis and multiplication • Frequency discrimination • Data synchronization and conditioning • Voltage-to-frequency conversion • Tone decoding • FSK modulation • Motor speed control Ordering Code: Order Number Package Number Package Description CD4046BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4046BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2002 Fairchild Semiconductor Corporation DS005968 CD4046BC Connection Diagram Block Diagram Top View FIGURE CD4046BC Absolute Maximum Ratings Note 1 Note 2 DC Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD Dual-In-Line Small Outline Lead Temperature TL Soldering, 10 seconds to +18 VDC to VDD VDC −65°C to +150°C 700 mW 500 mW 260°C Recommended Operating Conditions Note 2 DC Supply Voltage VDD 3 to 15 VDC Input Voltage VIN 0 to VDD VDC Operating Temperature Range TA −55°C to +125°C Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. Note 2 VSS = 0V unless otherwise specified. DC Electrical Characteristics Note 2 Parameter Conditions Quiescent Device Current Pin 5 = VDD, Pin 14 = VDD, Pin 3, 9 = VSS VDD = 5V VDD = 10V VDD = 15V Pin 5 = VDD, Pin 14 = Open, Pin 3, 9 = VSS VDD = 5V VDD = 10V VDD = 15V LOW Level Output Voltage VDD = 5V

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CD4046BC Micropower Phase-Locked Loop

CD4046BC Micropower Phase-Locked Loop

The CD4046BC micropower phase-locked loop PLL consists of a low power, linear, voltage-controlled oscillator VCO , a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the signal input for a small voltage signal.

Phase comparator I, an exclusive OR gate, provides a digital error signal phase comp. I Out and maintains 90° phase shifts at the VCO center frequency. Between signal input and comparator input both at 50% duty cycle , it may lock onto the signal input frequencies that are close to harmonics of the VCO center frequency.

Phase comparator II is an edge-controlled digital memory network. It provides a digital error signal phase comp. II Out and lock-in signal phase pulses to indicate a locked condition and maintains a 0° phase shift between signal input and comparator input.

The linear voltage-controlled oscillator VCO produces an output signal VCO Out whose frequency is determined by the voltage at the VCOIN input, and the capacitor and resistors connected to pin C1A, C1B, R1 and R2.

The source follower output of the VCOIN demodulator Out is used with an external resistor of 10 or more.

The INHIBIT input, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode is provided for power supply regulation, if necessary.
s Wide supply voltage range 3.0V to 18V s Low dynamic power consumption 70 µW typ.
at fo = 10 kHz, VDD = 5V s VCO frequency MHz typ. at VDD = 10V s Low frequency drift 0.06%/°C at VDD = 10V with
temperature s High VCO linearity 1% typ.
• FM demodulator and modulator
• Frequency synthesis and multiplication
• Frequency discrimination
• Data synchronization and conditioning
• Voltage-to-frequency conversion
• Tone decoding
• FSK modulation
• Motor speed control
Ordering Code:

Order Number Package Number

Package Description

CD4046BCM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4046BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2002 Fairchild Semiconductor Corporation DS005968

CD4046BC

Connection Diagram

Block Diagram

Top View

FIGURE

CD4046BC

Absolute Maximum Ratings Note 1

Note 2

DC Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD

Dual-In-Line

Small Outline

Lead Temperature TL Soldering, 10 seconds
to +18 VDC to VDD VDC
−65°C to +150°C
700 mW 500 mW
260°C

Recommended Operating Conditions Note 2

DC Supply Voltage VDD
3 to 15 VDC

Input Voltage VIN
0 to VDD VDC

Operating Temperature Range TA
−55°C to +125°C

Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation.

Note 2 VSS = 0V unless otherwise specified.

DC Electrical Characteristics Note 2

Parameter

Conditions

Quiescent Device Current

Pin 5 = VDD, Pin 14 = VDD,

Pin 3, 9 = VSS VDD = 5V VDD = 10V

VDD = 15V

Pin 5 = VDD, Pin 14 = Open,

Pin 3, 9 = VSS

VDD = 5V

VDD = 10V

VDD = 15V

LOW Level Output Voltage

VDD = 5V

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Datasheet ID: CD4046BCN 513568