CY9266-T

CY9266-T Datasheet

CY9266 HOTLink Evaluation Board User’s Guide

Part	Datasheet
CY9266-T	CY9266-T (pdf)

Related Parts	Information
CY9266-C	CY9266-C
CY9266-F	CY9266-F
CY9266-FX	CY9266-FX

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CY9266 HOTLink Evaluation Board User’s Guide Overview This document describes the construction, interfaces, and operation of the optical fiber , plastic optical fiber , shielded twisted pair/twinax , and coaxial cable HOTLink Evaluation Boards. These boards implement a complete bidirectional parallel-to-serial and serial-to-parallel communications link, capable of operation at serial rates of 150 to 400 Mbits/second 15 to 40 Mbytes/second . The supported rate of communication may be limited by the specific type and speed-grade of optical module or copper cable type used. The CY9266 Evaluation Boards are optically, electrically, and mechanically compatible with the ANSI T11 Fibre Channel Interface, as documented in the ANSI standard ANS It provides three different methods of access for the TTL parallel interface and supervisor functions, for testing or exercising the serial data link. Block Diagram The block diagram in Figure 1 illustrates the major functional blocks contained in the CY9266. These include: • 10-bit TTL parallel transmit data input • 10-bit TTL parallel receive data output • Selectable Encoded or Bypass operation modes • On-board socketed oscillator • Selectable internal/external clocking • Selectable signal-detect polarity • Selectable local loopback • Power supply voltage monitor • Built-in self-test BIST pattern generation and checking hardware with error/status display Board Connectors This board offers three primary methods of TTL-level access: • 58-position 2 x 29 set of holes, capable of accepting a sq. pin-header on the top or bottom of the board • 60-position 2 x 30 spaced board-edge finger stock • 48-position 4 x 12 matrix sq. pin-header mounted on the bottom of the board Connectors JP2 and JP3 provide access to all data input and output buses as well as all BIST, control, and clocking signals for the HOTLink Transmitter and Receiver. These connectors may be used individually or together since all signals present on JP2 are also present on JP3. Power for the board is also brought in through these same connectors. Connector JP4 is positioned and pinned to match up with the connector and signals present on other industry-standard Fibre Channel modules. Unlike these other modules which may contain two full-duplex channels , this evaluation board only provides a single full-duplex channel. While sufficient room exists to build a board with two channels, other functionality was added on-board oscillator, BIST PLD and display, etc. in this space to allow better testing and demonstration of the enhanced capabilities present in the Cypress HOTLink parts. Board Header CY7B923 XMTR Optical or Copper XMTR Board Edge JP3 Latch CY7B933 RCVR Optical or Copper RCVR OLC Header BIST PLD BIST Display Figure HOTLink Evaluation Board Block Diagram Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 11, 1999 CY9266 HOTLink Evaluation Board User’s Guide An additional jumper block JP1 is used to configure three of the operating characteristics of the board clock sourcing, serial output enable FOTO , and local loopback control. Optical Modules The Evaluation Board is designed to operate with industry-standard footprint optical modules. The evaluation board contains low-profile socket pins so the user may select and test optical modules from different vendors. This board accepts both the four-row DIP and the single-row 1X9 types of modules. These modules are available from multiple vendors with either ST- or SC-type optical fiber connectors. Because these modules are all LED-based, they are not required to meet many of the safety standards ANSI Z136.1 and Z136.2, F.D.A. regulation 21 CFR subchapter J, and IEC 825 necessary for LASER-based modules. These modules should be used with 62.5/125-mm multimode graded-index fiber. For longer distance communications, LASER-based modules are also available that are compatible with the cards. However, when used with LASER transmitters, it is the responsibility of the user to receive what ever safety certifications are necessary. The Evaluation Board is electrically identical to the except that it is shipped with an optical module configured for low-cost plastic optical fiber, and set for a lower data rate 155 MBaud .

PDF Datasheet Preview

CY9266 HOTLink Evaluation Board User’s Guide

Overview

This document describes the construction, interfaces, and operation of the optical fiber , plastic optical fiber , shielded twisted pair/twinax , and coaxial cable HOTLink Evaluation Boards. These boards implement a complete bidirectional parallel-to-serial and serial-to-parallel communications link, capable of operation at serial rates of 150 to 400 Mbits/second 15 to 40 Mbytes/second . The supported rate of communication may be limited by the specific type and speed-grade of optical module or copper cable type used.

The CY9266 Evaluation Boards are optically, electrically, and mechanically compatible with the ANSI T11 Fibre Channel Interface, as documented in the ANSI standard ANS It provides three different methods of access for the TTL parallel interface and supervisor functions, for testing or exercising the serial data link.

Block Diagram

The block diagram in Figure 1 illustrates the major functional blocks contained in the CY9266. These include:
• 10-bit TTL parallel transmit data input
• 10-bit TTL parallel receive data output
• Selectable Encoded or Bypass operation modes
• On-board socketed oscillator
• Selectable internal/external clocking
• Selectable signal-detect polarity
• Selectable local loopback
• Power supply voltage monitor
• Built-in self-test BIST pattern generation and checking hardware with error/status display

Board Connectors

This board offers three primary methods of TTL-level access:
• 58-position 2 x 29 set of holes, capable of accepting a sq. pin-header on the top or bottom of the board
• 60-position 2 x 30 spaced board-edge finger stock
• 48-position 4 x 12 matrix sq. pin-header mounted on the bottom of the board

Connectors JP2 and JP3 provide access to all data input and output buses as well as all BIST, control, and clocking signals for the HOTLink Transmitter and Receiver. These connectors may be used individually or together since all signals present on JP2 are also present on JP3. Power for the board is also brought in through these same connectors.

Connector JP4 is positioned and pinned to match up with the connector and signals present on other industry-standard Fibre Channel modules. Unlike these other modules which may contain two full-duplex channels , this evaluation board only provides a single full-duplex channel. While sufficient room exists to build a board with two channels, other functionality was added on-board oscillator, BIST PLD and display, etc. in this space to allow better testing and demonstration of the enhanced capabilities present in the Cypress HOTLink parts.

Board Header

CY7B923 XMTR

Optical or Copper XMTR

Board Edge JP3

Latch

CY7B933 RCVR

Optical or Copper RCVR

OLC Header

BIST PLD

BIST Display

Figure HOTLink Evaluation Board Block Diagram

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600 March 11, 1999

CY9266 HOTLink Evaluation Board User’s Guide

An additional jumper block JP1 is used to configure three of the operating characteristics of the board clock sourcing, serial output enable FOTO , and local loopback control.

Optical Modules

The Evaluation Board is designed to operate with industry-standard footprint optical modules. The evaluation board contains low-profile socket pins so the user may select and test optical modules from different vendors. This board accepts both the four-row DIP and the single-row 1X9 types of modules.

These modules are available from multiple vendors with either ST- or SC-type optical fiber connectors. Because these modules are all LED-based, they are not required to meet many of the safety standards ANSI Z136.1 and Z136.2, F.D.A. regulation 21 CFR subchapter J, and IEC 825 necessary for LASER-based modules. These modules should be used with 62.5/125-mm multimode graded-index fiber.

For longer distance communications, LASER-based modules are also available that are compatible with the cards. However, when used with LASER transmitters, it is the responsibility of the user to receive what ever safety certifications are necessary.

The Evaluation Board is electrically identical to the except that it is shipped with an optical module configured for low-cost plastic optical fiber, and set for a lower data rate 155 MBaud .

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY9266-T Datasheet file may be downloaded here without warranties.

Datasheet ID: CY9266-T 508189