CY8C5366LTI-053

CY8C5366LTI-053 Datasheet

5 CY8C53 Family Datasheet

Part	Datasheet
CY8C5366LTI-053	CY8C5366LTI-053 (pdf)

Related Parts	Information
CY8C5367LTI-003	CY8C5367LTI-003
CY8C5365LTI-104	CY8C5365LTI-104
CY8C5368LTI-026	CY8C5368LTI-026
CY8C5368AXI-106	CY8C5368AXI-106
CY8C5366AXI-001	CY8C5366AXI-001
CY8C5365AXI-043	CY8C5365AXI-043

PDF Datasheet Preview
5 CY8C53 Family Datasheet Programmable System-on-Chip With its unique array of configurable blocks, 5 is a true system level solution providing microcontroller unit MCU , memory, analog, and digital peripheral functions in a single chip. The CY8C53 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples near DC voltages to ultrasonic signals. The CY8C53 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C53 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multi-master I2C. In addition to communication interfaces, the CY8C53 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit Cortex -M3 microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using Creator , a hierarchical schematic design entry tool. The CY8C53 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. 32-bit ARM Cortex-M3 CPU core DC to 67 MHz operation Flash program memory, up to 256 KB, 100,000 write cycles, 20-year retention, multiple security features Up to 64 KB SRAM memory 128 bytes of cache memory 2-KB electrically erasable programmable read-only memory EEPROM memory, 1 million cycles, and 20 years retention 24-channel direct memory access DMA with multilayer AMBA high-performance bus AHB bus access • Programmable chained descriptors and priorities • High bandwidth 32-bit transfer support Low voltage, ultra low power Operating voltage range V to V 6 mA at 6 MHz Low power modes including • 2-µA sleep mode • 300-nA hibernate mode with RAM retention Versatile I/O system 46 to 70 I/Os 60 GPIOs, 8 SIOs, 2 USBIOs Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46x16 segments support from any GPIO[1] V to V I/O interface voltages, up to 4 domains Maskable, independent IRQ on any pin or port Schmitt-trigger transistor-transistor logic TTL inputs All GPIOs configurable as open drain high/low, pull-up/pull-down, High-Z, or strong output 25 mA sink on SIO Digital peripherals 20 to 24 programmable logic device PLD based universal digital blocks UDBs Full-Speed FS USB 12 Mbps using a 24 MHz external oscillator Up to four 16-bit configurable timer, counter, and PWM blocks Library of standard peripherals • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs • SPI, UART, and I2C • Many others available in catalog Library of advanced peripherals • Cyclic redundancy check CRC • Pseudo random sequence PRS generator • Local interconnect network LIN bus • Quadrature decoder Analog peripherals V VDDA V ±1% internal voltage reference Successive approximation register SAR analog-to-digital converter ADC , 12-bit at 700 ksps Two 8-bit Msps current digital-to-analog converters DAC IDACs or 1 Msps voltage DACs VDACs Four comparators with 95-ns response time Two uncommitted opamps with 10-mA drive capability Two configurable multifunction analog blocks. Example configurations are programmable gain amplifier PGA , transimpedance amplifier TIA , mixer, and sample and hold CapSense support Programming, debug, and trace Serial wire debug SWD and single-wire viewer SWV interfaces Cortex-M3 flash patch and breakpoint FPB block Cortex-M3 data watchpoint and trace DWT generates data trace information Cortex-M3 instrumentation trace macrocell ITM can be used for printf-style debugging DWT and ITM blocks communicate with off-chip debug and trace systems via the SWV interface Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces Precision, programmable clocking 3 to 48 MHz internal oscillator over full temperature and voltage range 4 to 25 MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 67 MHz kHz watch crystal oscillator Low power internal oscillator at 1, 33, and 100 kHz Temperature and packaging -40°C to +85°C degrees industrial temperature 68-pin QFN and 100-pin TQFP package options Note GPIOs with opamp outputs are not recommended for use with CapSense. • 198 Champion Court San Jose, CA 95134-1709 408-943-2600 5 CY8C53 Family Datasheet Contents Architectural Overview 3 Pinouts 5 Pin Descriptions 9 CPU 10 ARM Cortex-M3 CPU 10 Cache Controller 12 DMA and PHUB 12 Interrupt Controller 14 Memory 16 Static RAM 16 Flash Program Memory 16 Flash Security 16 EEPROM 16 Memory Map 17 System Integration 18 Clocking System 18 Power System 22 Reset 24 I/O System and Routing 25 Digital Subsystem 32 Example Peripherals 32 Universal Digital Block 36 UDB Array Description 39 DSI Routing Interface Description 39 USB 41 Timers, Counters, and PWMs 41 I2C 43 Analog Subsystem 44 Analog Routing 45 Successive Approximation ADC 47 Comparators 47 Opamps 49 Programmable SC/CT Blocks 49 LCD Direct Drive 50 CapSense 51 Temp Sensor 51 DAC Up/Down Mixer Sample and Hold Programming, Debug Interfaces, Resources Debug Port Acquisition SWD Interface Debug Features Trace Features SWV Interface Programming Features Device Security Development Support Documentation Online Tools Electrical Specifications Absolute Maximum Ratings Device Level Specifications Power Regulators Inputs and Outputs Analog Peripherals Digital Peripherals Memory PSoC System Resources Clocking Ordering Information Part Numbering Conventions Packaging Acronyms Reference Documents Document Conventions Units of Measure Sales, Solutions, and Legal Information Page 2 of 105 5 CY8C53 Family Datasheet Architectural Overview Introducing the CY8C53 family of ultra low-power, flash Programmable System-on-Chip devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C53 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure Simplified Block Diagram 4 to25 MHz Optional KHz Optional SIOs GPIOs GPIOs GPIOs System Wide Resources Xtal Osc RTC Timer WDT and Wake Clocking System Power Management System POR and LVD Sleep Power V LDO Clock Tree Usage Example for UDB Sequencer Digital Interconnect Analog Interconnect Digital System Universal Digital Block Array 24 x UDB 8- Bit Timer Quadrature Decoder 16-Bit PWM 16- Bit PRS UDB I 2C Slave UDB 8- Bit SPI UDB UART UDB 12- Bit SPI UDB 8- Bit Timer Logic Logic UDB Ordering Information In addition to the features listed in Table 12-1, every CY8C53 device includes up to 128 KB flash, 32 KB SRAM, 2 KB EEPROM, a precision on-chip voltage reference, precision oscillators, flash, DMA, a fixed function I2C, SWD programming and debug, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes derivatives incorporate device and a part recommendation after you choose flash security in user-selectable security tlheeveclosm; application. CY8C53 Table CY8C53 Family with ARM Cortex-M3 CPU MCU Core Analog Digital I/O[50] Package Device ID[51] CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive ADC DAC Comparators SC/CT Analog Blocks[48] Opamps DFB CapSense UDBs[49] 16-bit Timer/PWM FS USB Total I/O GPIO SIO USBIO CY8C5368LTI-026 67 256 64 2 1 x 12-bit SAR 2 4 2 24 4 46 36 8 2 68-pin QFN 0x0E11A069 CY8C5368AXI-106 67 256 64 2 1 x 12-bit SAR 2 4 2 24 4 70 60 8 2 100-pin TQFP 0x0E16A069 CY8C5367LTI-003 67 128 32 2 1 x 12-bit SAR 2 4 2 24 4 46 36 8 2 68-pin QFN 0x0E103069 CY8C5367AXI-108 67 128 32 2 1 x 12-bit SAR 2 4 2 24 4 70 60 8 2 100-pin TQFP 0x0E16C069 CY8C5366LTI-053 67 64 16 2 1 x 12-bit SAR 2 4 2 24 4 46 36 8 2 68-pin QFN 0x0E135069 CY8C5366AXI-001 67 64 16 2 1 x 12-bit SAR 2 4 2 24 4 70 60 8 2 100-pin TQFP 0x0E101069 CY8C5365LTI-104 67 32 8 2 1 x 12-bit SAR 2 4 2 20 4 46 36 8 2 68-pin QFN 0x0E168069 CY8C5365AXI-043 67 32 8 2 1 x 12-bit SAR 2 4 2 20 4 70 60 8 2 100-pin TQFP 0x0E12B069 Notes Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 32 for more information on how analog blocks can be used. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 32 for more information on how UDBs can be used. The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 25 for details on the functionality of each of these types of I/O. The device ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID. Page 96 of 105 5 CY8C53 Family Datasheet Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric 0, 1, 2, 9, A, B, Z unless stated otherwise. CY8Cabcdefg-xxx a Architecture 3 PSoC 3 5 PSoC 5 b Family group within architecture 2 CY8C52 family 3 CY8C53 family 4 CY8C54 family 5 CY8C55 family c Speed grade 4 40 MHz 6 67 MHz d Flash capacity 5 32 KB 6 64 KB 7 128 KB 8 256 KB ef Package code Two character alphanumeric AX TQFP LT QFN g Temperature range C commercial I industrial A automotive xxx Peripheral set Three character numeric No meaning is associated with these three characters Examples CY8C 5 3 6 8 AX /LT I - x Cypress Prefix 5 PSoC 5 Architecture 3 CY8C53 Family Family Group within Architecture 6 67 MHz Speed Grade 8 256 KB

PDF Datasheet Preview

5 CY8C53 Family Datasheet

Programmable System-on-Chip

With its unique array of configurable blocks, 5 is a true system level solution providing microcontroller unit MCU , memory, analog, and digital peripheral functions in a single chip. The CY8C53 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples near DC voltages to ultrasonic signals. The CY8C53 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C53 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multi-master I2C. In addition to communication interfaces, the CY8C53 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit Cortex -M3 microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using Creator , a hierarchical schematic design entry tool. The CY8C53 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
32-bit ARM Cortex-M3 CPU core DC to 67 MHz operation Flash program memory, up to 256 KB, 100,000 write cycles, 20-year retention, multiple security features Up to 64 KB SRAM memory 128 bytes of cache memory 2-KB electrically erasable programmable read-only memory EEPROM memory, 1 million cycles, and 20 years retention 24-channel direct memory access DMA with multilayer AMBA high-performance bus AHB bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support

Low voltage, ultra low power Operating voltage range V to V 6 mA at 6 MHz Low power modes including
• 2-µA sleep mode
• 300-nA hibernate mode with RAM retention

Versatile I/O system 46 to 70 I/Os 60 GPIOs, 8 SIOs, 2 USBIOs Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46x16 segments support from any GPIO[1] V to V I/O interface voltages, up to 4 domains Maskable, independent IRQ on any pin or port Schmitt-trigger transistor-transistor logic TTL inputs All GPIOs configurable as open drain high/low, pull-up/pull-down, High-Z, or strong output 25 mA sink on SIO

Digital peripherals 20 to 24 programmable logic device PLD based universal digital blocks UDBs Full-Speed FS USB 12 Mbps using a 24 MHz external oscillator Up to four 16-bit configurable timer, counter, and PWM blocks Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• SPI, UART, and I2C
• Many others available in catalog

Library of advanced peripherals
• Cyclic redundancy check CRC
• Pseudo random sequence PRS generator
• Local interconnect network LIN bus
• Quadrature decoder

Analog peripherals V VDDA V ±1% internal voltage reference Successive approximation register SAR analog-to-digital converter ADC , 12-bit at 700 ksps Two 8-bit Msps current digital-to-analog converters DAC IDACs or 1 Msps voltage DACs VDACs Four comparators with 95-ns response time Two uncommitted opamps with 10-mA drive capability Two configurable multifunction analog blocks. Example configurations are programmable gain amplifier PGA , transimpedance amplifier TIA , mixer, and sample and hold CapSense support

Programming, debug, and trace Serial wire debug SWD and single-wire viewer SWV interfaces Cortex-M3 flash patch and breakpoint FPB block Cortex-M3 data watchpoint and trace DWT generates data trace information Cortex-M3 instrumentation trace macrocell ITM can be used for printf-style debugging DWT and ITM blocks communicate with off-chip debug and trace systems via the SWV interface Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces

Precision, programmable clocking 3 to 48 MHz internal oscillator over full temperature and voltage range 4 to 25 MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 67 MHz kHz watch crystal oscillator Low power internal oscillator at 1, 33, and 100 kHz

Temperature and packaging -40°C to +85°C degrees industrial temperature 68-pin QFN and 100-pin TQFP package options

Note GPIOs with opamp outputs are not recommended for use with CapSense.
• 198 Champion Court

San Jose, CA 95134-1709
408-943-2600
5 CY8C53 Family Datasheet

Contents

Architectural Overview 3

Pinouts 5

Pin Descriptions 9

CPU 10 ARM Cortex-M3 CPU 10 Cache Controller 12 DMA and PHUB 12 Interrupt Controller 14

Memory 16 Static RAM 16 Flash Program Memory 16 Flash Security 16 EEPROM 16 Memory Map 17

System Integration 18 Clocking System 18 Power System 22 Reset 24 I/O System and Routing 25

Digital Subsystem 32 Example Peripherals 32 Universal Digital Block 36 UDB Array Description 39 DSI Routing Interface Description 39 USB 41 Timers, Counters, and PWMs 41 I2C 43

Analog Subsystem 44 Analog Routing 45 Successive Approximation ADC 47 Comparators 47 Opamps 49 Programmable SC/CT Blocks 49 LCD Direct Drive 50 CapSense 51 Temp Sensor 51

DAC Up/Down Mixer Sample and Hold

Programming, Debug Interfaces, Resources Debug Port Acquisition SWD Interface Debug Features Trace Features SWV Interface Programming Features Device Security

Development Support Documentation Online Tools

Electrical Specifications Absolute Maximum Ratings Device Level Specifications Power Regulators Inputs and Outputs Analog Peripherals Digital Peripherals Memory PSoC System Resources Clocking
Ordering Information Part Numbering Conventions

Packaging

Acronyms

Reference Documents

Document Conventions Units of Measure

Sales, Solutions, and Legal Information

Page 2 of 105
5 CY8C53 Family Datasheet

Architectural Overview

Introducing the CY8C53 family of ultra low-power, flash Programmable System-on-Chip devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C53 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure Simplified Block Diagram
4 to25 MHz Optional

KHz Optional

SIOs

GPIOs

GPIOs

GPIOs

System Wide Resources

Xtal Osc

RTC Timer

WDT and Wake

Clocking System

Power Management System

POR and LVD Sleep Power

V LDO

Clock Tree Usage Example for UDB

Sequencer

Digital Interconnect

Analog Interconnect

Digital System

Universal Digital Block Array 24 x UDB
8- Bit Timer

Quadrature Decoder
16-Bit PWM
16- Bit PRS

UDB I 2C Slave

UDB 8- Bit SPI

UDB UART

UDB 12- Bit SPI

UDB 8- Bit Timer Logic

Logic UDB
Ordering Information

In addition to the features listed in Table 12-1, every CY8C53 device includes up to 128 KB flash, 32 KB SRAM, 2 KB EEPROM, a precision on-chip voltage reference, precision oscillators, flash, DMA, a fixed function I2C, SWD programming and debug, and more.

In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting
the ideal part, PSoC Creator makes derivatives incorporate device and
a part recommendation after you choose flash security in user-selectable security
tlheeveclosm;
application.

CY8C53

Table CY8C53 Family with ARM Cortex-M3 CPU

MCU Core

Analog

Digital

I/O[50]

Package

Device ID[51]

CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive ADC DAC Comparators SC/CT Analog Blocks[48] Opamps DFB CapSense UDBs[49] 16-bit Timer/PWM FS USB Total I/O GPIO SIO USBIO

CY8C5368LTI-026 67 256 64 2 1 x 12-bit SAR 2 4 2 24 4 46 36 8 2 68-pin QFN 0x0E11A069 CY8C5368AXI-106 67 256 64 2 1 x 12-bit SAR 2 4 2 24 4 70 60 8 2 100-pin TQFP 0x0E16A069 CY8C5367LTI-003 67 128 32 2 1 x 12-bit SAR 2 4 2 24 4 46 36 8 2 68-pin QFN 0x0E103069 CY8C5367AXI-108 67 128 32 2 1 x 12-bit SAR 2 4 2 24 4 70 60 8 2 100-pin TQFP 0x0E16C069 CY8C5366LTI-053 67 64 16 2 1 x 12-bit SAR 2 4 2 24 4 46 36 8 2 68-pin QFN 0x0E135069 CY8C5366AXI-001 67 64 16 2 1 x 12-bit SAR 2 4 2 24 4 70 60 8 2 100-pin TQFP 0x0E101069 CY8C5365LTI-104 67 32 8 2 1 x 12-bit SAR 2 4 2 20 4 46 36 8 2 68-pin QFN 0x0E168069 CY8C5365AXI-043 67 32 8 2 1 x 12-bit SAR 2 4 2 20 4 70 60 8 2 100-pin TQFP 0x0E12B069

Notes Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 32 for more information on how analog blocks
can be used. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 32 for more information on how UDBs can be used. The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 25 for details on the functionality of each of
these types of I/O. The device ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.

Page 96 of 105
5 CY8C53 Family Datasheet

Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric 0, 1, 2, 9, A, B, Z unless stated otherwise. CY8Cabcdefg-xxx
a Architecture 3 PSoC 3 5 PSoC 5
b Family group within architecture 2 CY8C52 family 3 CY8C53 family 4 CY8C54 family 5 CY8C55 family
c Speed grade 4 40 MHz 6 67 MHz
d Flash capacity 5 32 KB 6 64 KB 7 128 KB 8 256 KB
ef Package code Two character alphanumeric AX TQFP LT QFN
g Temperature range C commercial I industrial A automotive
xxx Peripheral set Three character numeric No meaning is associated with these three characters

Examples

CY8C 5 3 6 8 AX /LT I - x

Cypress Prefix
5 PSoC 5

Architecture
3 CY8C53 Family

Family Group within Architecture
6 67 MHz

Speed Grade
8 256 KB

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY8C5366LTI-053 Datasheet file may be downloaded here without warranties.

Datasheet ID: CY8C5366LTI-053 508169