ADM800LARN

ADM800LARN Datasheet

ADM691A/ADM693A/ADM800L/M

Part	Datasheet
ADM800LARN	ADM800LARN (pdf)

Related Parts	Information
ADM800LARN-REEL	ADM800LARN-REEL

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Microprocessor Supervisory Circuits ADM691A/ADM693A/ADM800L/M FEATURES Low Power Consumption Precision Voltage Monitor Tolerance on ADM800L/M Reset Time ms, or Adjustable 1 Standby Current Automatic Battery Backup Power Switching Fast Onboard Gating of Chip Enable Signals Also Available in TSSOP Package ADM691A APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Automotive Systems Critical Power Monitoring GENERAL DESCRIPTION The ADM691A/ADM693A/ADM800L/ADM800M family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. These functions include µP reset, backup-battery switchover, watchdog timer, CMOS RAM write protection, and power-failure warning. The family of products provides an upgrade for the MAX691A/93A/800M family of products. All parts are available in 16-pin DIP and SO packages. The ADM691A is also available in a space-saving TSSOP package. The following functionality is provided: Power-on reset output during power-up, power-down and brownout conditions. The circuitry remains operational with VCC as low as 1 V. Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic. A reset pulse if the optional watchdog timer has not been toggled within a specified time. A V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than +5 V. FUNCTIONAL BLOCK DIAGRAM BATT ON 4.65V1 VCC VBATT CEIN CHIP ENABLE OUTPUT CONTROL LOW LINE VOUT CEOUT OSC IN OSC SEL RESET & WATCHDOG TIMEBASE RESET & GENERATOR WATCHDOG INPUT WDI POWER FAIL INPUT PFI WATCHDOG TRANSITION DETECTOR WATCHDOG TIMER 1.25V ADM691A/ADM693A ADM800L/ADM800M RESET RESET WATCHDOG OUTPUT WDO POWER FAIL OUTPUT PFO 1VOLTAGE DETECTOR = 4.4V ADM693A/ADM800M INPUT POWER R1 R2 7805 +5V 0.1µF CMOS RAM BATTERY NC VCC VBATT BAT VOUT ON CEOUT ADM691A CEIN ADM693A PFI GND ADM800L ADM800M ORDERING GUIDE Temperature Range to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C Table I. Product Selection Table ADM691A ADM693A ADM800M ADM800L Power On Reset Time 200 ms or Adj. 200 ms or Adj. 200 ms or Adj. 200 ms or Adj. Low VCC Threshold V ± 3% V ± 3% V ± 2% V ± 2% Watchdog Timeout 100 ms, s, Adj. 100 ms, s, Adj. 100 ms, s, Adj. 100 ms, s, Adj. Battery Backup Switching Base Drive Ext PNP Package Option N-16 R-16N R-16W RU-16 N-16 R-16N R-16W N-16 R-16N R-16W N-16 R-16N R-16W Chip Enable Signals Yes ADM691A/ADM693A/ADM800L/M Pin Mnemonic VBATT VOUT 4 GND 5 BATT ON 6 LOW LINE 7 OSC IN 8 OSC SEL 9 PFI 10 PFO 11 WDI CEOUT 13 CEIN 14 WDO 15 RESET 16 RESET PIN DESCRIPTIONS Function Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is not used. Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. When VCC is higher than VBATT and is also higher than the reset threshold, VCC is switched to VOUT. When VCC is lower than VBATT and below the reset threshold, VBATT is switched to VOUT. Connect VOUT to VCC if a backup battery is not being used. Power Supply Input +5 V. 0 V. Ground reference for all signals. Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally switched to VCC. The output may also be used to drive the base via a resistor of an external PNP transistor to increase the output current above the 250 mA rating of VOUT. Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold. Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset delay and the watchdog timeout period. Connecting OSC IN low selects 100 ms while leaving it floating selects sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period. See Table II and Figure Logic Oscillator Select Input. When OSC SEL is unconnected floating or driven high, the internal oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has a 10 µA internal pullup. Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than V, PFO goes low. Connect PFI to GND or VOUT when not used. Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than V. Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply. Output. CEOUT goes low only when CEIN is low and VCC is above the reset threshold. If CEIN is low when reset is asserted, CEOUT will remain low for 15 µs or until CEIN goes high, whichever occurs first. Chip Enable Input. The input to the CE gating circuit. Connect to GND or VOUT if not used. Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the Watchdog timeout period. WDO is set high by the next transition at WDI. WDO remains high if WDI is unconnected. Logic Output. RESET goes low if VCC falls below the Reset Threshold. It remains low for 200 ms typ after VCC goes above the reset threshold. Logic Output. RESET is an open-drain output. It is the inverse of RESET. PIN CONFIGURATIONS VBATT 1 VOUT 2 16 RESET 15 RESET VCC GND BATT ON LOW LINE OSC IN

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Microprocessor Supervisory Circuits

ADM691A/ADM693A/ADM800L/M

FEATURES Low Power Consumption Precision Voltage Monitor Tolerance on ADM800L/M Reset Time ms, or Adjustable 1 Standby Current Automatic Battery Backup Power Switching Fast Onboard Gating of Chip Enable Signals Also Available in TSSOP Package ADM691A

APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Automotive Systems Critical Power Monitoring

GENERAL DESCRIPTION The ADM691A/ADM693A/ADM800L/ADM800M family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. These functions include µP reset, backup-battery switchover, watchdog timer, CMOS RAM write protection, and power-failure warning. The family of products provides an upgrade for the MAX691A/93A/800M family of products.

All parts are available in 16-pin DIP and SO packages. The ADM691A is also available in a space-saving TSSOP package. The following functionality is provided:

Power-on reset output during power-up, power-down and brownout conditions. The circuitry remains operational with VCC as low as 1 V.

Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic.

A reset pulse if the optional watchdog timer has not been toggled within a specified time.

A V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than +5 V.

FUNCTIONAL BLOCK DIAGRAM

BATT ON
4.65V1 VCC

VBATT CEIN

CHIP ENABLE OUTPUT CONTROL

LOW LINE VOUT

CEOUT

OSC IN OSC SEL

RESET & WATCHDOG TIMEBASE

RESET & GENERATOR

WATCHDOG INPUT WDI

POWER FAIL INPUT PFI

WATCHDOG TRANSITION DETECTOR

WATCHDOG TIMER
1.25V

ADM691A/ADM693A ADM800L/ADM800M

RESET

RESET WATCHDOG OUTPUT WDO

POWER FAIL OUTPUT PFO
1VOLTAGE DETECTOR = 4.4V ADM693A/ADM800M

INPUT POWER

R1 R2
7805 +5V
0.1µF

CMOS RAM

BATTERY NC

VCC VBATT

BAT VOUT ON CEOUT

ADM691A CEIN ADM693A

PFI GND

ADM800L ADM800M
ORDERING GUIDE

Temperature Range
to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C to +85°C

Table I. Product Selection Table

ADM691A ADM693A ADM800M ADM800L

Power On Reset Time
200 ms or Adj. 200 ms or Adj. 200 ms or Adj. 200 ms or Adj.

Low VCC Threshold

V ± 3% V ± 3% V ± 2% V ± 2%

Watchdog Timeout
100 ms, s, Adj. 100 ms, s, Adj. 100 ms, s, Adj. 100 ms, s, Adj.

Battery Backup Switching

Base Drive Ext PNP

Package Option N-16 R-16N R-16W RU-16 N-16 R-16N R-16W N-16 R-16N R-16W N-16 R-16N R-16W

Chip Enable Signals Yes

ADM691A/ADM693A/ADM800L/M

Pin Mnemonic

VBATT

VOUT
4 GND
5 BATT ON
6 LOW LINE 7 OSC IN
8 OSC SEL
9 PFI 10 PFO 11 WDI

CEOUT
13 CEIN 14 WDO
15 RESET 16 RESET

PIN DESCRIPTIONS

Function

Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is not used.

Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. When VCC is higher than VBATT and is also higher than the reset threshold, VCC is switched to VOUT. When VCC is lower than VBATT and below the reset threshold, VBATT is switched to VOUT. Connect VOUT to VCC if a backup battery is not being used. Power Supply Input +5 V.
0 V. Ground reference for all signals.

Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally switched to VCC. The output may also be used to drive the base via a resistor of an external PNP transistor to increase the output current above the 250 mA rating of VOUT. Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold. Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset delay and the watchdog timeout period. Connecting OSC IN low selects 100 ms while leaving it floating selects sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period. See Table II and Figure

Logic Oscillator Select Input. When OSC SEL is unconnected floating or driven high, the internal oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has a 10 µA internal pullup. Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than V, PFO goes low. Connect PFI to GND or VOUT when not used. Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than V.

Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply.

Output. CEOUT goes low only when CEIN is low and VCC is above the reset threshold. If CEIN is low when reset is asserted, CEOUT will remain low for 15 µs or until CEIN goes high, whichever occurs first. Chip Enable Input. The input to the CE gating circuit. Connect to GND or VOUT if not used. Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the Watchdog timeout period. WDO is set high by the next transition at WDI. WDO remains high if WDI is unconnected.

Logic Output. RESET goes low if VCC falls below the Reset Threshold. It remains low for 200 ms typ after VCC goes above the reset threshold. Logic Output. RESET is an open-drain output. It is the inverse of RESET.

PIN CONFIGURATIONS

VBATT 1 VOUT 2
16 RESET 15 RESET

VCC GND BATT ON LOW LINE OSC IN

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Datasheet ID: ADM800LARN 517839