CY8C5247AXI-051

CY8C5247AXI-051 Datasheet

5 CY8C52 Family Datasheet

Part	Datasheet
CY8C5247AXI-051	CY8C5247AXI-051 (pdf)

Related Parts	Information
CY8C5246LTI-029	CY8C5246LTI-029
CY8C5248LTI-030	CY8C5248LTI-030
CY8C5247LTI-089	CY8C5247LTI-089
CY8C5248AXI-047	CY8C5248AXI-047

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5 CY8C52 Family Datasheet Programmable System-on-Chip With its unique array of configurable blocks, 5 is a true system-level solution providing microcontroller unit MCU , memory, analog, and digital peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples near DC voltages to ultrasonic signals. The CY8C52 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C52 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C52 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit Cortex -M3 microprocessor core. Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator , a hierarchical schematic design entry tool. The CY8C52 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. 32-bit ARM Cortex-M3 CPU core DC to 40 MHz operation Flash program memory, up to 256 KB, 100,000 write cycles, 20-year retention and multiple security features Up to 64 KB SRAM memory 128 bytes of cache memory 2-KB electrically erasable programmable read-only memory EEPROM memory, 1 million cycles, and 20 years retention 24-channel direct memory access DMA with multilayer AMBA high-performance bus AHB bus access • Programmable chained descriptors and priorities • High bandwidth 32-bit transfer support Low voltage, ultra low power Operating voltage range V to V 6 mA at 6 MHz Low power modes including • 2-µA sleep mode • 300-nA hibernate mode with RAM retention Versatile I/O system 46 to 70 I/Os 60 GPIOs, 8 SIOs, 2 USBIOs Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46 x 16 segments support from any GPIO V to V I/O interface voltages, up to four domains Maskable, independent IRQ on any pin or port Schmitt trigger transistor-transistor logic TTL inputs All GPIOs configurable as open drain high/low, pull up/down, High-Z, or strong output 25 mA sink on SIO Digital peripherals 20 to 24 programmable logic device PLD based universal digital blocks UDBs Full-Speed FS USB 12 Mbps using a 24 MHz external oscillator Four 16-bit configurable timer, counter, and PWM blocks Library of standard peripherals • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs • SPI, UART, and I2C • Many others available in catalog Library of advanced peripherals • Cyclic redundancy check CRC • Pseudo random sequence PRS generator • Local interconnect network LIN bus • Quadrature decoder Analog peripherals V VDDA V ±1% internal voltage reference Successive approximation register SAR analog-to-digital converter ADC , 12-bit at 700 ksps One 8-bit, 5.5-Msps current DAC IDAC or 1-Msps voltage DAC VDAC Two comparators with 95-ns response time CapSense support Programming, debug, and trace Serial wire debug SWD and single-wire viewer SWV interfaces Cortex-M3 flash patch and breakpoint FPB block Cortex-M3 data watchpoint and trace DWT generates data trace information Cortex-M3 Instrumentation Trace Macrocell ITM can be used for printf-style debugging DWT and ITM blocks communicate with off-chip debug and trace systems via the SWV interface Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces Precision, programmable clocking 3 to 24 MHz internal oscillator over full temperature and voltage range 4 to 25 MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 40 MHz kHz watch crystal oscillator Low power internal oscillator at 1, 33, and 100 kHz Temperature and packaging °C to +85 °C degrees industrial temperature 68-pin QFN and 100-pin TQFP package options • 198 Champion Court San Jose, CA 95134-1709 408-943-2600 5 CY8C52 Family Datasheet Contents Architectural Overview 3 Pinouts 5 Pin Descriptions 8 CPU 9 ARM Cortex-M3 CPU Cache Controller DMA and PHUB Interrupt Controller Memory 16 Static RAM Flash Program Memory Flash Security EEPROM Memory Map System Integration 18 Clocking System Power System Reset I/O System and Routing Digital Subsystem 32 Example Peripherals Universal Digital Block UDB Array Description DSI Routing Interface Description USB Timers, Counters, and PWMs I2C Analog Subsystem 43 Analog Routing Successive Approximation ADC Comparators LCD Direct Drive CapSense Temp Sensor DAC Programming, Debug Interfaces, Resources 49 Debug Port Acquisition SWD Interface Debug Features Trace Features SWV Interface Programming Features Device Security Development Support 52 Documentation Online Tools Electrical Specifications 53 Absolute Maximum Ratings Device Level Specifications Power Regulators Inputs and Outputs Analog Peripherals Digital Peripherals Memory PSoC System Resources Clocking Ordering Information 89 Part Numbering Conventions Packaging 90 Acronyms 92 Reference Documents 93 Document Conventions 94 Units of Measure Sales, Solutions, and Legal Information 97 Page 2 of 97 5 CY8C52 Family Datasheet Architectural Overview Introducing the CY8C52 family of ultra low power, flash Programmable System-on-Chip PSoC devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C52 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure Simplified Block Diagram 4 to 25 MHz Optional KHz Optional SIOs GPIOs GPIOs GPIOs System Wide Resources Xtal Osc RTC Timer WDT and Wake Clocking System Power Management System POR and LVD Sleep Power V LDO Clock Tree Usage Example for UDB Sequencer Digital Interconnect Analog Interconnect Digital System Universal Digital Block Array 24 x UDB 8- Bit Quadrature Decoder Timer 16 -Bit PWM 16- Bit PRS UDB UDB I 2C Slave UDB 8- Bit SPI UDB UART UDB 12- Bit SPI UDB 8- Bit Timer Logic Logic UDB 12- Bit PWM Ordering Information In addition to the features listed in Table 12-1, every CY8C52 device includes up to 256 KB flash, 64 KB SRAM, 2 KB EEPROM, a precision on-chip voltage reference, precision oscillators, flash, DMA, a fixed function I2C, SWD programming and debug, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C52 derivatives incorporate device and flash security in user-selectable security levels see the TRM for details. Table CY8C52 Family with ARM Cortex-M3 CPU MCU Core Analog Digital I/O[46] Package Device ID[47] CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive ADC DAC Comparators SC/CT Analog Blocks Opamps DFB CapSense UDBs[45] 16-bit Timer/PWM FS USB Total I/O GPIO SIO USBIO CY8C5248LTI-030 40 256 64 2 1x12-bit SAR 1 2 24 4 46 36 8 2 68-pin QFN 0x0E11E069 CY8C5248AXI-047 40 256 64 2 1x12-bit SAR 1 2 24 4 70 60 8 2 100-pin TQFP 0x0E12F069 CY8C5247LTI-089 40 128 32 2 1x12-bit SAR 1 2 24 4 46 36 8 2 68-pin QFN 0x0E159069 CY8C5247AXI-051 40 128 32 2 1x12-bit SAR 1 2 24 4 70 60 8 2 100-pin TQFP 0x0E133069 CY8C5246LTI-029 40 64 16 2 1x12-bit SAR 1 2 24 4 46 36 8 2 68-pin QFN 0x0E11D069 CY8C5246AXI-054 40 64 16 2 1x12-bit SAR 1 2 24 4 70 60 8 2 100-pin TQFP 0x0E136069 Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric 0, 1, 2, 9, A, B, Z unless stated otherwise. CY8Cabcdefg-xxx a Architecture 3 PSoC 3 5 PSoC 5 b Family group within architecture 2 CY8C52 family 3 CY8C53 family 4 CY8C54 family 5 CY8C55 family ef Package code Two character alphanumeric AX TQFP LT QFN g Temperature range C commercial I industrial A automotive c Speed grade 4 40 MHz 6 67 MHz xxx Peripheral set Three character numeric No meaning is associated with these three characters d Flash capacity 5 32 KB 6 64 KB 7 128 KB 8 256 KB Notes UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 32 for more information on how UDBs can be used. The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 25 for details on the functionality of each of these types of I/O. The device ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID. Page 89 of 97 5 CY8C52 Family Datasheet Examples CY8C 5 2 4 8 AX /LT I - x Cypress Prefix 5 PSoC 5 Architecture 2 CY8C52 Family Family Group within Architecture 4 40 MHz Speed Grade 8 256 KB Flash Capacity AX TQFP, LT QFN Package Code

PDF Datasheet Preview

5 CY8C52 Family Datasheet

Programmable System-on-Chip

With its unique array of configurable blocks, 5 is a true system-level solution providing microcontroller unit MCU , memory, analog, and digital peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples near DC voltages to ultrasonic signals. The CY8C52 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C52 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C52 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit Cortex -M3 microprocessor core. Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator , a hierarchical schematic design entry tool. The CY8C52 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
32-bit ARM Cortex-M3 CPU core DC to 40 MHz operation Flash program memory, up to 256 KB, 100,000 write cycles, 20-year retention and multiple security features Up to 64 KB SRAM memory 128 bytes of cache memory 2-KB electrically erasable programmable read-only memory EEPROM memory, 1 million cycles, and 20 years retention 24-channel direct memory access DMA with multilayer AMBA high-performance bus AHB bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support

Low voltage, ultra low power Operating voltage range V to V 6 mA at 6 MHz Low power modes including
• 2-µA sleep mode
• 300-nA hibernate mode with RAM retention

Versatile I/O system 46 to 70 I/Os 60 GPIOs, 8 SIOs, 2 USBIOs Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46 x 16 segments support from any GPIO V to V I/O interface voltages, up to four domains Maskable, independent IRQ on any pin or port Schmitt trigger transistor-transistor logic TTL inputs All GPIOs configurable as open drain high/low, pull up/down, High-Z, or strong output 25 mA sink on SIO

Digital peripherals 20 to 24 programmable logic device PLD based universal digital blocks UDBs Full-Speed FS USB 12 Mbps using a 24 MHz external oscillator Four 16-bit configurable timer, counter, and PWM blocks

Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• SPI, UART, and I2C
• Many others available in catalog

Library of advanced peripherals
• Cyclic redundancy check CRC
• Pseudo random sequence PRS generator
• Local interconnect network LIN bus
• Quadrature decoder

Analog peripherals V VDDA V ±1% internal voltage reference Successive approximation register SAR analog-to-digital converter ADC , 12-bit at 700 ksps One 8-bit, 5.5-Msps current DAC IDAC or 1-Msps voltage DAC VDAC Two comparators with 95-ns response time CapSense support

Programming, debug, and trace

Serial wire debug SWD and single-wire viewer SWV interfaces

Cortex-M3 flash patch and breakpoint FPB block Cortex-M3 data watchpoint and trace DWT generates data
trace information Cortex-M3 Instrumentation Trace Macrocell ITM can be
used for printf-style debugging DWT and ITM blocks communicate with off-chip debug and
trace systems via the SWV interface Bootloader programming supportable through I2C, SPI,

UART, USB, and other interfaces Precision, programmable clocking
3 to 24 MHz internal oscillator over full temperature and voltage range
4 to 25 MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 40 MHz kHz watch crystal oscillator Low power internal oscillator at 1, 33, and 100 kHz

Temperature and packaging °C to +85 °C degrees industrial temperature 68-pin QFN and 100-pin TQFP package options
• 198 Champion Court

San Jose, CA 95134-1709
408-943-2600
5 CY8C52 Family Datasheet

Contents

Architectural Overview 3

Pinouts 5

Pin Descriptions 8

CPU 9 ARM Cortex-M3 CPU Cache Controller DMA and PHUB Interrupt Controller

Memory 16 Static RAM Flash Program Memory Flash Security EEPROM Memory Map

System Integration 18 Clocking System Power System Reset I/O System and Routing

Digital Subsystem 32 Example Peripherals Universal Digital Block UDB Array Description DSI Routing Interface Description USB Timers, Counters, and PWMs I2C

Analog Subsystem 43 Analog Routing Successive Approximation ADC Comparators LCD Direct Drive CapSense Temp Sensor DAC

Programming, Debug Interfaces, Resources 49 Debug Port Acquisition SWD Interface Debug Features Trace Features SWV Interface Programming Features Device Security

Development Support 52 Documentation Online Tools

Electrical Specifications 53 Absolute Maximum Ratings Device Level Specifications Power Regulators Inputs and Outputs Analog Peripherals Digital Peripherals Memory PSoC System Resources Clocking
Ordering Information 89 Part Numbering Conventions

Packaging 90

Acronyms 92

Reference Documents 93

Document Conventions 94 Units of Measure

Sales, Solutions, and Legal Information 97

Page 2 of 97
5 CY8C52 Family Datasheet

Architectural Overview

Introducing the CY8C52 family of ultra low power, flash Programmable System-on-Chip PSoC devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C52 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure Simplified Block Diagram
4 to 25 MHz Optional

KHz Optional

SIOs

GPIOs

GPIOs

GPIOs

System Wide Resources

Xtal Osc

RTC Timer

WDT and Wake

Clocking System

Power Management System

POR and LVD Sleep Power

V LDO

Clock Tree Usage Example for UDB

Sequencer

Digital Interconnect

Analog Interconnect

Digital System

Universal Digital Block Array 24 x UDB
8- Bit Quadrature Decoder Timer
16 -Bit PWM
16- Bit PRS UDB

UDB I 2C Slave

UDB 8- Bit SPI

UDB UART

UDB 12- Bit SPI

UDB 8- Bit Timer Logic

Logic UDB
12- Bit PWM
Ordering Information

In addition to the features listed in Table 12-1, every CY8C52 device includes up to 256 KB flash, 64 KB SRAM, 2 KB EEPROM, a precision on-chip voltage reference, precision oscillators, flash, DMA, a fixed function I2C, SWD programming and debug, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C52
derivatives incorporate device and flash security in user-selectable security levels see the TRM for details.

Table CY8C52 Family with ARM Cortex-M3 CPU

MCU Core

Analog

Digital

I/O[46]

Package

Device ID[47]

CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive ADC DAC Comparators SC/CT Analog Blocks Opamps DFB CapSense UDBs[45] 16-bit Timer/PWM FS USB Total I/O GPIO SIO USBIO

CY8C5248LTI-030 40 256 64 2 1x12-bit SAR 1 2 24 4 46 36 8 2 68-pin QFN 0x0E11E069 CY8C5248AXI-047 40 256 64 2 1x12-bit SAR 1 2 24 4 70 60 8 2 100-pin TQFP 0x0E12F069 CY8C5247LTI-089 40 128 32 2 1x12-bit SAR 1 2 24 4 46 36 8 2 68-pin QFN 0x0E159069 CY8C5247AXI-051 40 128 32 2 1x12-bit SAR 1 2 24 4 70 60 8 2 100-pin TQFP 0x0E133069 CY8C5246LTI-029 40 64 16 2 1x12-bit SAR 1 2 24 4 46 36 8 2 68-pin QFN 0x0E11D069 CY8C5246AXI-054 40 64 16 2 1x12-bit SAR 1 2 24 4 70 60 8 2 100-pin TQFP 0x0E136069

Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric 0, 1, 2, 9, A, B, Z unless stated otherwise. CY8Cabcdefg-xxx
a Architecture 3 PSoC 3 5 PSoC 5
b Family group within architecture 2 CY8C52 family 3 CY8C53 family 4 CY8C54 family 5 CY8C55 family
ef Package code Two character alphanumeric AX TQFP LT QFN
g Temperature range C commercial I industrial A automotive
c Speed grade
4 40 MHz 6 67 MHz
xxx Peripheral set

Three character numeric No meaning is associated with these three characters
d Flash capacity
5 32 KB 6 64 KB 7 128 KB 8 256 KB

Notes UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 32 for more information on how UDBs can be used. The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 25 for details on the functionality of each of
these types of I/O. The device ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.

Page 89 of 97
5 CY8C52 Family Datasheet

Examples

CY8C 5 2 4 8 AX /LT I - x

Cypress Prefix
5 PSoC 5

Architecture
2 CY8C52 Family

Family Group within Architecture
4 40 MHz

Speed Grade
8 256 KB

Flash Capacity

AX TQFP, LT QFN

Package Code

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Datasheet ID: CY8C5247AXI-051 508168