CY8C3665LTI-006

CY8C3665LTI-006 Datasheet


PRELIMINARY 3 CY8C36 Family Datasheet

Part Datasheet
CY8C3665LTI-006 CY8C3665LTI-006 CY8C3665LTI-006 (pdf)
Related Parts Information
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CY8C3665LTI-043 CY8C3665LTI-043 CY8C3665LTI-043
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CY8C3665LTI-004 CY8C3665LTI-004 CY8C3665LTI-004
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CY8C3665LTI-001 CY8C3665LTI-001 CY8C3665LTI-001
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CY8C3665AXI-013 CY8C3665AXI-013 CY8C3665AXI-013
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CY8C3666PVI-026 CY8C3666PVI-026 CY8C3666PVI-026
CY8C3666PVI-057 CY8C3666PVI-057 CY8C3666PVI-057
CY8C3666LTI-012 CY8C3666LTI-012 CY8C3666LTI-012
CY8C3665LTI-002 CY8C3665LTI-002 CY8C3665LTI-002
CY8C3665PVI-080 CY8C3665PVI-080 CY8C3665PVI-080
CY8C3666LTI-011 CY8C3666LTI-011 CY8C3666LTI-011
CY8C3666LTI-028 CY8C3666LTI-028 CY8C3666LTI-028
CY8C3666LTI-025 CY8C3666LTI-025 CY8C3666LTI-025
CY8C3666AXI-031 CY8C3666AXI-031 CY8C3666AXI-031
CY8C3666AXI-034 CY8C3666AXI-034 CY8C3666AXI-034
CY8C3665PVI-049 CY8C3665PVI-049 CY8C3665PVI-049
CY8C3665PVI-007 CY8C3665PVI-007 CY8C3665PVI-007
CY8C3666PVI-041 CY8C3666PVI-041 CY8C3666PVI-041
CY8C3666LTI-042 CY8C3666LTI-042 CY8C3666LTI-042
CY8C3665AXI-016 CY8C3665AXI-016 CY8C3665AXI-016
CY8C3665AXI-010 CY8C3665AXI-010 CY8C3665AXI-010
CY8C3665AXI-010T CY8C3665AXI-010T CY8C3665AXI-010T
CY8C3665AXI-016T CY8C3665AXI-016T CY8C3665AXI-016T
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PRELIMINARY 3 CY8C36 Family Datasheet

Programmable System-on-Chip

With its unique array of configurable blocks, 3 is a true system level solution providing microcontroller unit MCU , memory, analog, and digital peripheral functions in a single chip. The CY8C36 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples near DC voltages to ultrasonic signals. The CY8C36 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output GPIO pin. The CY8C36 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multi-master inter-integrated circuit I2C , and controller area network CAN . In addition to communication interfaces, the CY8C36 family has an easy to configure logic array, flexible routing to all I/O pins, andcurrent DAC a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator , a hierarchical schematic design entry tool. The CY8C36 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
- Single cycle 8051 CPU core DC to 67 MHz operation Multiply and divide instructions Flash program memory, up to 64 KB, 100,000 write cycles, 20 years retention, and multiple security features Up to 8-KB flash error correcting code ECC or configuration storage Up to 8 KB SRAM Up to 2 KB electrically erasable programmable read-only memory EEPROM , 1 M cycles, and 20 years retention 24-channel direct memory access DMA with multilayer AHB[1] bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
- Low voltage, ultra low-power Wide operating voltage range V to V High efficiency boost regulator from 0.5-V input through 1.8-V to 5.0-V output mA at 3 MHz, mA at 6 MHz, mA at 48 MHz Low-power modes including
• 1-µA sleep mode with real-time clock RTC and low-voltage detect LVD interrupt
• 200-nA hibernate mode with RAM retention
- Versatile I/O system 28 to 72 I/O 62 GPIOs, eight special input/outputs SIO , two USBIOs[2] Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46 x 16 segments[2] support from any GPIO[3] 1.2-V to 5.5-V I/O interface voltages, up to four domains Maskable, independent interrupt request IRQ on any pin or port Schmitt-trigger transistor-transistor logic TTL inputs All GPIO configurable as open drain high/low, pull-up/pull-down, High Z, or strong output Configurable GPIO pin state at power-on reset POR 25 mA sink on SIO
- Digital peripherals 20 to 24 programmable logic devices PLD based universal digital blocks UDB Full CAN 2.0b 16-receive Rx , 8-transmit Tx buffers[2] Full-Speed FS USB 12 Mbps using internal oscillator[2] Up to four 16-bit configurable timer, counter, and PWM blocks

Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface SPI , universal asynchronous transmitter receiver UART , I2C
• Many others available in catalog

Library of advanced peripherals
• Cyclic redundancy check CRC
• Pseudo random sequence PRS generator
• Local interconnect network LIN bus
• Quadrature decoder
- Analog peripherals V VDDA V ± internal voltage reference across °C to +85 °C 14 ppm/°C Configurable delta-sigma ADC with 8- to12-bit resolution
• Programmable gain stage to x16
• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion ratio SINAD , ±1-bit INL/DNL 67-MHz, 24-bit fixed point digital filter block DFB to implement finite impulse response FIR and infinite impulse response IIR filters Up to four 8-bit, 8-Msps IDACs or 1-Msps VDACs Four comparators with 95-ns response time Up to four uncommitted opamps with 25 mA drive capability Up to four configurable multifunction analog blocks. Example configurations are programmable gain amplifier PGA , transimpedance amplifier TIA , mixer, and sample and hold CapSense support
- Programming, debug, and trace JTAG 4-wire , serial wire debug SWD 2-wire , and single wire viewer SWV interfaces Eight address and one data breakpoint 4-KB instruction trace buffer Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces
- Precision, programmable clocking 3- to 62-MHz internal oscillator over full temperature and voltage range 4- to 33-MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 67 MHz kHz watch crystal oscillator Low-power internal oscillator at 1, 33, and 100 kHz
- Temperature and packaging °C to +85 °C degrees industrial temperature 48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP package options
Notes AHB AMBA advanced microcontroller bus architecture high-performance bus, an ARM data transfer bus This feature on select devices only. See Ordering Information on page 99 for details. GPIOs with opamp outputs are not recommended for use with CapSense.
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, San Jose CA 95134-1709
408-943-2600
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PRELIMINARY 3 CY8C36 Family Datasheet

Contents

ARCHITECTURAL OVERVIEW 3

PINOUTS 5

PIN DESCRIPTIONS 10

CPU 11 8051 CPU 11 Addressing Modes 11 Instruction Set 11 DMA and PHUB 15 Interrupt Controller 17

MEMORY 18 Static RAM 18 Flash Program Memory 18 Flash Security 18 EEPROM 18 External Memory Interface 18 Memory Map 19

SYSTEM INTEGRATION 21 Clocking System 21 Power System 24 Reset 27 I/O System and Routing 28

DIGITAL SUBSYSTEM 34 Example Peripherals 35 Universal Digital Block 38 UDB Array Description 41 DSI Routing Interface Description 41 CAN 43 USB 44 Timers, Counters, and PWMs 45 I2C 45 Digital Filter Block 45

ANALOG SUBSYSTEM 46 Analog Routing 47 Delta-sigma ADC 49 Comparators 50 Opamps 51 Programmable SC/CT Blocks 51 LCD Direct Drive 52

CapSense 53 Temp Sensor 53 DAC 53 Up/Down Mixer 54 Sample and Hold 54

PROGRAMMING, DEBUG INTERFACES, RESOURCES 55 JTAG Interface 55 Serial Wire Debug Interface 55 Debug Features 55 Trace Features 56 Single Wire Viewer Interface 56 Programming Features 56 Device Security 56

DEVELOPMENT SUPPORT 57 Documentation 57 Online 57 Tools 57

ELECTRICAL SPECIFICATIONS 58 Absolute Maximum Ratings 58 Device Level Specifications 59 Power Regulators 62 Inputs and Outputs 64 Analog Peripherals 68 Digital Peripherals 82 Memory 85 PSoC System Resources 91 Clocking 93
ORDERING INFORMATION 96 Part Numbering Conventions 98

PACKAGING 99

ACRONYMS 102

REFERENCE DOCUMENTS 103

DOCUMENT CONVENTIONS 104 Units of Measure 104

SALES, SOLUTIONS, AND LEGAL INFORMATION 108

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PRELIMINARY 3 CY8C36 Family Datasheet

Architectural Overview

Introducing the CY8C36 family of ultra low-power, flash Programmable System-on-Chip devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C36 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure Simplified Block Diagram
4- 33 MHz Optiona l

KHz Optiona l

GPIOs

SIOs

GPIOs

GPIOs

SYSTEM WIDE RESOURCES

Xtal Osc

RTC Timer

WDT and Wake

Clocking System

Power Management System

POR and LVD Sleep Power
1.8V LDO SMP

Clock Tree

Usage Example for UDB Sequencer

Digital Interconnect

Analog Interconnect

DIGITAL SYSTEM

Universal Digital Block Array 24 x UDB
8- Bit Quadrature Decoder Timer
16- Bit 16- Bit PRS PWM

UDB I2C Slave

UDB UART

UDB 8- Bit SPI

UDB 12- Bit SPI

UDB 8- Bit Timer

Logic

Logic UDB
Notes This feature on select devices only. See Ordering Information on page 99 for details. GPIOs with opamp outputs are not recommended for use with CapSense.

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PRELIMINARY 3 CY8C36 Family Datasheet

Figure 48-pin QFN Part Pinout[7]
48 P2[5] GPIO 47 Vddio2 46 P2[4] GPIO 45 P2[3] GPIO 44 Vddd 43 Vssd 42 Vccd 41 P0[7] IDAC2, GPIO 40 P0[6] IDAC0, GPIO 39 P0[5] OpAmp2-, GPIO 38 P0[4] OpAmp2+, GPIO 37 Vddio0

GPIO P2[6] 1 GPIO P2[7] 2

Vssb 3 Ind 4

Vboost 5 Vbat 6

GPIO, TMS, SWDIO P1[0] 7 GPIO, TCK, SWDCK P1[1] 8 GPIO, Configurable XRES P1[2] 9

GPIO, TDO, SWV P1[3] 10 GPIO, TDI P1[4] 11

GPIO, nTRST P1[5] 12

Lines show Vddio to I/O supply association

Top View
36 P0[3] OpAmp0-/Extref0, GPIO 35 P0[2] OpAmp0+, GPIO
34 P0[1] OpAmp0out, GPIO 33 P0[0] OpAmp2out, GPIO 32 P12[3] SIO 31 P12[2] SIO
30 Vdda 29 Vssa 28 Vcca 27 P15[3] GPIO, kHz XTAL Xi 26 P15[2] GPIO, kHz XTAL Xo 25 P12[1] SIO, I2C1 SDA

SIO, I2C1 SCL P12[0] 24

Vddio3 23

GPIO, MHz XTAL Xi P15[1] 22

GPIO, MHz XTAL Xo P15[0] 21

Vssd 19 Vccd 20
[6] USBIO, D-, SWDCK P15[7] 17 Vddd 18

USBIO, D+, SWDIO P15[6] 16

GPIO P1[7] 15

GPIO P1[6] 14

Vddio1 13

Notes

Pins are Do Not Use DNU on devices without USB. The pin must be left floating.

The center pad on the QFN package should be connected to digital ground Vssd for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.

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PRELIMINARY 3 CY8C36 Family Datasheet

Figure 68-pin QFN Part Pinout[10]
68 P2[5] GPIO 67 Vddio2 66 P2[4] GPIO 65 P2[3] GPIO 64 P2[2] GPIO 63 P2[1] GPIO 62 P2[0] GPIO 61 P15[5] GPOI 60 P15[4] GPIO 59 Vddd 58 Vssd 57 Vccd 56 P0[7] GPIO, IDAC2 55 P0[6] GPIO, IDAC0 54 P0[5] GPIO, OpAmp2- 53 P0[4] GPIO, OpAmp2+ 52 Vddio0

GPIO P2[6] 1 GPIO P2[7] 2 I2C0 SCL, SIO P12[4] 3 I2C0 SDA, SIO P12[5] 4

Vssb 5 Ind 6

Vboost 7 Vbat 8 Vssd 9

XRES 10 TMS, SWDIO, GPIO P1[0] 11 TCK, SWDCK, GPIO P1[1] 12 configurable XRES, GPIO P1[2] 13

TDO, SWV, GPIO P1[3] 14 TDI, GPIO P1[4] 15
nTRST, GPIO P1[5] 16 Vddio1 17
Notes Pins are Do Not Use DNU on devices without USB. The pin must be left floating. This feature on select devices only. See Ordering Information on page 99 for details. The center pad on the QFN package should be connected to digital ground Vssd for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.

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PRELIMINARY 3 CY8C36 Family Datasheet

Figure 100-pin TQFP Part Pinout
100 Vddio2 99 P2[4] GPIO 98 P2[3] GPIO 97 P2[2] GPIO 96 P2[1] GPIO 95 P2[0] GPIO 94 P15[5] GPIO 93 P15[4] GPIO 92 P6[3] GPIO 91 P6[2] GPIO 90 P6[1] GPIO 89 P6[0] GPIO 88 Vddd 87 Vssd 86 Vccd 85 P4[7] GPIO 84 P4[6] GPIO 83 P4[5] GPIO 82 P4[4] GPIO 81 P4[3] GPIO 80 P4[2] GPIO 79 P0[7] GPIO, IDAC2 78 P0[6] GPIO, IDAC0 77 P0[5] GPIO, OpAmp2- 76 P0[4] GPIO, OpAmp2+

GPIO P2[5] 1 GPIO P2[6] 2 GPIO P2[7] 3 I2C0 SCL, SIO P12[4] 4 I2C0 SDA, SIO P12[5] 5 GPIO P6[4] 6 GPIO P6[5] 7 GPIO P6[6] 8 GPIO P6[7] 9

Vssb 10 Ind 11

Vboost 12 Vbat 13

Vssd 14 XRES 15 GPIO P5[0] 16 GPIO P5[1] 17 GPIO P5[2] 18 GPIO P5[3] 19 TMS, SWDIO, GPIO P1[0] 20

TCK, SWDCK, GPIO P1[1] 21
configurable XRES, GPIO P1[2] 22 TDO, SWV, GPIO P1[3] 23

TDI, GPIO P1[4] 24 nTRST, GPIO P1[5] 25

Lines show Vddio to I/O supply association

TQFP
75 Vddio0 74 P0[3] GPIO, OpAmp0-/Extref0
73 P0[2] GPIO, OpAmp0+ 72 P0[1] GPIO, OpAmp0out 71 P0[0] GPIO, OpAmp2out 70 P4[1] GPIO
69 P4[0] GPIO
68 P12[3] SIO 67 P12[2] SIO 66 Vssd
65 Vdda 64 Vssa
63 Vcca
62 NC
61 NC 60 NC
59 NC
58 NC 57 NC 56 P15[3] GPIO, kHz XTAL Xi 55 P15[2] GPIO, kHz XTAL Xo
54 P12[1] SIO, I2C1 SDA
53 P12[0] SIO, I2C1 SCL
[12]
52 P3[7] GPIO, OpAmp3out
[12]
51 P3[6] GPIO, OpAmp1out

Vddio3 50
[12] OpAmp1+, GPIO P3[5] 49

OpAmp1-, GPIO P3[4] 48
46 47

P3[2] P3[3]

GPIO

IDAC1, GPIO P3[0] 44 IDAC3, GPIO P3[1] 45

MHz XTAL Xi, GPIO P15[1] 43

MHz XTAL Xo, GPIO P15[0] 42
Notes Pins are Do Not Use DNU on devices without USB. The pin must be left floating. This feature on select devices only. See Ordering Information on page 99 for details. The center pad on the QFN package should be connected to digital ground Vssd for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.

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PRELIMINARY 3 CY8C36 Family Datasheet

Figure Example Schematic for 100-pin TQFP Part With Power Connections

Vddd

Vddd

Vddd

C6 uF Vssd
100 Vddd 99 98 97 96 95 94 93 92 91 90 89 88 Vddd 87 Vssd 86 85 84 83 82 81 80 79 78 77 76

C1 1 uF

Vssd

C2 uF

Vccd

Vssd

U2 CY8C55xx

Vddio2 P2[4] P2[3] P2[2] P2[1] P2[0]

P15[5] P15[4]

P6[3] P6[2] P6[1] P6[0] Vddd Vssd Vccd P4[7] P4[6] P4[5] P4[4] P4[3] P4[2] IDAC2, P0[7] IDAC0, P0[6] OA2-, P0[5] OA2+, P0[4]

Vssd
1 2 3 4 5 6 7 8 9 10 11 12 13 Vssd 14 15 16 17 18 19 20 21 22 23 24 25

P2[5] P2[6] P2[7] P12[4], SIO P12[5], SIO P6[4] P6[5] P6[6] P6[7] Vssb Ind Vboost Vbat Vssd XRES P5[0] P5[1] P5[2] P5[3] P1[0], SWIO, TMS P1[1], SWDIO, TCK P1[2] P1[3], SWV, TDO P1[4], TDI P1[5], nTRST

Vddio0 OA0-, REF0, P0[3]

OA0+, P0[2] OA0out, P0[1] OA2out, P0[0]

P4[1] P4[0] SIO, P12[3] SIO, P12[2] Vssd Vdda Vssa Vcca

NC kHzXin, P15[3] kHzXout, P15[2] SIO, P12[1] SIO, P12[0] OA3out, P3[7] OA1out, P3[6]
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

Vddd

Vdda

C8 uF

C17 1 uF

Vssd

Vssd Vdda Vssa Vcca

Vssa Vssd

Vdda

C9 1 uF

C10 uF

Vssa

Vddio1 P1[6] P1[7] P12[6], SIO P12[7], SIO P5[4] P5[5] P5[6] P5[7] USB D+, P15[6] USB D-, P15[7] Vddd Vssd Vccd NC P15[0], MHzXout P15[1], MHzXin P3[0], IDAC1 P3[1], IDAC3 P3[2], OA3-, REF1 P3[3], OA3+ P3[4], OA1P3[5], OA1+ Vddio3
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 P32 47 48 49 50
Notes GPIOs with opamp outputs are not recommended for use with CapSense. This feature on select devices only. See Ordering Information on page 99 for details.

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Vccd. Output of digital core regulator and input to digital core. The two Vccd pins must be shorted together, with the trace between them as short as possible, and a 1-µF capacitor to Vssd see Power System on page Regulator output not for external use.

Vdda. Supply for all analog peripherals and analog core regulator. Vdda must be the highest voltage present on the device. All other supply pins must be less than or equal to Vdda.

Vddd. Supply for all digital peripherals and digital core regulator. VDDD must be less than or equal to Vdda. Vssa. Ground for all analog peripherals.

Vssb. Ground connection for boost pump.

Vssd. Ground for all digital logic and I/O pins.

Vddio0, Vddio1, Vddio2, Vddio3. Supply for I/O pins. See pinouts for specific I/O pin to Vddio mapping. Each Vddio must be tied to a valid operating voltage V to V , and must be less than or equal to Vdda. If the I/O pins associated with Vddio0, Vddio2 or Vddio3 are not used then that Vddio should be tied to ground Vssd or Vssa .

XRES and configurable XRES . External reset pin. Active low with internal pull-up. In 48-pin SSOP parts and 48-pin QFN parts, P1[2] may be configured as XRES. In all other parts the pin is configured as a GPIO.
8051 CPU

The CY8C36 devices use a single cycle 8051 CPU, which is fully compatible with the original MCS-51 instruction set. The CY8C36 family uses a pipelined RISC architecture, which executes most instructions in 1 to 2 cycles to provide peak performance of up to 33 MIPS with an average of 2 cycles per instruction. The single cycle 8051 CPU runs ten times faster than a standard 8051 processor.

The 8051 CPU subsystem includes these features:
- Single cycle 8051 CPU
- Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up to 8 KB of SRAM
- Programmable nested vector interrupt controller
- DMA controller
- Peripheral HUB PHUB
- External memory interface EMIF

Addressing Modes

The following addressing modes are supported by the 8051:
- Direct addressing The operand is specified by a direct 8-bit address field. Only the internal RAM and the SFRs can be accessed using this mode.
- Indirect addressing The instruction specifies the register which contains the address of the operand. The registers R0 or R1 are used to specify the 8-bit address, while the data pointer DPTR register is used to specify the 16-bit address.
- Register addressing Certain instructions access one of the registers R0 to R7 in the specified register bank. These instructions are more efficient because there is no need for an address field.
- Register specific instructions Some instructions are specific to certain registers. For example, some instructions always act on the accumulator. In this case, there is no need to specify the operand.
- Immediate constants Some instructions carry the value of the constants directly instead of an address.
- Indexed addressing This type of addressing can be used only for a read of the program memory. This mode uses the Data Pointer as the base and the accumulator value as an offset to read a program memory.
- Bit addressing In this mode, the operand is one of 256 bits.

Instruction Set

The 8051 instruction set is highly optimized for 8-bit handling and Boolean operations. The types of instructions supported include:
- Arithmetic instructions
- Logical instructions
- Data transfer instructions
- Boolean instructions
- Program branching instructions

Instruction Set Summary

Arithmetic Instructions

Arithmetic instructions support the direct, indirect, register, immediate constant, and register-specific instructions. Arithmetic modes are used for addition, subtraction, multiplication, division, increment, and decrement operations. Table 4-1 on page 12 lists the different arithmetic instructions.

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Ordering Information

In addition to the features listed in Table 12-1, every CY8C36 device includes a precision on-chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I2C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C36 derivatives incorporate device and flash security in user-selectable security levels see the TRM for details.

Table CY8C36 Family with Single Cycle 8051

MCU Core

Analog

Digital

I/O[62]

Package

JTAG ID[63]

CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive ADC DAC Comparator SC/CT Analog Blocks[60] Opamps DFB CapSense UDBs[61] 16-bit Timer/PWM FS USB CAN 2.0b Total I/O GPIO SIO USBIO
32 KB Flash CY8C3665AXI-010 67 32 4 1 CY8C3665LTI-009 67 32 4 1 CY8C3665LTI-001 67 32 4 1 CY8C3665PVI-008 67 32 4 1 CY8C3665AXI-016 67 32 4 1 CY8C3665LTI-044 67 32 4 1 CY8C3665LTI-004 67 32 4 1 CY8C3665PVI-049 67 32 4 1 CY8C3665AXI-013 67 32 4 1 CY8C3665LTI-043 67 32 4 1 CY8C3665LTI-002 67 32 4 1 CY8C3665PVI-003 67 32 4 1 CY8C3665AXI-017 67 32 4 1 CY8C3665LTI-048 67 32 4 1 CY8C3665LTI-006 67 32 4 1 CY8C3665PVI-007 67 32 4 1 CY8C3665PVI-080 67 32 4 1 64 KB Flash CY8C3666AXI-052 67 64 8 2 CY8C3666LTI-042 67 64 8 2 CY8C3666LTI-011 67 64 8 2 CY8C3666PVI-041 67 64 8 2 CY8C3666AXI-034 67 64 8 2 CY8C3666LTI-025 67 64 8 2 CY8C3666LTI-046 67 64 8 2 CY8C3666PVI-022 67 64 8 2 CY8C3666AXI-031 67 64 8 2 CY8C3666LTI-028 67 64 8 2
12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4
12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4
4 20 4 70 62 8 0 100-pin TQFP 0x0E00A069 4 20 4 46 38 8 0 68-pin QFN 0x0E009069 2 20 4 29 25 4 0 48-pin QFN 0x0E001069 2 20 4 29 25 4 0 48-pin SSOP 0x0E008069 4 20 4 72 62 8 2 100-pin TQFP 0x0E010069 4 20 4 48 38 8 2 68-pin QFN 0x0E02C069 2 20 4 31 25 4 2 48-pin QFN 0x0E004069 2 20 4 31 25 4 2 48-pin SSOP 0x0E031069 4 20 4 70 62 8 0 100-pin TQFP 0x0E00D069 4 20 4 46 38 8 0 68-pin QFN 0x0E02B069 2 20 4 29 25 4 0 48-pin QFN 0x0E002069 2 20 4 29 25 4 0 48-pin SSOP 0x0E003069 4 20 4 72 62 8 2 100-pin TQFP 0x0E011069 4 20 4 48 38 8 2 68-pin QFN 0x0E030069 2 20 4 31 25 4 2 48-pin QFN 0x0E006069 2 20 4 31 25 4 2 48-pin SSOP 0x0E007069 2 20 4 29 25 4 0 48-pin SSOP 0x0E050069
4 24 4 70 62 8 0 100-pin TQFP 0x0E034069 4 24 4 46 38 8 0 68-pin QFN 0x0E02A069 2 24 4 29 25 4 0 48-pin QFN 0x0E00B069 2 24 4 29 25 4 0 48-pin SSOP 0x0E029069 4 24 4 72 62 8 2 100-pin TQFP 0x0E022069 4 24 4 - 48 38 8 2 68-pin QFN 0x0E019069 2 24 4 31 25 4 2 48-pin QFN 0x0E02E069 2 24 4 31 25 4 2 48-pin SSOP 0x0E016069 4 24 4 70 62 8 0 100-pin TQFP 0x0E01F069 4 24 4 46 38 8 0 68-pin QFN 0x0E01C069

Notes

Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See the Example Peripherals on page 35 for more information on how analog blocks can be used.

UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 35 for more information on how UDBs can be used.

The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 28 for details on the functionality of each of these types of I/O.

The JTAG ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.

Page 99 of 111
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PRELIMINARY 3 CY8C36 Family Datasheet

Table CY8C36 Family with Single Cycle 8051 continued

MCU Core

Analog

Digital

I/O[66]

Package

JTAG ID[67]

CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive ADC DAC Comparator SC/CT Analog Blocks[64] Opamps DFB CapSense UDBs[65] 16-bit Timer/PWM FS USB CAN 2.0b Total I/O GPIO SIO USBIO

CY8C3666LTI-012 67 64 8 2 CY8C3666PVI-026 67 64 8 2 CY8C3666AXI-036 67 64 8 2 CY8C3666LTI-027 67 64 8 2 CY8C3666LTI-050 67 64 8 2 CY8C3666PVI-057 67 64 8 2 CY8C3666AXI-037 67 64 8 2
12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4 12-bit Del-Sig 4
2 24 4 29 25 4 0 48-pin QFN 0x0E00C069 2 24 4 29 25 4 0 48-pin SSOP 0x0E01A069 4 24 4 72 62 8 2 100-pin TQFP 0x0E024069 4 24 4 48 38 8 2 68-pin QFN 0x0E01B069 2 24 4 31 25 4 2 48-pin QFN 0x0E032069 2 24 4 31 25 4 2 48-pin SSOP 0x0E039069 4 24 4 70 62 8 0 100-pin TQFP 0x0E025069

Notes

Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See the Example Peripherals on page 35 for more information on how analog blocks can be used.

UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 35 for more information on how UDBs can be used.

The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 28 for details on the functionality of each of these types of I/O.

The JTAG ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.

Page 100 of 111 [+] Feedback

PRELIMINARY 3 CY8C36 Family Datasheet
Removed ESO parts from ordering information

Changed USBIO pins from NC to DNU and removed redundant USBIO pin
description notes

Updated POR with brown out DC and AC specs

Updated PGA AC specs

Updated 32 kHz External Crystal DC Specifications

Updated opamp AC specs

Updated XRES IO specs

Updated Inductive boost regulator section

Delta sigma ADC spec updates

Updated comparator section

Removed buzz mode from Power Mode Transition diagram

Updated opamp DC and AC spec tables

Updated PGA DC table
3179219 02/22/2011 MKEA Updated conditions for flash data retention time.

Updated 100-pin TQFP package spec.

Updated EEPROM AC specifications.

Page 110 of 111
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PRELIMINARY 3 CY8C36 Family Datasheet

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 111 of 111
and Creator are trademarks and is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks
of their respective holders.
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More datasheets: T0052704399N | 0RCR-18S08LG | 07CR-12S12LG | 07CR-18S08LG | 74VCXH16374MTDX | 74VCXH16374MTD | CY8C3665AXI-017 | CY8C3665LTI-048 | CY8C3665LTI-043 | CY8C3665LTI-009


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Datasheet ID: CY8C3665LTI-006 508166