74VCXH16374MTDX

74VCXH16374MTDX Datasheet

74VCXH16374 Low Voltage 16-Bit D-Type Flip-Flops with Bushold

Part	Datasheet
74VCXH16374MTDX	74VCXH16374MTDX (pdf)

Related Parts	Information
74VCXH16374MTD	74VCXH16374MTD

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74VCXH16374 Low Voltage 16-Bit D-Type Flip-Flops with Bushold 74VCXH16374 Low Voltage 16-Bit D-Type Flip-Flops with Bushold The VCXH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and output enable OE are common to each byte and can be shorted together for full 16-bit operation. The VCXH16374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74VCXH16374 is designed for low voltage 1.4V to 3.6V VCC applications with output compatibility up to 3.6V. The 74VCXH16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 1.4V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s tPD ns max for 3.0V to 3.6V VCC s Static Drive IOH/IOL r24 mA 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model ! 2000V Machine model ! 200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary Ordering Code: Order Number Package Number Package Descriptions 74VCXH16374GX Note 1 BGA54A 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Preliminary [TAPE and REEL] 74VCXH16374MTD Note 2 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 1 BGA package available in Tape and Reel only. Note 2 Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol 2005 Fairchild Semiconductor Corporation DS500228 74VCXH16374 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA Top Thru View Pin Descriptions Pin Names OEn CPn NC Description Output Enable Input Active LOW Clock Pulse Input Bushold Inputs Outputs No Connect FBGA Pin Assignments O0 NC OE1 CP1 NC O1 NC O3 VCC O5 GND I5 O7 GND I7 O10 O9 GND I9 O12 O11 VCC O14 O13 NC O15 NC OE2 CP2 NC Truth Tables Inputs Outputs OE1 L Inputs Outputs OE2 L H HIGH Voltage Level L LOW Voltage Level X Immaterial HIGH or LOW, control inputs may not float Z High Impedance O0 Previous O0 before HIGH-to-LOW of CP 74VCXH16374 Functional Description The 74VCXH16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each Logic Diagram flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CPn transition. With the Output Enable OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops. Byte 1 0:7 Byte 2 8:15 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74VCXH16374 Absolute Maximum Ratings Note 3 Supply Voltage VCC DC Input Voltage VI

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74VCXH16374 Low Voltage 16-Bit D-Type Flip-Flops with Bushold
74VCXH16374 Low Voltage 16-Bit D-Type Flip-Flops with Bushold

The VCXH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and output enable OE are common to each byte and can be shorted together for full 16-bit operation.

The VCXH16374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level.

The 74VCXH16374 is designed for low voltage 1.4V to 3.6V VCC applications with output compatibility up to 3.6V.

The 74VCXH16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s 1.4V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors s tPD
ns max for 3.0V to 3.6V VCC s Static Drive IOH/IOL
r24 mA 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance:

Human body model ! 2000V Machine model ! 200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary
Ordering Code:

Order Number Package Number

Package Descriptions
74VCXH16374GX Note 1

BGA54A
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide

Preliminary [TAPE and REEL]
74VCXH16374MTD Note 2

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide

Note 1 BGA package available in Tape and Reel only.
Note 2 Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol
2005 Fairchild Semiconductor Corporation DS500228
74VCXH16374

Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA Top Thru View

Pin Descriptions

Pin Names

OEn CPn NC

Description Output Enable Input Active LOW

Clock Pulse Input Bushold Inputs Outputs No Connect

FBGA Pin Assignments

O0 NC OE1 CP1 NC

O1 NC

O3 VCC

O5 GND I5

O7 GND I7

O10 O9 GND I9

O12 O11 VCC

O14 O13 NC

O15 NC OE2 CP2 NC

Truth Tables

Inputs

Outputs

OE1 L

Inputs

Outputs

OE2 L

H HIGH Voltage Level L LOW Voltage Level X Immaterial HIGH or LOW, control inputs may not float Z High Impedance O0 Previous O0 before HIGH-to-LOW of CP
74VCXH16374

Functional Description

The 74VCXH16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each

Logic Diagram
flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CPn transition. With the Output Enable OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops.

Byte 1 0:7

Byte 2 8:15

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74VCXH16374

Absolute Maximum Ratings Note 3

Supply Voltage VCC DC Input Voltage VI

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Datasheet ID: 74VCXH16374MTDX 513485