CY8C24423-24LFI

CY8C24423-24LFI Datasheet


CY8C24123, CY8C24223, CY8C24423

Part Datasheet
CY8C24423-24LFI CY8C24423-24LFI CY8C24423-24LFI (pdf)
Related Parts Information
CY8C24123-24SIT CY8C24123-24SIT CY8C24123-24SIT
CY8C24423-24PVIT CY8C24423-24PVIT CY8C24423-24PVIT
CY8C24223-24PVIT CY8C24223-24PVIT CY8C24223-24PVIT
CY8C24423-24PVI CY8C24423-24PVI CY8C24423-24PVI
CY8C24423-24PI CY8C24423-24PI CY8C24423-24PI
CY8C24123-24PI CY8C24123-24PI CY8C24123-24PI
CY8C24123-24SI CY8C24123-24SI CY8C24123-24SI
CY8C24223-24PI CY8C24223-24PI CY8C24223-24PI
CY8C24223-24PVI CY8C24223-24PVI CY8C24223-24PVI
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CY8C24123, CY8C24223, CY8C24423

December 22, 2003 Cypress MicroSystems 2700 162nd Street SW

Building D Lynnwood, WA 98037 Phone:

CY8C24xxx Preliminary Data Sheet

Cypress MicroSystems, Inc. 2000 All rights reserved. PSoC Programmable System-on-Chip is a trademark of Cypress MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress MicroSystems’ products in life-support system applications implies that the manufacturer assumes all risk of such use and in doing so, indemnifies Cypress MicroSystems against all charges.

December 22, 2003

Contents

SECTION A OVERVIEW

Getting Started

Development Kits

Tele-Training

Consultants

Technical Support

Application Notes

Top-Level Architecture

Development Tools

PSoC Designer Software Subsystems

Hardware Tools

User Modules and Development Process
Ordering Information

Organization and Conventions

Document Organization

Document Conventions

Pin Information Pin Summary Pinouts

Packaging Information Packaging Thermal Impedances

SECTION B CORE ARCHITECTURE

Top-Level Core Architecture

Core Register Summary

CPU Core M8C Internal Registers Address Spaces Instruction Set Instruction Format One-Byte Two-Byte Three-Byte Instructions Addressing Modes Source Immediate Source Direct Source Indexed Destination

December 22, 2003

Contents

CY8C24xxx Preliminary Data Sheet

Destination Indexed Destination Direct Source Immediate Destination Indexed Source Immediate Destination Direct Source Indirect Post Destination Indirect Post Increment Register CPU_F Flag Register

Supervisory ROM SROM 47 Architectural Description Additional SROM Feature SROM Function Register CPU_SCR1 Register Clocking

Interrupt Controller 53 Architectural Description Register INT_CLRx INT_MSKx Register INT_VC CPU_F

General Purpose IO GPIO 57 Architectural Description Digital IO Global Analog IO GPIO Block Interrupts Register PRTxDR PRTxIE Registers PRTxGS PRTxDMx Registers PRTxICx Registers

Analog Output Drivers 63 Architectural Description Register ABF_CR0 Register

Internal Main Oscillator IMO 65 Architectural Description Register IMO_TR Register

Internal Low Speed Oscillator ILO 67 Architectural Description Register ILO_TR Register
32 kHz Crystal Oscillator ECO 69 Architectural Description ECO External Register

December 22, 2003

CY8C24xxx Preliminary Data Sheet

Contents

OSC_CR0 ECO_TR Register CPU_SCR1

Phase Locked Loop PLL Architectural Description Register Definitions OSC_CR0 OSC_CR2

Sleep and Watchdog Architectural Description 32 kHz Clock Selection Sleep Timer Sleep Application Register Definitions INT_MSK0 Register RES_WDT Register OSC_CR0 CPU_SCR1 ILO_TR Register ECO_TR Register CPU_SCR0 Timing Diagrams Sleep Wake Up Sequence Bandgap Refresh Watchdog Timer WDT Power

SECTION C REGISTER REFERENCE

Register Conventions

Register Mapping Tables

Register Map 0 Table User Space

Register Map 1 Table Configuration Space

Register Details Bank 0 PRTxDR PRTxIE PRTxGS PRTxDM2 DxBxxDR0 DxBxxDR1 DxBxxDR2 DxBxxCR0 DCBxxCR0 AMX_IN ARF_CR

December 22, 2003

Contents

CY8C24xxx Preliminary Data Sheet

CMP_CR0 ASY_CR CMP_CR1 ACBxxCR3 ACBxxCR0 ACBxxCR1 ACBxxCR2 ASCxxCR0 ASCxxCR1 ASCxxCR2 ASCxxCR3 ASDxxCR0 ASDxxCR1 ASDxxCR2 ASDxxCR3 RDIxRI RDIxSYN RDIxIS RDIxLT0 RDIxLT1 RDIxRO0 RDIxRO1 I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL MAC_X/ACC_DR1 MAC_Y/ACC_DR0 MAC_CL0/ACC_DR3 MAC_CL1/ACC_DR2 CPU_F CPU_SCR1 CPU_SCR0 Bank 1 PRTxDM0 PRTxDM1 PRTxIC0 PRTxIC1

December 22, 2003

CY8C24xxx Preliminary Data Sheet

Contents

DxBxxFN DxBxxIN DxBxxOU CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 AMD_CR1 ALT_CR0 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP IMO_TR ILO_TR BDG_TR ECO_TR
The Overview section discusses the Features, Getting Started, Top-Level Architecture, Development Tools, User Modules and Development Process, along with Ordering Information. It also lists the Conventions used in this document. This section encompasses the following chapters:
s Pin Information on page 23
s Packaging Information on page 27
s Powerful Harvard Architecture Processor Speeds to 24 MHz x 8 Multiply, 32-Bit Accumulate Power at High Speed to V Operating Voltage Voltages Down to V Using On-Chip Switch Mode Pump SMP Temperature Range to +85°C
s Advanced Peripherals PSoC Blocks Rail-to-Rail Analog PSoC Blocks Provide to 14-Bit ADCs to 8-Bit DACs Gain Amplifiers Filters and Comparators Digital PSoC Blocks Provide to 32-Bit Timers, Counters and PWMs and PRS Modules UART Masters Or Slaves to all GPIO Pins Peripherals by Combining Blocks
s Flexible On-Chip Memory Bytes Flash Program Storage 50,000 Erase/Write Cycles Bytes SRAM Data Storage Serial Programming Flash Updates Protection Modes Emulation in Flash
s Precision, Programmable Clocking ± 24/48 MHz Oscillator 24 MHz with Optional 32 kHz Crystal and PLL External Oscillator, up to 24 MHz Oscillator for Watchdog and Sleep
s Programmable Pin Configurations mA Drive on all GPIO up, Pull down, High Z, Strong, or Open

Drain Drive Modes on all GPIO to 10 Analog Inputs on GPIO 30 mA Analog Outputs on GPIO Interrupt on all GPIO
s Additional System Resources Slave, Master, and Multi-Master to 400 kHz and Sleep Timers Low Voltage Detection Supervisory Circuit Precision Voltage Reference
s Complete Development Tools Development Software PSoC Designer In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory

December 22, 2003

SECTION A OVERVIEW

CY8C24xxx Preliminary Data Sheet

Getting Started

The quickest path to understanding the PSoC silicon is through the PSoC Designer software GUI. This data sheet is useful for understanding the details of the PSoC integrated circuit, but is not a good starting point for a new PSoC developer seeking to get a general overview of this new technology.

PSoC developers are not required to build their own ADCs, DACs, and other peripherals. Embedded in the PSoC Designer software are the individual data sheets, performance graphs, and PSoC User Modules graphically selected code packets for the peripherals, such as the incremental ADCs, DACs, LCD controllers, op amps, low-pass filters, etc. With simple GUI-based selection, placement, and connection, the basic architecture of a design may be developed within PSoC Designer software without ever writing a single line of code.

Development Kits

Development Kits are available from the following distributors Digi-Key, Avnet, Arrow, and Future. The Cypress.com Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Online Store web site and click on PSoC Programmable System-on-Chip to view a current list of available items.

Tele-Training

PSoC "Tele-training" is available for beginners and is taught by a live marketing or application engineer over the phone. Please see for more details. Five training classes are available to accelerate the learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus.

Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to the following web site,

Technical Support

PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at

Application Notes

A long list of application notes will assist you in every aspect of your design effort. Go to results.cfm to locate the PSoC application notes.

December 22, 2003

CY8C24xxx Preliminary Data Sheet

Top-Level Architecture

The figure below illustrates the top-level architecture of the PSoc CY8C24xxx. SYSTEM BUS

SECTION A OVERVIEW

Port 2

Port 1

Port 0

Analog Drivers

Global Digital Interconnect

Global Analog Interconnect

SRAM

PSoC CORE

Supervisory ROM SROM Flash Nonvolatile Memory
Ordering Information
The following table lists the PSoC Device family’s key features and ordering codes. PSoC Device Family Key Features
Package Ordering Code Flash Kbytes

RAM Bytes Switch Mode Pump Temperature Range Digital PSoC Blocks

Rows of 4 Analog PSoC Blocks

Columns of 3 Digital IO Pins Analog Inputs Analog Outputs

XRES Pin
8 Pin 300 Mil DIP 8 Pin 150 Mil SOIC 20 Pin 300 Mil DIP 20 Pin 210 Mil SSOP 20 Pin 210 Mil SSOP Tape and Reel 20 Pin 300 Mil SOIC 20 Pin 300 Mil SOIC Tape and Reel 28 Pin 300 Mil DIP 28 Pin 210 Mil SSOP 28 Pin 210 Mil SSOP Tape and Reel 28 Pin 300 Mil SOIC 28 Pin 300 Mil SOIC Tape and Reel 32 Pin 5x5 mm MLF

CY8C24123-24PI CY8C24123-24SI CY8C24223-24PI CY8C24223-24PVI CY8C24223-24PVIT CY8C24223-SI CY8C24223-SIT CY8C24423-24PI CY8C24423-24PVI CY8C24423-24PVIT CY8C24423-SI CY8C24423-SIT CY8C24423-24LFI
4 256 No -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4 256 Yes -40C to +85C 4
2 No 2 No 2 Yes 2 Yes
2 Yes
2 Yes
2 Yes
24 10
2 Yes
24 10
2 Yes
24 10
2 Yes
24 10
2 Yes
24 10
2 Yes
24 10
2 Yes

December 22, 2003

SECTION A OVERVIEW

CY8C24xxx Preliminary Data Sheet

Organization and Conventions

Document Organization

Document Conventions

Register Conventions

The following table lists the register conventions that are specific to this document.

Convention ‘x’ in a register name RW R W L C 00 XX 0, 1,

Example

ACBxxCR1

RW:00 R:00 W:00 RL:00 RC:00 RW:00 RW:XX 0,04h 1, 23h
x,F7h

Empty, grayedout table cell

Description Multiple instances/address ranges of the same register. Read and write register or bit s Read register or bit s Write register or bit s Logical register or bit s Clearable register or bit s Reset value is 0x00 Register is not reset Register is in bank 0 Register is in bank 1 Register exists in register bank 0 and register bank 1 Reserved bit or group of bits, unless otherwise stated.

Units of Measure

The following table lists the units of measure used in this document.
The SPI Control CR0 register contains both control and status bits. There are four control bits that are read/write Enable, Clock Phase and Clock Polarity to set the mode, and LSB First, which controls bit ordering. There are two read-only status bits Overrun and SPI Complete. There are two additional read-only status bits to indicate TX and RX Buffer status.
The SPI Control CR0 register contains both control and status bits. There are four control bits that are read/write Enable, Clock Phase and Clock Polarity to set the mode, and LSB First, which controls bit ordering. There are two read-only status bits Overrun and SPI Complete. There are two additional read-only status bits to indicate TX and RX Buffer status.

The Transmitter Control CR0 register contains three control bits and two status bits. The control bits are Enable, Parity Enable, and Parity Type, and have read/write access. The status bits, TX Reg Empty and TX Complete, are read-only.

The Receiver Control CR0 register contains both control and status bits. Three control bits are read/write Enable, Parity Enable, and Parity Type. There are five read-only status bits RX Reg Full, RX Active, Framing Error, Overrun, and Parity Error.

Interrupt Mask Register

INT_MSK1 Register

The INT_MSK1 register is described in the “Interrupt Controller” chapter on page For additional information, reference the INT_MSK1 register on page

Configuration Registers

The Configuration block contains 3 registers Function DxBxxFN , Input DxBxxIN , and Output DxBxxOU . The values in these registers should not be changed while the block is enabled.

DxBxxFN Registers

These registers contain the primary Function and Mode bits. The function bits configure the block into one of the available block functions six for the Comm block, four for the Basic block . The mode bits select the options available for the selected function. These bits should only be changed when the block is disabled.

Three additional control bits are found in this register. The End/Single bit is used to indicate the last or most significant block in a chainable function. This bit must also be set if the chainable function only consists of a single block. The Data Invert bit optimally inverts the selected data input.

The BCEN bits enable the primary output of the block, to drive the row broadcast block. The BCEN bits are set independently in each block and therefore, care must be taken to ensure that only one BCEN bit in a given row is enabled.

However, if any of the blocks in a given row have the BCEN bit set, the input that allows the broadcast net from other rows to drive the given row’s broadcast net is disabled see Figure 16-2 on page

Table DxBxxFN Function Registers
[2:0] Function
[4:3] Mode [5] End/Single [6] BCEN [7] Data Invert
000b Timer 001b Counter 010b CRCPRS 011b Reserved 100b Dead band for PWM 101b UART 110b SPI 111b Reserved

Function specific
1 == Block is not chained or is at the end of a chain 0 == Block is at the start of or in the middle of a chain
1 == Disable 0 == Enable
1 == Invert block’s data input 0 == Do not invert block’s data input

For additional information, reference the DxBxxFN register on page

December 22, 2003

Digital Blocks

CY8C24xxx Preliminary Data Sheet

DxBxxIN Registers

The Input registers are 8 bits and consist of two 4-bit fields to control each of the 16-1 Clock and Data input multiplexers. The meaning of these fields depends on the external clock and data connections, which is context specific.

Table Digital Block Input Definitions

Inputs

DATA

Auxiliary

Timer

Capture

Counter

Enable

Dead Band

Kill

Reference *

CRCPRS

Serial Data **

SPIM
More datasheets: 9091-05-11 | 3568 | CY8C24123-24SIT | CY8C24423-24PVIT | CY8C24223-24PVIT | CY8C24423-24PVI | CY8C24423-24PI | CY8C24123-24PI | CY8C24123-24SI | CY8C24223-24PI


Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY8C24423-24LFI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY8C24423-24LFI 508152