CY7C68000-56PVXCT

CY7C68000-56PVXCT Datasheet

CY7C68000

Part	Datasheet
CY7C68000-56PVXCT	CY7C68000-56PVXCT (pdf)

Related Parts	Information
CY7C68000-56LFXCT	CY7C68000-56LFXCT
CY7C68000-56PVXC	CY7C68000-56PVXC
CY7C68000-56LFXC	CY7C68000-56LFXC

PDF Datasheet Preview
CY7C68000 TX2 USB UTMI Transceiver EZ-USB TX2 Features • Synchronous field and EOP detection on receive packets • Synchronous field and EOP generation on transmit packets • Data and clock recovery from the USB serial stream that operates at the maximum allowable USB bandwidth. • Bit stuffing/unstuffing bit stuff error detection This allows the system designer to keep the complex highspeed analog USB components external to the digital ASIC which decreases development time and associated risk. A standard interface is provided that is USB 2.0-certified and is compliant with Transceiver Macrocell Interface UTMI specification version dated • Staging register to manage data rate variation due to bit stuffing/unstuffing • 16-bit 30-MHz, and 8-bit 60-MHz parallel interface • Ability to switch between FS and HS terminations and signaling Two packages are defined for the family 56-pin SSOP and 56pin QFN. The function block diagram is shown in Figure The features of the EX-USB TX2 are: • Supports detection of USB reset, suspend, and resume • Supports HS identification and detection as defined by the USB Specification • Supports transmission of resume signaling • UTMI-compliant/USB-2.0-certified for device operation • V operation • Operates in both USB high speed HS , 480 • Two package QFN, and 56-pin SSOP Mbits/second, and full speed FS , 12 Mbits/second • All required terminations, including 1.5K-ohm pull up • Serial-to-parallel and parallel-to-serial conversions on DPLUS, are internal to the chip • 8-bit unidirectional, 8-bit bidirectional, or 16-bit • Supports USB test modes bidirectional external data interface CY7C68000 CY7C68000 XTALIN/ OUT 20X PLL PLL_480 UTMI CLK UTMI CLK Full-Speed Rx High-Speed Rx Traffic Sync XCVR High-Speed Tx Full-Speed Tx Elasticity Buffer Ordering Information Table Ordering Information Ordering Code CY7C68000-56LFXC CY7C68000-56LFXCT CY7C68000-56PVC CY7C68000-56PVCT CY7C68000-56PVXC CY7C68000-56PVXCT CY3683 Package Diagrams The TX2 is available in two packages • 56-pin SSOP • 56-pin QFN. CY7C68000 Package Type 56 QFN Pb-Free 56 QFN Pb-Free Tap/Reel 56 SSOP 56 SSOP Tape/Reel 56 SSOP Pb-Free 56 SSOP Pb-Free Tape/Reel EZ-USB TX2 Development Board Figure 56-lead Shrunk Small Outline Package O56 51-85062-C Page 11 of 14 [+] Feedback CY7C68000 DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-220 56-Lead QFN 8 x 8 mm Sawn Version LS56B MAX. TOP VIEW SIDE VIEW BOTTOM VIEW PIN #1 CORNER MAX. REF. MAX. PIN #1 CORNER E-PAD PAD SIZE VARY BY DEVICE TYPE E-PAD maximum size X mm [187 x 215 mils] width x length . SEATING PLANE Figure 56-lead Quad Flatpack No Lead Package 8 x 8 mm SAWN VERSION PCB Layout Recommendations[3] 51-85187-A The following recommendations should be followed to ensure reliable high-performance operation. • At least a four-layer impedance controlled boards are required to maintain signal quality. • Specify impedance targets ask your board vendor what they can achieve . • To control impedance, maintain trace widths and trace spacing to within specifications. • Minimize stubs to minimize reflected signals. • Connections between the USB connector shell and signal ground must be done near the USB connector. • Bypass/flyback capacitors on VBus, near the connector, are recommended. • DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of mm. • Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. • If possible, do not place any vias on the DPLUS or DMINUS trace routing. • Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm. Note: Source for recommendations EZ-USB FX2 PCB Design Recommendations, HighSpeed USB Platform Design Guidelines, Page 12 of 14 [+] Feedback 448451 SEE ECN TEH Updated Ordering information to include Pb-Free part numbers. Page 14 of 14 [+] Feedback

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CY7C68000

TX2 USB UTMI Transceiver

EZ-USB TX2 Features
• Synchronous field and EOP detection on receive
packets
• Synchronous field and EOP generation on transmit packets
• Data and clock recovery from the USB serial stream
that operates at the maximum allowable USB bandwidth.
• Bit stuffing/unstuffing bit stuff error detection

This allows the system designer to keep the complex highspeed analog USB components external to the digital ASIC which decreases development time and associated risk. A standard interface is provided that is USB 2.0-certified and is compliant with Transceiver Macrocell Interface UTMI specification version dated
• Staging register to manage data rate variation due to bit stuffing/unstuffing
• 16-bit 30-MHz, and 8-bit 60-MHz parallel interface
• Ability to switch between FS and HS terminations and signaling

Two packages are defined for the family 56-pin SSOP and 56pin QFN.

The function block diagram is shown in Figure The features of the EX-USB TX2 are:
• Supports detection of USB reset, suspend, and resume
• Supports HS identification and detection as defined by the USB Specification
• Supports transmission of resume signaling
• UTMI-compliant/USB-2.0-certified for device operation
• V operation
• Operates in both USB high speed HS , 480
• Two package QFN, and 56-pin SSOP

Mbits/second, and full speed FS , 12 Mbits/second
• All required terminations, including 1.5K-ohm pull up
• Serial-to-parallel and parallel-to-serial conversions
on DPLUS, are internal to the chip
• 8-bit unidirectional, 8-bit bidirectional, or 16-bit
• Supports USB test modes
bidirectional external data interface

CY7C68000

CY7C68000

XTALIN/ OUT
20X PLL

PLL_480

UTMI CLK

UTMI CLK

Full-Speed Rx

High-Speed Rx Traffic

Sync

XCVR High-Speed Tx

Full-Speed Tx

Elasticity Buffer
Ordering Information
Table Ordering Information Ordering Code

CY7C68000-56LFXC CY7C68000-56LFXCT CY7C68000-56PVC CY7C68000-56PVCT CY7C68000-56PVXC CY7C68000-56PVXCT CY3683

Package Diagrams

The TX2 is available in two packages
• 56-pin SSOP
• 56-pin QFN.

CY7C68000

Package Type 56 QFN Pb-Free 56 QFN Pb-Free Tap/Reel 56 SSOP 56 SSOP Tape/Reel 56 SSOP Pb-Free 56 SSOP Pb-Free Tape/Reel EZ-USB TX2 Development Board

Figure 56-lead Shrunk Small Outline Package O56
51-85062-*C

Page 11 of 14 [+] Feedback

CY7C68000

DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-220
56-Lead QFN 8 x 8 mm Sawn Version LS56B

MAX.

TOP VIEW

SIDE VIEW

BOTTOM VIEW

PIN #1 CORNER

MAX.

REF. MAX.

PIN #1 CORNER

E-PAD

PAD SIZE VARY BY DEVICE TYPE

E-PAD maximum size X mm [187 x 215 mils] width x length .

SEATING PLANE

Figure 56-lead Quad Flatpack No Lead Package 8 x 8 mm SAWN VERSION

PCB Layout Recommendations[3]
51-85187-*A

The following recommendations should be followed to ensure reliable high-performance operation.
• At least a four-layer impedance controlled boards are required to maintain signal quality.
• Specify impedance targets ask your board vendor what they can achieve .
• To control impedance, maintain trace widths and trace spacing to within specifications.
• Minimize stubs to minimize reflected signals.
• Connections between the USB connector shell and signal ground must be done near the USB connector.
• Bypass/flyback capacitors on VBus, near the connector, are recommended.
• DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of mm.
• Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces.
• If possible, do not place any vias on the DPLUS or DMINUS trace routing.
• Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm.

Note:

Source for recommendations EZ-USB FX2 PCB Design Recommendations, HighSpeed USB Platform Design Guidelines,

Page 12 of 14 [+] Feedback
448451 SEE ECN TEH Updated Ordering information to include Pb-Free part numbers.

Page 14 of 14 [+] Feedback

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Datasheet ID: CY7C68000-56PVXCT 508137