CY7C66113C-LFXC

CY7C66113C-LFXC Datasheet

CY7C66013C, CY7C66113C

Part	Datasheet
CY7C66113C-LFXC	CY7C66113C-LFXC (pdf)

Related Parts	Information
CY7C66113C-LFXCT	CY7C66113C-LFXCT
CY7C66113C-LTXC	CY7C66113C-LTXC
CY7C66113C-LTXCT	CY7C66113C-LTXCT

PDF Datasheet Preview
CY7C66013C, CY7C66113C Full Speed USB 12 Mbps Peripheral Controller with Integrated Hub • Full speed USB peripheral microcontroller with an integrated USB hub Well suited for USB compound devices such as a keyboard hub function • 8-bit USB optimized microcontroller Harvard architecture 6 MHz external clock source 12 MHz internal CPU clock 48 MHz internal Hub clock • Internal memory 256 bytes of RAM 8 KB of PROM • Integrated Master and Slave I2C compatible controller 100 kHz enabled through General Purpose I/O GPIO pins • Hardware Assisted Parallel Interface HAPI for data transfer to external devices • I/O ports Three GPIO ports Port 0 to 2 capable of sinking 8 mA per pin typical An additional GPIO port 3 capable of sinking 12 mA per pin typical for high current requirements LEDs Higher current drive achievable by connecting multiple GPIO pins together to drive a common output Each GPIO port is configured as inputs with internal pull ups or open drain outputs or traditional CMOS outputs A Digital to Analog Conversion DAC port with programmable current sink outputs is available on the CY7C66113C device Maskable interrupts on all I/O pins • 12-bit free running timer with one microsecond clock ticks • Watchdog Timer WDT • Internal Power on Reset POR • USB Specification compliance Conforms to USB Specification, Version Conforms to USB HID Specification, Version Supports one or two device addresses with up to five user configured endpoints • Up to two 8-byte control endpoints • Up to four 8-byte data endpoints • Up to two 32-byte data endpoints Integrated USB transceivers Supports four downstream USB ports GPIO pins provide individual power control outputs for each downstream USB port GPIO pins provide individual port over current inputs for each downstream USB port • Improved output drivers to reduce electromagnetic interference EMI • Operating voltage from DC • Operating temperature from • CY7C66013C available in 48-pin SSOP -PVXC packages • CY7C66113C available in 56-pin QFN or 56-pin SSOP -PVXC packages • Industry standard programmer support Functional Overview The CY7C66013C and CY7C66113C are compound devices with a full speed USB microcontroller in combination with a USB hub. Each device is suited for combination peripheral functions with hubs such as a keyboard hub function. The 8-bit one time programmable microcontroller with a 12 Mbps USB Hub supports as many as four downstream ports. GPIO The CY7C66013C features 29 GPIO pins to support USB and other applications. The I/O pins are grouped into four ports P0[7:0], P1[7:0], P2[7:0], P3[4:0] where each port is configured as inputs with internal pull ups, open drain outputs, or traditional CMOS outputs. Ports 0 to 2 are rated at 8 mA per pin typical sink current. Port 3 pins are rated at 12 mA per pin typical sink current, which allows these pins to drive LEDs. Multiple GPIO pins are connected together to drive a single output for more drive current capacity. Additionally, each I/O pin is used to generate a GPIO interrupt to the microcontroller. All of the GPIO interrupts all share the same “GPIO” interrupt vector. The CY7C66113C has 31 GPIO pins P0[7:0], P1[7:0], P2[7:0], P3[6:0] . The CY7C66113C has an additional port P4[7:0] that features an additional eight programmable sink current I/O pins DAC . Every DAC pin includes an integrated 14 kΩ pull up resistor. When a ‘1’ is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven HIGH by the internal pull up resistor. When a ‘0’ is written to a DAC I/O pin, the internal pull up is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin is used as an input with an internal pull up by writing a ‘1’ to the pin. The sink current for each DAC I/O pin is individually programmed to one of sixteen values using dedicated Isink registers. DAC bits DAC[1:0] is used as high current outputs with a programmable sink current range of to 16 mA typical . DAC bits DAC[7:2] have a programmable current sink range of to mA typical . Multiple DAC pins are connected together to drive a single output that requires more sink current capacity. Each I/O pin is used to generate a DAC interrupt to the microcontroller. Also, the interrupt polarity for each DAC I/O pin is individually programmable. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C66013C, CY7C66113C Clock The microcontroller uses an external 6 MHz crystal and an internal oscillator to provide a reference to an internal PLL based clock generator. This technology allows the customer application to use an inexpensive 6 MHz fundamental crystal that reduces the clock related noise emissions EMI . A PLL clock generator provides the 6, 12, and 48 MHz clock signals for distribution within the microcontroller. Memory The CY7C66013C and CY7C66113C have 8 KB of PROM. Power on Reset, Watchdog, and Free Running Timer These parts include POR logic, a WDT, and a 12-bit free-running timer. The POR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address 0x0000. The WDT is used to ensure that the microcontroller recovers after a period of inactivity. The firmware may become inactive for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. I2C and HAPI Interface The microcontroller communicates with external electronics through the GPIO pins. An I2C compatible interface accommodates a 100 kHz serial link with an external device. There is also a HAPI to transfer data to an external device. Timer The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128 us and ms. The timer is used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read. Interrupts The microcontroller supports eleven maskable interrupts in the vectored interrupt controller. Interrupt sources include the 128 us bit 6 and ms bit 9 outputs from the free-running timer, five USB endpoints, the USB hub, the DAC port, the GPIO ports, and the I2C compatible master mode interface. The timer bits cause an interrupt if enabled when the bit toggles from LOW ‘0’ to HIGH The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller sends a packet to the USB host. The DAC ports have an additional level of masking that allows the user to select which DAC inputs causes a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs causes a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity is programmed for each GPIO port as part of the port configuration. The interrupt polarity can be rising edge ‘0’ to ‘1’ or falling edge ‘1’ to The CY7C66013C and CY7C66113C include an integrated USB Serial Interface Engine SIE that supports the integrated peripherals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the hub two endpoints and a device address for a compound device three endpoints . The SIE allows the USB host to communicate with the hub and functions integrated into the microcontroller. The part includes a 1:4 hub repeater with one upstream port and four downstream ports. The USB Hub allows power management control of the downstream ports by using GPIO pins assigned by the user firmware. The user has the option of ganging the downstream ports together with a single pair of power management pins, or providing power management for each port with four pairs of power management pins. Ordering Information Ordering Code CY7C66013C-PVXC CY7C66113C-PVXC CY7C66113C-LFXC CY7C66113C-PVXCT CY7C66113C-XC CY7C66113C-LTXC CY7C66113C-LTXCT PROM Size 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB Package Type 48-pin 300-Mil SSOP 56-pin 300-Mil SSOP 56-pin QFN 56-pin 300-Mil SSOP Die 56-pin QFN 56-pin QFN Operating Range Commercial Page 54 of 59 [+] Feedback Package Diagrams CY7C66013C, CY7C66113C Figure 48-Pin Shrunk Small Outline Package O48 Figure 56-Pin Shrunk Small Outline Package O56 51-85061-C 51-85062-C Page 55 of 59 [+] Feedback CY7C66013C, CY7C66113C Figure 56-Pin QFN 8 x 8 MM LF56A 51-85144 G Page 56 of 59 [+] Feedback CY7C66013C, CY7C66113C Figure 56-QFN 8x8x0.9 mm EPad 6.1x6.1 mm 51-85187 C Page 57 of 59 [+] Feedback CY7C66013C, CY7C66113C Quad Flat Package No Leads QFN Package Design Notes Electrical contact of the part to the Printed Circuit Board PCB is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper Cu fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the FX1 through the device’s metal paddle on the bottom side of the package. Heat from here, is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via. A via is a plated through hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process. For further information on this package design please refer to the application note Surface Mount Assembly of AMKOR’s MicroLeadFrame MLF Technology. This application note can be downloaded from AMKOR’s website from the following URL 0902.pdf. The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. Figure 29 displays a cross sectional area underneath the package. The cross section is of only one via. The thickness of the solder paste template should be 5 mil. It is recommended that “No Clean” type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow. Figure 58 is a plot of the solder mask pattern. This pad is thermally connected and is not electrically connected inside the chip. To minimize EMI, this pad should be connected to the ground plane of the circuit board. Figure Cross Section of the Area Underneath the QFN Package Cu Fill Solder Mask Cu Fill PCB Material PCB Material Via hole for thermally connecting the QFN to the circuit board ground plane. This figure only shows the top three layers of the circuit board Top Solder, PCB Dielectric, and the Ground Plane Figure Plot of the Solder Mask White Area Page 58 of 59 [+] Feedback CY7C66013C, CY7C66113C Document History Page Document Title CY7C66013C, CY7C66113C Full Speed USB 12 Mbps Peripheral Controller with Integrated Hub Document Number 38-08024 ECN No. Submission Date Updated part number and ordering information. Added QFN Package Drawing and Design Notes. Corrected bit names in Figures 9-3, 9-4, 9-5, 9-8, 9-9, 9-10, 10-5, 16-1, 18-1, 18-2, 18-3, 18-6, 18-7, 18-9, Removed Hub Ports Force Low register address 0x52. Added HAPI to Interrupt Vector Number 11 in Table Corrected bit names in Section Corrected Units in Table for RUUP, RUDN, REXT, and ZO. Added DIE diagram and related information. Added HAPI to GPIO interrupt vector in Table 5-1 and figure 16-3 C 1825466 See ECN TLY/PYRS Changed Title from "CY7C66013, CY7C66113 Full Speed USB 12 Mbps Peripheral Controller with Integrated Hub" to "CY7C66013C, CY7C66113C Full Speed USB 12 Mbps Peripheral Controller with Integrated Hub" Changed package description for CY7C66013C and CY7C66113C from -PVC to -PVXC D 2720540 06/18/09 DPT/AESA Added 56 QFN 8x8x1 mm package diagram and ordering information Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers psoc.cypress.com clocks.cypress.com Wireless Memories Image Sensors wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 59 of 59 [+] Feedback

PDF Datasheet Preview

CY7C66013C, CY7C66113C

Full Speed USB 12 Mbps Peripheral Controller with Integrated Hub
• Full speed USB peripheral microcontroller with an integrated USB hub Well suited for USB compound devices such as a keyboard hub function
• 8-bit USB optimized microcontroller Harvard architecture 6 MHz external clock source 12 MHz internal CPU clock 48 MHz internal Hub clock
• Internal memory 256 bytes of RAM 8 KB of PROM
• Integrated Master and Slave I2C compatible controller 100 kHz enabled through General Purpose I/O GPIO pins
• Hardware Assisted Parallel Interface HAPI for data transfer to external devices
• I/O ports Three GPIO ports Port 0 to 2 capable of sinking 8 mA per pin typical An additional GPIO port 3 capable of sinking 12 mA per pin typical for high current requirements LEDs Higher current drive achievable by connecting multiple GPIO pins together to drive a common output Each GPIO port is configured as inputs with internal pull ups or open drain outputs or traditional CMOS outputs A Digital to Analog Conversion DAC port with programmable current sink outputs is available on the CY7C66113C device Maskable interrupts on all I/O pins
• 12-bit free running timer with one microsecond clock ticks
• Watchdog Timer WDT
• Internal Power on Reset POR
• USB Specification compliance Conforms to USB Specification, Version Conforms to USB HID Specification, Version Supports one or two device addresses with up to five user configured endpoints
• Up to two 8-byte control endpoints
• Up to four 8-byte data endpoints
• Up to two 32-byte data endpoints Integrated USB transceivers Supports four downstream USB ports GPIO pins provide individual power control outputs for each downstream USB port GPIO pins provide individual port over current inputs for each downstream USB port
• Improved output drivers to reduce electromagnetic interference EMI
• Operating voltage from DC
• Operating temperature from
• CY7C66013C available in 48-pin SSOP -PVXC packages
• CY7C66113C available in 56-pin QFN or 56-pin SSOP -PVXC packages
• Industry standard programmer support

Functional Overview

The CY7C66013C and CY7C66113C are compound devices with a full speed USB microcontroller in combination with a USB hub. Each device is suited for combination peripheral functions with hubs such as a keyboard hub function. The 8-bit one time programmable microcontroller with a 12 Mbps USB Hub supports as many as four downstream ports.

GPIO

The CY7C66013C features 29 GPIO pins to support USB and other applications. The I/O pins are grouped into four ports P0[7:0], P1[7:0], P2[7:0], P3[4:0] where each port is configured as inputs with internal pull ups, open drain outputs, or traditional CMOS outputs. Ports 0 to 2 are rated at 8 mA per pin typical sink current. Port 3 pins are rated at 12 mA per pin typical sink current, which allows these pins to drive LEDs. Multiple GPIO pins are connected together to drive a single output for more drive current capacity. Additionally, each I/O pin is used to generate a GPIO interrupt to the microcontroller. All of the GPIO interrupts all share the same “GPIO” interrupt vector.

The CY7C66113C has 31 GPIO pins P0[7:0], P1[7:0], P2[7:0], P3[6:0] .

The CY7C66113C has an additional port P4[7:0] that features an additional eight programmable sink current I/O pins DAC . Every DAC pin includes an integrated 14 kΩ pull up resistor. When a ‘1’ is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven HIGH by the internal pull up resistor. When a ‘0’ is written to a DAC I/O pin, the internal pull up is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin is used as an input with an internal pull up by writing a ‘1’ to the pin.

The sink current for each DAC I/O pin is individually programmed to one of sixteen values using dedicated Isink registers. DAC bits DAC[1:0] is used as high current outputs with a programmable sink current range of to 16 mA typical . DAC bits DAC[7:2] have a programmable current sink range of to mA typical . Multiple DAC pins are connected together to drive a single output that requires more sink current capacity. Each I/O pin is used to generate a DAC interrupt to the microcontroller. Also, the interrupt polarity for each DAC I/O pin is individually programmable.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C66013C, CY7C66113C

Clock

The microcontroller uses an external 6 MHz crystal and an internal oscillator to provide a reference to an internal PLL based clock generator. This technology allows the customer application to use an inexpensive 6 MHz fundamental crystal that reduces the clock related noise emissions EMI . A PLL clock generator provides the 6, 12, and 48 MHz clock signals for distribution within the microcontroller.

Memory

The CY7C66013C and CY7C66113C have 8 KB of PROM.

Power on Reset, Watchdog, and Free Running Timer

These parts include POR logic, a WDT, and a 12-bit free-running timer. The POR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address 0x0000. The WDT is used to ensure that the microcontroller recovers after a period of inactivity. The firmware may become inactive for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs.

I2C and HAPI Interface

The microcontroller communicates with external electronics through the GPIO pins. An I2C compatible interface accommodates a 100 kHz serial link with an external device. There is also a HAPI to transfer data to an external device.

Timer

The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128 us and ms. The timer is used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read.

Interrupts

The microcontroller supports eleven maskable interrupts in the vectored interrupt controller. Interrupt sources include the 128 us bit 6 and ms bit 9 outputs from the free-running timer, five USB endpoints, the USB hub, the DAC port, the GPIO ports, and the I2C compatible master mode interface. The timer bits cause an interrupt if enabled when the bit toggles from LOW ‘0’ to HIGH The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller sends a packet to the USB host. The DAC ports have an additional level of masking that allows the user to select which DAC inputs causes a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs causes a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity is programmed for each GPIO port as part of the port configuration. The interrupt polarity can be rising edge ‘0’ to ‘1’ or falling edge ‘1’ to

The CY7C66013C and CY7C66113C include an integrated USB Serial Interface Engine SIE that supports the integrated peripherals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the hub two endpoints and a device address for a compound device three endpoints . The SIE allows the USB host to communicate with the hub and functions integrated into the microcontroller. The part includes a 1:4 hub repeater with one upstream port and four downstream ports. The USB Hub allows power management control of the downstream ports by using GPIO pins assigned by the user firmware. The user has the option of ganging the downstream ports together with a single pair of power management pins, or providing power management for each port with four pairs of power management pins.
Ordering Information
Ordering Code CY7C66013C-PVXC CY7C66113C-PVXC CY7C66113C-LFXC CY7C66113C-PVXCT CY7C66113C-XC CY7C66113C-LTXC CY7C66113C-LTXCT

PROM Size 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB

Package Type 48-pin 300-Mil SSOP 56-pin 300-Mil SSOP 56-pin QFN 56-pin 300-Mil SSOP Die 56-pin QFN 56-pin QFN

Operating Range Commercial

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Package Diagrams

CY7C66013C, CY7C66113C

Figure 48-Pin Shrunk Small Outline Package O48

Figure 56-Pin Shrunk Small Outline Package O56
51-85061-*C
51-85062-*C

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CY7C66013C, CY7C66113C

Figure 56-Pin QFN 8 x 8 MM LF56A
51-85144 *G

Page 56 of 59 [+] Feedback

CY7C66013C, CY7C66113C

Figure 56-QFN 8x8x0.9 mm EPad 6.1x6.1 mm
51-85187 *C

Page 57 of 59 [+] Feedback

CY7C66013C, CY7C66113C

Quad Flat Package No Leads QFN Package Design Notes

Electrical contact of the part to the Printed Circuit Board PCB is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper Cu fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the FX1 through the device’s metal paddle on the bottom side of the package. Heat from here, is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via. A via is a plated through hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process.

For further information on this package design please refer to the application note Surface Mount Assembly of AMKOR’s MicroLeadFrame MLF Technology. This application note can be downloaded from AMKOR’s website from the following URL 0902.pdf. The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc.

Figure 29 displays a cross sectional area underneath the package. The cross section is of only one via. The thickness of the solder paste template should be 5 mil. It is recommended that “No Clean” type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow.

Figure 58 is a plot of the solder mask pattern. This pad is thermally connected and is not electrically connected inside the chip. To minimize EMI, this pad should be connected to the ground plane of the circuit board.

Figure Cross Section of the Area Underneath the QFN Package

Cu Fill

Solder Mask

Cu Fill

PCB Material

PCB Material

Via hole for thermally connecting the QFN to the circuit board ground plane.

This figure only shows the top three layers of the circuit board Top Solder, PCB Dielectric, and the Ground Plane

Figure Plot of the Solder Mask White Area

Page 58 of 59 [+] Feedback

CY7C66013C, CY7C66113C

Document History Page

Document Title CY7C66013C, CY7C66113C Full Speed USB 12 Mbps Peripheral Controller with Integrated Hub Document Number 38-08024

ECN No.

Submission Date
Updated part number and ordering information. Added QFN Package Drawing and Design Notes. Corrected bit names in Figures 9-3, 9-4, 9-5, 9-8, 9-9, 9-10, 10-5, 16-1, 18-1, 18-2, 18-3, 18-6, 18-7, 18-9, Removed Hub Ports Force Low register address 0x52. Added HAPI to Interrupt Vector Number 11 in Table Corrected bit names in Section Corrected Units in Table for RUUP, RUDN, REXT, and ZO. Added DIE diagram and related information. Added HAPI to GPIO interrupt vector in Table 5-1 and figure 16-3
*C 1825466 See ECN TLY/PYRS Changed Title from "CY7C66013, CY7C66113 Full Speed USB 12 Mbps Peripheral Controller with Integrated Hub" to "CY7C66013C, CY7C66113C Full Speed USB 12 Mbps Peripheral Controller with Integrated Hub" Changed package description for CY7C66013C and CY7C66113C from -PVC to -PVXC
*D 2720540 06/18/09 DPT/AESA Added 56 QFN 8x8x1 mm package diagram and ordering information

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers
psoc.cypress.com clocks.cypress.com

Wireless Memories Image Sensors
wireless.cypress.com memory.cypress.com
image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

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[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C66113C-LFXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C66113C-LFXC 508136