CY7C1354C-166BZC

CY7C1354C-166BZC Datasheet

CY7C1354C, CY7C1356C

Part	Datasheet
CY7C1354C-166BZC	CY7C1354C-166BZC (pdf)

Related Parts	Information
CY7C1354C-166BZCT	CY7C1354C-166BZCT

PDF Datasheet Preview
CY7C1354C, CY7C1356C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture • Pin-compatible and Functionally equivalent to ZBT • Supports 250 MHz Bus Operations with Zero Wait States Available speed grades are 250, 200, and 166 MHz • Internally Self-timed Output Buffer Control to eliminate the need to use Asynchronous OE • Fully Registered Inputs and Outputs for Pipelined Operation • Byte Write capability • Single 3.3V Power Supply VDD • 3.3V or 2.5V I/O Power Supply VDDQ • Fast Clock-to-output Times ns for 250 MHz device • Clock Enable CEN Pin to suspend Operation • Synchronous Self-timed Writes • Available in Pb-free 100-Pin TQFP Package, Pb-free, and non Pb-free 119-Ball BGA Package and 165-Ball FBGA Package • IEEE JTAG-Compatible Boundary Scan • Burst Capability Linear or Interleaved Burst Order • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1354C and CY7C1356C[1] are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354C and CY7C1356C are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature greatly improves the throughput of data in systems that require frequent write/read transitions. The CY7C1354C and CY7C1356C are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects for CY7C1354C and for CY7C1356C and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. Logic Block 256K x 36 A0, A1, A MODE ADV/LD BW a BW b BW c BW d ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 A1 D1 Q1 A1' A0 D0 BURST Q0 A0' LOGIC ADV/LD WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY INPUT REGISTER 1 E O U T P U T D A T A O U T P U T Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code 166 CY7C1354C-166AXC CY7C1356C-166AXC CY7C1354C-166BGC CY7C1356C-166BGC CY7C1354C-166BZC CY7C1354C-166AXI CY7C1356C-166AXI 200 CY7C1354C-200AXC CY7C1354C-200BGC CY7C1354C-200AXI 250 CY7C1356C-250AXC Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85115 119-ball Grid Array 14 x 22 x mm 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85115 119-ball Grid Array 14 x 22 x mm 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free Operating Range Commercial Industrial Commercial Industrial Commercial Page 25 of 30 [+] Feedback CY7C1354C, CY7C1356C Package Diagrams Figure 100-Pin Thin Plastic Quad Flatpack 14X20X1.4 mm 100 1 81 80 R MIN. MAX. GAUGE PLANE 0° -7° REF. 30 31 0° MIN. R MIN. MAX. MIN. DETAIL A TYP. 51 50 12° ±1° 8X SEE DETAIL Changed TQFP pkg to Lead-free TQFP in Ordering Information section Added comment of Lead-free BG and BZ packages availability 284431 See ECN VBL Changed ISB1 and ISB3 from DC Characteristic table as follows ISB1 225 mA-> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA ISB3 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA Add BG and BZ pkg lead-free part numbers to ordering info section 320834 See ECN PCI Changed 225 MHz to 250 MHz Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Unshaded frequencies of 250, 200, 166 MHz in AC/DC Tables and Selection Guide Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to and °C/W respectively Changed ΘJA and ΘJC for BGA Package from 25 and 6 °C/W to and °C/W respectively Changed ΘJA and ΘJC for FBGA Package from 27 and 6 °C/W to and °C/W respectively Modified VOL, VOH test conditions Added Lead-Free product information Updated Ordering Information Table Changed from Preliminary to Final 351895 See ECN PCI Changed ISB2 from 35 to 40 mA Updated Ordering Information Table 377095 See ECN PCI Modified test condition in note# 15 from VDDQ < VDD to VDDQ VDD 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed three-state to tri-state. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Replaced Package Name column with Package Diagram in the Ordering Infor- mation table. 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. 2756340 08/26/2009 VKN/AESA Updated template Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Page 29 of 30 [+] Feedback CY7C1354C, CY7C1356C Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 30 of 30 No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C1354C, CY7C1356C
9-Mbit 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
• Pin-compatible and Functionally equivalent to ZBT
• Supports 250 MHz Bus Operations with Zero Wait States Available speed grades are 250, 200, and 166 MHz
• Internally Self-timed Output Buffer Control to eliminate the need to use Asynchronous OE
• Fully Registered Inputs and Outputs for Pipelined Operation
• Byte Write capability
• Single 3.3V Power Supply VDD
• 3.3V or 2.5V I/O Power Supply VDDQ
• Fast Clock-to-output Times
ns for 250 MHz device
• Clock Enable CEN Pin to suspend Operation
• Synchronous Self-timed Writes
• Available in Pb-free 100-Pin TQFP Package, Pb-free, and non Pb-free 119-Ball BGA Package and 165-Ball FBGA Package
• IEEE JTAG-Compatible Boundary Scan
• Burst Capability Linear or Interleaved Burst Order
• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1354C and CY7C1356C[1] are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354C and CY7C1356C are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature greatly improves the throughput of data in systems that require frequent write/read transitions. The CY7C1354C and CY7C1356C are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects for CY7C1354C and for CY7C1356C and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence.

Logic Block 256K x 36

A0, A1, A

MODE

ADV/LD

BW a BW b BW c BW d

ADDRESS REGISTER 0

WRITE ADDRESS REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

WRITE ADDRESS REGISTER 2

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

WRITE DRIVERS

MEMORY

ARRAY

INPUT REGISTER 1 E

O U T P U T

D A T A

O U T P U T
Ordering Information

The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
166 CY7C1354C-166AXC

CY7C1356C-166AXC

CY7C1354C-166BGC

CY7C1356C-166BGC

CY7C1354C-166BZC

CY7C1354C-166AXI

CY7C1356C-166AXI
200 CY7C1354C-200AXC

CY7C1354C-200BGC

CY7C1354C-200AXI
250 CY7C1356C-250AXC

Package Diagram

Part and Package Type
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
51-85115 119-ball Grid Array 14 x 22 x mm
51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85115 119-ball Grid Array 14 x 22 x mm 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free

Operating Range

Commercial

Industrial Commercial

Industrial Commercial

Page 25 of 30 [+] Feedback

CY7C1354C, CY7C1356C

Package Diagrams

Figure 100-Pin Thin Plastic Quad Flatpack 14X20X1.4 mm
100 1
81 80

R MIN. MAX.

GAUGE PLANE
0° -7°

REF.
30 31
0° MIN.

R MIN. MAX.

MIN.

DETAIL A

TYP.
51 50
12° ±1° 8X

SEE DETAIL
Changed TQFP pkg to Lead-free TQFP in Ordering Information section

Added comment of Lead-free BG and BZ packages availability
284431 See ECN

VBL Changed ISB1 and ISB3 from DC Characteristic table as follows

ISB1 225 mA-> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA

ISB3 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA
Add BG and BZ pkg lead-free part numbers to ordering info section
320834 See ECN

PCI Changed 225 MHz to 250 MHz

Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard

Unshaded frequencies of 250, 200, 166 MHz in AC/DC Tables and Selection

Guide

Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to and °C/W respectively

Changed ΘJA and ΘJC for BGA Package from 25 and 6 °C/W to and °C/W respectively

Changed ΘJA and ΘJC for FBGA Package from 27 and 6 °C/W to and °C/W respectively

Modified VOL, VOH test conditions Added Lead-Free product information
Updated Ordering Information Table

Changed from Preliminary to Final
351895 See ECN

PCI Changed ISB2 from 35 to 40 mA
Updated Ordering Information Table
377095 See ECN

PCI Modified test condition in note# 15 from VDDQ < VDD to VDDQ VDD
408298 See ECN

RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court” Changed three-state to tri-state.

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering Infor-
mation table.
501793 See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

Switching Characteristics table.
Updated the Ordering Information table.
2756340 08/26/2009 VKN/AESA Updated template

Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information.

Page 29 of 30 [+] Feedback

CY7C1354C, CY7C1356C

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 30 of 30

No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1354C-166BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1354C-166BZC 507975