CY7C63413-PVC

CY7C63413-PVC Datasheet

CY7C63411/12/13 CY7C63511/12/13

Part	Datasheet
CY7C63413-PVC	CY7C63413-PVC (pdf)

Related Parts	Information
CY7C63513-PVC	CY7C63513-PVC

PDF Datasheet Preview
fax id 3404 CY7C63411/12/13 CY7C63511/12/13 CY7C63411/12/13 CY7C63511/12/13 Low-Speed, High I/O, Mbps USB Controller CY7C63411/12/13 CY7C63511/12/13 TABLE OF CONTENTS FEATURES 5 FUNCTIONAL OVERVIEW 6 PIN ASSIGNMENTS 8 PROGRAMMING MODEL 8 14-bit Program Counter PC 8-bit Accumulator A 8-bit Index Register X 8-bit Program Stack Pointer PSP 8-bit Data Stack Pointer DSP 9 Address Modes 9 Data 9 Direct 9 Indexed 9 INSTRUCTION SET SUMMARY 10 MEMORY ORGANIZATION 11 Program Memory Organization 11 Data Memory Organization 12 I/O Register Summary 13 CLOCKING 14 RESET 14 Power-On Reset POR 14 Watch Dog Reset WDR 15 GENERAL PURPOSE I/O PORTS 15 GPIO Interrupt Enable Ports 16 GPIO Configuration Port 16 DAC PORT 17 DAC Port Interrupts 18 DAC Isink Registers 18 USB SERIAL INTERFACE ENGINE SIE 18 USB Enumeration 19 PS/2 Operation 19 USB Port Status and Control 19 USB DEVICE 20 USB Ports 20 Device Endpoints 3 20 12-BIT FREE-RUNNING TIMER 21 Timer LSB 21 Timer MSB 21 PROCESSOR STATUS AND CONTROL REGISTER 22 CY7C63411/12/13 CY7C63511/12/13 TABLE OF CONTENTS continued INTERRUPTS 22 Interrupt Vectors 23 Interrupt Latency 23 USB Bus Reset Interrupt 23 Timer Interrupt 24 USB Endpoint Interrupts 24 DAC Interrupt 24 GPIO Interrupt 24 TRUTH TABLES 24 ABSOLUTE MAXIMUM RATINGS 27 DC CHARACTERISTICS 28 SWITCHING CHARACTERISTICS 29 ORDERING INFORMATION 31 PACKAGE DIAGRAMS 32 CY7C63411/12/13 CY7C63511/12/13 LIST OF FIGURES Figure Program Memory Space with Interrupt Vector Table 11 Figure Clock Oscillator On-chip Circuit 14 Figure Watch Dog Reset WDR 15 Figure Block Diagram of a GPIO Line 15 Figure Port 0 Data 0x00h read/write 16 Figure Port 1 Data 0x01h read/write 16 Figure Port 2 Data 0x02h read/write 16 Figure Port 3 Data 0x03h read/write 16 Figure Port 0 Interrupt Enable 0x04h write only 16 Figure Port 1 Interrupt Enable 0x05h write only 16 Figure Port 2 Interrupt Enable 0x06h write only 16 Figure Port 3 Interrupt Enable 0x07h write only 16 Figure GPIO Configuration Register 0x08h write only 17 Figure Block Diagram of DAC Port 17 Figure DAC Port Data 0x30h read/write 18 Figure DAC Port Interrupt Enable 0x31h write only 18 Figure DAC Port Interrupt Polarity 0x32h write only 18 Figure DAC Port Isink 0x38h to 0x3Fh write only 18 Figure USB Status and Control Register 0x1Fh 19 Figure USB Device Address Register 0x10h read/write 20 Figure USB Device EPA0 Mode Register 0x12h read/write 20 Figure USB Device Endpoint Mode Registers 0x14h, 0x16h read/write 20 Figure USB Device Counter Registers 0x11h, 0x13h, 0x15h read/write 21 Figure Timer Register 0x24h read only 21 Figure Timer Register 0x25h read only 21 Figure Timer Block Diagram 21 Figure Processor Status and Control Register 0xFFh 22 Figure Global Interrupt Enable Register 0x20h read/write 22 Figure USB End Point Interrupt Enable Register 0x21h read/write 23 Figure Clock Timing 29 Figure USB Data Signal Timing 30 Figure Receiver Jitter Tolerance 30 Figure Differential to EOP Transition Skew and EOP Width 30 Figure Differential Data Jitter 31 LIST OF TABLES Table I/O Register Summary 13 Table Interrupt Vector Assignments 23 Table USB Register Mode Encoding 24 Table Decode table forTable 16-3 “Details of Modes for Differing Traffic Conditions” Table Details of Modes for Differing Traffic Conditions 26 CY7C63411/12/13 CY7C63511/12/13 • Low-cost solution for low-speed applications with high I/O requirements such as keyboards, keyboards with integrated pointing device, gamepads, and many others. • USB Specification Compliance Conforms to USB Specification, Version Conforms to USB HID Specification, Version Supports 1 device address and 3 data endpoints Integrated USB transceiver • 8-bit RISC microcontroller Harvard architecture 6 MHz external ceramic resonator 12 MHz internal CPU clock • Internal memory 256 bytes of RAM 4 Kbytes of EPROM CY7C63411, CY7C63511 6 Kbytes of EPROM CY7C63412, CY7C63512 8 Kbytes of EPROM CY7C63413, CY7C63513 • Interface can auto-configure to operate as PS2 or USB • I/O port 24 General Purpose I/O GPIO pins Port 0 to 2 capable of sinking 7 mA per pin typical Eight GPIO pins Port 3 capable of sinking 12 mA per pin typical which can drive LEDs Higher current drive is available by connecting multiple GPIO pins together to drive an common output Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs The CY7C63511/12/1 has an additional eight I/O pins on a DAC port which has programmable current sink outputs Maskable interrupts on all I/O pins • 12-bit free-running timer with one microsecond clock ticks • Watchdog timer WDT • Internal power-on reset POR • Improved output drivers to reduce EMI • Operating voltage from 4.0V to 5.5VDC • Operating temperature from 0 to 70 degrees Celsius • CY7C63411/12/13 available in 40-pin PDIP, 48-pin SSOP for production • CY7C63411/12/13 available in 40-pin Windowed CerDIP, 48-pin Windowed SideBraze for program development • CY7C63511/12/13 available in 48-pin SSOP packages for production • CY7C63511/12/13 available in 48-pin Windowed SideBraze for program development • Industry standard programmer support CY7C63411/12/13 CY7C63511/12/13 Functional Overview The CY7C63411/12/13 and CY7C63511/12/13 are 8-bit RISC One Time Programmable OTP microcontrollers. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. The CY7C63411/12/13 features 32 general purpose I/O GPIO pins to support USB and other applications. The I/O pins are grouped into four ports Port 0 to 3 where each port can be configured as inputs with internal pull-ups, open drain outputs, o r traditional CMOS outputs. 24 GPIO pins Ports 0 to 2 are rated at 7 mA typical sink current. There are 8 GPIO pins Port 3 which are rated at 12 mA typical sink current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector. The CY7C63511/12/13 features an additional 8 I/O pins in the DAC port. Every DAC pin includes an integrated 14-Kohm pull-up resistor. When a “1” is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven high by the internal pull-up resistor. When a “0” is written to a DAC I/O pin, the internal pull-up is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin can be used as an input with an internal pull-up by writing a “1” to the pin. The sink current for each DAC I/O pin can be individually programmed to one of sixteen values using dedicated Isink registers. DAC bits [1:0] can be used as high current outputs with a programmable sink current range of to 16 mA typical . DAC bits [7:2] have a programmable current sink range of to mA typical . Again, multiple DAC pins can be connected together to drive a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the microcontroller and the interrupt polarity for each DAC I/O pin is individually programmable. The DAC port interrupts share a separate “DAC” interrupt vector. The Cypress microcontrollers use an external 6 MHz ceramic resonator to provide a reference to an internal clock generator. This clock generator reduces the clock-related noise emissions EMI . The clock generator provides the 6 and 12 MHz clocks that remain internal to the microcontroller. The CY7C63411/12/13 and CY7C63511/12/13 are offered with three EPROM options to maximize flexibility and minimize cost. The CY7C63411 and CY7C63511 have 4 Kilobytes of EPROM. The CY7C63412 and CY7C63512 have 6 Kilobytes of EPROM. The CY7C63413 and CY7C63513 have 8 Kilobytes of EPROM. These parts include power-on reset logic, a watchdog timer, a vectored interrupt controller, and a 12-bit free-running timer. The power-on reset POR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000h. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The firmware can get stalled for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. The firmware should clear the watchdog timer periodically. If the watchdog timer is not cleared for approximately 8 ms, the microcontroller will generate a hardware watchdog reset. The microcontroller supports 8 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128 microsecond and ms outputs from the free-running timer, three USB endpoints, the DAC port, and the GPIO ports. The timer bits cause an interrupt if enabled when the bit toggles from low “0” to high The USB endpoints interrupt after either the USB host or the USB controller sends a packet to the USB. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be either rising edge “0” to “1” or falling edge “1” to The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above 128 µsec and ms . The timer can be used to measure the duration of an event under firmware control by reading the timer twice once at the start of the event, and once after the event is complete. The difference between the two readings indicates the duration of the event measured in microseconds. The upper 4 bits of the timer are latched into an internal register when the firmware reads the lower 8 bits. A read from the upper 4 bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to attempt to compensate if the upper 4 bits happened to increment right after the lower 8 bits are read. The CY7C63411/12/13 and CY7C63511/12/13 include an integrated USB serial interface engine SIE that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. Finally, the CY7C63411/12/13 and CY7C63511/12/13 support PS/2 operation. With appropriate firmware the D+ and USB pins can also be used as PS/2 clock and data signals. Products utilizing these devices can be used for USB and/or PS/2 operation with appropriate firmware. Logic Block Diagram 6 MHz ceramic resonator 12 MHz 6 MHz 12 MHz 8-bit CPU USB Transceiver EPROM 4/6/8 Kbyte USB SIE RAM 256 byte Interrupt Controller CY7C63411/12/13 CY7C63511/12/13 D+ USB PS/2 PORT Pin Configurations CY7C63511/12/13 48-pin SSOP 48-pin SideBraze CY7C63411/12/13 48-pin SSOP 48-pin SideBraze D+ 1 2 P3[7] 3 P3[5] 4 P3[3] 5 P3[1] 6 P2[7] 7 P2[5] 8 P2[3] 9 P2[1] 10 P1[7] 11 P1[5] 12 P1[3] 13 P1[1] 14 DAC[7] 15 DAC[5] 16 P0[7] 17 P0[5] 18 P0[3] 19 P0[1] 20 DAC[3] 21 DAC[1] 22 VPP 23 Vss 24 48 VCC 47 Vss 46 P3[6] 45 P3[4] 44 P3[2] 43 P3[0] 42 P2[6] 41 P2[4] 40 P2[2] 39 P2[0] 38 P1[6] 37 P1[4] 36 P1[2] 35 P1[0] 34 DAC[6] 33 DAC[4] 32 P0[6] 31 P0[4] 30 P0[2] 29 P0[0] 28 DAC[2] 27 DAC[0] 26 XTALOUT 25 XTALIN D+ 1 2 P3[7] 3 P3[5] 4 P3[3] 5 P3[1] 6 P2[7] 7 P2[5] 8 P2[3] 9 P2[1] 10 P1[7] 11 P1[5] 12 P1[3] 13 P1[1] 14 NC 15 NC 16 P0[7] 17 P0[5] 18 P0[3] 19 P0[1] 20 NC 21 NC 22 VPP 23 Vss 24 48 VCC 47 Vss 46 P3[6] 45 P3[4] 44 P3[2] 43 P3[0] 42 P2[6] 41 P2[4] 40 P2[2] 39 P2[0] 38 P1[6] 37 P1[4] 36 P1[2] 35 P1[0] 34 NC 33 NC 32 P0[6] 31 P0[4] 30 P0[2] 29 P0[0] 28 NC 27 NC 26 XTALOUT 25 XTALIN TOP VIEW 8-bit Bus 12-bit Timer Watchdog Timer Ordering Information Ordering Code CY7C63411-PC EPROM Size Package Name CY7C63411-PVC CY7C63412-PC CY7C63412-PVC CY7C63413-PC CY7C63413-PVC CY7C63413-WC 8 KB 8 KB 8 KB P17 O48 W18 CY7C63413-WVC CY7C63511-PVC CY7C63512-PVC CY7C63513-PVC CY7C63513-WVC 8 KB 8 KB O48 W48 Package Type Operating Range 40-Pin 600-Mil PDIP Commercial 48-Lead Shrunk Small Outline Package Commercial 40-Pin 600-Mil PDIP Commercial 48-Lead Shrunk Small Outline Package Commercial 40-Pin 600-Mil PDIP Commercial 48-Lead Shrunk Small Outline Package Commercial 40-Pin 600-Mil Windowed CerDIP Commercial 48-Pin Windowed SideBraze Commercial 48-Lead Shrunk Small Outline Package Commercial 48-Lead Shrunk Small Outline Package Commercial 48-Lead Shrunk Small Outline Package Commercial 48-Pin Windowed SideBraze Commercial Document # 38-00589-D Package Diagrams 48-Lead Shrunk Small Outline Package O48 CY7C63411/12/13 CY7C63511/12/13 40-Lead 600-Mil Molded DIP P17 Package Diagrams continued 40-Lead 600-Mil Windowed CerDIP W18 CY7C63411/12/13 CY7C63511/12/13 48-Lead 600-Mil Windowed Sidebraze W48

PDF Datasheet Preview

fax id 3404

CY7C63411/12/13 CY7C63511/12/13

CY7C63411/12/13 CY7C63511/12/13 Low-Speed, High I/O, Mbps USB Controller

CY7C63411/12/13 CY7C63511/12/13

TABLE OF CONTENTS

FEATURES 5 FUNCTIONAL OVERVIEW 6 PIN ASSIGNMENTS 8 PROGRAMMING MODEL 8 14-bit Program Counter PC 8-bit Accumulator A 8-bit Index Register X 8-bit Program Stack Pointer PSP 8-bit Data Stack Pointer DSP 9 Address Modes 9

Data 9 Direct 9 Indexed 9 INSTRUCTION SET SUMMARY 10 MEMORY ORGANIZATION 11 Program Memory Organization 11 Data Memory Organization 12 I/O Register Summary 13 CLOCKING 14 RESET 14 Power-On Reset POR 14 Watch Dog Reset WDR 15 GENERAL PURPOSE I/O PORTS 15 GPIO Interrupt Enable Ports 16 GPIO Configuration Port 16 DAC PORT 17 DAC Port Interrupts 18 DAC Isink Registers 18 USB SERIAL INTERFACE ENGINE SIE 18 USB Enumeration 19 PS/2 Operation 19 USB Port Status and Control 19 USB DEVICE 20 USB Ports 20 Device Endpoints 3 20 12-BIT FREE-RUNNING TIMER 21 Timer LSB 21 Timer MSB 21 PROCESSOR STATUS AND CONTROL REGISTER 22

CY7C63411/12/13 CY7C63511/12/13

TABLE OF CONTENTS continued

INTERRUPTS 22 Interrupt Vectors 23 Interrupt Latency 23
USB Bus Reset Interrupt 23 Timer Interrupt 24 USB Endpoint Interrupts 24 DAC Interrupt 24 GPIO Interrupt 24 TRUTH TABLES 24 ABSOLUTE MAXIMUM RATINGS 27 DC CHARACTERISTICS 28 SWITCHING CHARACTERISTICS 29 ORDERING INFORMATION 31 PACKAGE DIAGRAMS 32

CY7C63411/12/13 CY7C63511/12/13

LIST OF FIGURES

Figure Program Memory Space with Interrupt Vector Table 11 Figure Clock Oscillator On-chip Circuit 14 Figure Watch Dog Reset WDR 15 Figure Block Diagram of a GPIO Line 15 Figure Port 0 Data 0x00h read/write 16 Figure Port 1 Data 0x01h read/write 16 Figure Port 2 Data 0x02h read/write 16 Figure Port 3 Data 0x03h read/write 16 Figure Port 0 Interrupt Enable 0x04h write only 16 Figure Port 1 Interrupt Enable 0x05h write only 16 Figure Port 2 Interrupt Enable 0x06h write only 16 Figure Port 3 Interrupt Enable 0x07h write only 16 Figure GPIO Configuration Register 0x08h write only 17 Figure Block Diagram of DAC Port 17 Figure DAC Port Data 0x30h read/write 18 Figure DAC Port Interrupt Enable 0x31h write only 18 Figure DAC Port Interrupt Polarity 0x32h write only 18 Figure DAC Port Isink 0x38h to 0x3Fh write only 18 Figure USB Status and Control Register 0x1Fh 19 Figure USB Device Address Register 0x10h read/write 20 Figure USB Device EPA0 Mode Register 0x12h read/write 20 Figure USB Device Endpoint Mode Registers 0x14h, 0x16h read/write 20 Figure USB Device Counter Registers 0x11h, 0x13h, 0x15h read/write 21 Figure Timer Register 0x24h read only 21 Figure Timer Register 0x25h read only 21 Figure Timer Block Diagram 21 Figure Processor Status and Control Register 0xFFh 22 Figure Global Interrupt Enable Register 0x20h read/write 22 Figure USB End Point Interrupt Enable Register 0x21h read/write 23 Figure Clock Timing 29 Figure USB Data Signal Timing 30 Figure Receiver Jitter Tolerance 30 Figure Differential to EOP Transition Skew and EOP Width 30 Figure Differential Data Jitter 31

LIST OF TABLES

Table I/O Register Summary 13 Table Interrupt Vector Assignments 23 Table USB Register Mode Encoding 24 Table Decode table forTable 16-3 “Details of Modes for Differing Traffic Conditions” Table Details of Modes for Differing Traffic Conditions 26

CY7C63411/12/13 CY7C63511/12/13
• Low-cost solution for low-speed applications with high I/O requirements such as keyboards, keyboards with integrated pointing device, gamepads, and many others.
• USB Specification Compliance Conforms to USB Specification, Version Conforms to USB HID Specification, Version Supports 1 device address and 3 data endpoints Integrated USB transceiver
• 8-bit RISC microcontroller Harvard architecture 6 MHz external ceramic resonator 12 MHz internal CPU clock
• Internal memory 256 bytes of RAM 4 Kbytes of EPROM CY7C63411, CY7C63511 6 Kbytes of EPROM CY7C63412, CY7C63512 8 Kbytes of EPROM CY7C63413, CY7C63513
• Interface can auto-configure to operate as PS2 or USB
• I/O port
24 General Purpose I/O GPIO pins Port 0 to 2 capable of sinking 7 mA per pin typical Eight GPIO pins Port 3 capable of sinking 12 mA per pin typical which can drive LEDs Higher current drive is available by connecting multiple GPIO pins together to drive an common output Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs The CY7C63511/12/1 has an additional eight I/O pins on a DAC port which has programmable current sink outputs Maskable interrupts on all I/O pins
• 12-bit free-running timer with one microsecond clock ticks
• Watchdog timer WDT
• Internal power-on reset POR
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.5VDC
• Operating temperature from 0 to 70 degrees Celsius
• CY7C63411/12/13 available in 40-pin PDIP, 48-pin SSOP for production
• CY7C63411/12/13 available in 40-pin Windowed CerDIP, 48-pin Windowed SideBraze for program development
• CY7C63511/12/13 available in 48-pin SSOP packages for production
• CY7C63511/12/13 available in 48-pin Windowed SideBraze for program development
• Industry standard programmer support

CY7C63411/12/13

CY7C63511/12/13

Functional Overview

The CY7C63411/12/13 and CY7C63511/12/13 are 8-bit RISC One Time Programmable OTP microcontrollers. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. The CY7C63411/12/13 features 32 general purpose I/O GPIO pins to support USB and other applications. The I/O pins are grouped into four ports Port 0 to 3 where each port can be configured as inputs with internal pull-ups, open drain outputs, o r traditional CMOS outputs. 24 GPIO pins Ports 0 to 2 are rated at 7 mA typical sink current. There are 8 GPIO pins Port 3 which are rated at 12 mA typical sink current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector. The CY7C63511/12/13 features an additional 8 I/O pins in the DAC port. Every DAC pin includes an integrated 14-Kohm pull-up resistor. When a “1” is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven high by the internal pull-up resistor. When a “0” is written to a DAC I/O pin, the internal pull-up is disabled and the output pin provides the programmed amount of sink current. A DAC I/O pin can be used as an input with an internal pull-up by writing a “1” to the pin. The sink current for each DAC I/O pin can be individually programmed to one of sixteen values using dedicated Isink registers. DAC bits [1:0] can be used as high current outputs with a programmable sink current range of to 16 mA typical . DAC bits [7:2] have a programmable current sink range of to mA typical . Again, multiple DAC pins can be connected together to drive a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the microcontroller and the interrupt polarity for each DAC I/O pin is individually programmable. The DAC port interrupts share a separate “DAC” interrupt vector. The Cypress microcontrollers use an external 6 MHz ceramic resonator to provide a reference to an internal clock generator. This clock generator reduces the clock-related noise emissions EMI . The clock generator provides the 6 and 12 MHz clocks that remain internal to the microcontroller. The CY7C63411/12/13 and CY7C63511/12/13 are offered with three EPROM options to maximize flexibility and minimize cost. The CY7C63411 and CY7C63511 have 4 Kilobytes of EPROM. The CY7C63412 and CY7C63512 have 6 Kilobytes of EPROM. The CY7C63413 and CY7C63513 have 8 Kilobytes of EPROM. These parts include power-on reset logic, a watchdog timer, a vectored interrupt controller, and a 12-bit free-running timer. The power-on reset POR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000h. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The firmware can get stalled for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs. The firmware should clear the watchdog timer periodically. If the watchdog timer is not cleared for approximately 8 ms, the microcontroller will generate a hardware watchdog reset. The microcontroller supports 8 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128 microsecond and ms outputs from the free-running timer, three USB endpoints, the DAC port, and the GPIO ports. The timer bits cause an interrupt if enabled when the bit toggles from low “0” to high The USB endpoints interrupt after either the USB host or the USB controller sends a packet to the USB. The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity can be either rising edge “0” to “1” or falling edge “1” to The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above 128 µsec and ms . The timer can be used to measure the duration of an event under firmware control by reading the timer twice once at the start of the event, and once after the event is complete. The difference between the two readings indicates the duration of the event measured in microseconds. The upper 4 bits of the timer are latched into an internal register when the firmware reads the lower 8 bits. A read from the upper 4 bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to attempt to compensate if the upper 4 bits happened to increment right after the lower 8 bits are read. The CY7C63411/12/13 and CY7C63511/12/13 include an integrated USB serial interface engine SIE that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. Finally, the CY7C63411/12/13 and CY7C63511/12/13 support PS/2 operation. With appropriate firmware the D+ and USB pins can also be used as PS/2 clock and data signals. Products utilizing these devices can be used for USB and/or PS/2 operation with appropriate firmware.

Logic Block Diagram
6 MHz ceramic resonator
12 MHz 6 MHz
12 MHz 8-bit CPU

USB Transceiver

EPROM 4/6/8 Kbyte

USB SIE

RAM 256 byte

Interrupt Controller

CY7C63411/12/13 CY7C63511/12/13

D+ USB

PS/2 PORT

Pin Configurations

CY7C63511/12/13 48-pin SSOP 48-pin SideBraze

CY7C63411/12/13 48-pin SSOP
48-pin SideBraze

D+ 1 2 P3[7] 3 P3[5] 4 P3[3] 5 P3[1] 6 P2[7] 7 P2[5] 8 P2[3] 9 P2[1] 10 P1[7] 11 P1[5] 12 P1[3] 13 P1[1] 14 DAC[7] 15 DAC[5] 16 P0[7] 17 P0[5] 18 P0[3] 19 P0[1] 20 DAC[3] 21 DAC[1] 22 VPP 23 Vss 24
48 VCC 47 Vss 46 P3[6] 45 P3[4] 44 P3[2] 43 P3[0] 42 P2[6] 41 P2[4] 40 P2[2] 39 P2[0] 38 P1[6] 37 P1[4] 36 P1[2] 35 P1[0] 34 DAC[6] 33 DAC[4] 32 P0[6] 31 P0[4] 30 P0[2] 29 P0[0] 28 DAC[2] 27 DAC[0] 26 XTALOUT 25 XTALIN

D+ 1 2 P3[7] 3 P3[5] 4 P3[3] 5 P3[1] 6 P2[7] 7 P2[5] 8 P2[3] 9 P2[1] 10 P1[7] 11 P1[5] 12 P1[3] 13 P1[1] 14 NC 15 NC 16 P0[7] 17 P0[5] 18 P0[3] 19 P0[1] 20 NC 21 NC 22 VPP 23 Vss 24
48 VCC 47 Vss 46 P3[6] 45 P3[4] 44 P3[2] 43 P3[0] 42 P2[6] 41 P2[4] 40 P2[2] 39 P2[0] 38 P1[6] 37 P1[4] 36 P1[2] 35 P1[0] 34 NC 33 NC 32 P0[6] 31 P0[4] 30 P0[2] 29 P0[0] 28 NC 27 NC 26 XTALOUT 25 XTALIN

TOP VIEW
8-bit Bus
12-bit Timer

Watchdog Timer
Ordering Information
Ordering Code CY7C63411-PC

EPROM Size

Package Name

CY7C63411-PVC CY7C63412-PC CY7C63412-PVC

CY7C63413-PC CY7C63413-PVC CY7C63413-WC
8 KB 8 KB 8 KB

P17 O48 W18

CY7C63413-WVC

CY7C63511-PVC CY7C63512-PVC

CY7C63513-PVC CY7C63513-WVC
8 KB 8 KB

O48 W48

Package Type

Operating Range
40-Pin 600-Mil PDIP

Commercial
48-Lead Shrunk Small Outline Package Commercial
40-Pin 600-Mil PDIP

Commercial
48-Lead Shrunk Small Outline Package Commercial
40-Pin 600-Mil PDIP

Commercial
48-Lead Shrunk Small Outline Package Commercial
40-Pin 600-Mil Windowed CerDIP

Commercial
48-Pin Windowed SideBraze

Commercial
48-Lead Shrunk Small Outline Package Commercial
48-Lead Shrunk Small Outline Package Commercial
48-Lead Shrunk Small Outline Package Commercial
48-Pin Windowed SideBraze

Commercial

Document # 38-00589-D

Package Diagrams
48-Lead Shrunk Small Outline Package O48

CY7C63411/12/13 CY7C63511/12/13
40-Lead 600-Mil Molded DIP P17

Package Diagrams continued
40-Lead 600-Mil Windowed CerDIP W18

CY7C63411/12/13 CY7C63511/12/13
48-Lead 600-Mil Windowed Sidebraze W48

More datasheets: B65716L0000R087 | B65716L0000R065 | B65738L0000R087 | B65738L0590J087 | 2458 | WP0612-760 | WP1112-760 | CY29773AXIT | CY29773AXI | CY7C63513-PVC

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C63413-PVC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C63413-PVC 508123