CY29773AXIT

CY29773AXIT Datasheet

CY29773

Part	Datasheet
CY29773AXIT	CY29773AXIT (pdf)

Related Parts	Information
CY29773AXI	CY29773AXI

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CY29773 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer • 6 ps typical period jitter • Output frequency range MHz to 200 MHz • Input frequency range MHz to 125 MHz • 2.5V or 3.3V operation • Split 2.5V/3.3V outputs • 12 Clock outputs drive up to 24 clock lines • One feedback output • Three reference clock inputs LVPECL or LVCMOS • Phase-locked loop PLL bypass mode • Spread Aware • Output enable/disable • Pin-compatible with MPC9773 and MPC973 • Industrial temperature range to +85°C • 52-pin 1.0-mm TQFP package The CY29773 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29773 features one LVPECL and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL A:C settings see Table Function Table Configuration Controls . These dividers allow output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and Each LVCMOS-compatible output can drive series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces, giving the device an effective fanout of The PLL is ensured stable, given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies, from 8 MHz to 200 MHz. For normal operation, the external feedback input FB_IN is connected to the feedback output FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider see Table Frequency Table . When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Block Diagram Pin Configuration PECL_CLK# VCO_SEL PLL_EN REF_SEL TCLK0 TCLK1 TCLK_SEL FB_IN Phase Detector FB_SEL2 MR#/OE Power-On Reset SELA 0,1 SELB 0,1 SELC 0,1 FB_SEL 0,1 SCLK SDATA INV_CLK /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 Sync Pulse Data Generator 0 /2 1 Output Disable Circuitry Sync Frz Sync Frz Sync Frz Sync Frz Sync Frz Sync Frz SELB1 SELB0 SELA1 SELA0 QA3 VDDQA Ordering Information Part Number CY29773AI CY29773AIT Lead-free CY29773AXI CY29773AXIT Package Type 52-pin TQFP 52-pin TQFP Tape and Reel 52-pin TQFP 52-pin TQFP Tape and Reel Product Flow Industrial, to +85°C Industrial, to 85°C Industrial, to +85°C Industrial, to 85°C Page 11 of 13 Package Drawing and Dimension 52-Lead Thin Plastic Quad Flat Pack 10 x 10 x mm A52B CY29773 51-85158-** Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Page 12 of 13 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Document History Page Document Title:CY29773 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Document Number 38-07573 Description of Change 129007 09/02/03 RGL New Data Sheet 404290 See ECN Added pb-free devices added typical data for period jitter CY29773 Page 13 of 13

PDF Datasheet Preview

CY29773
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
• 6 ps typical period jitter
• Output frequency range MHz to 200 MHz
• Input frequency range MHz to 125 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• 12 Clock outputs drive up to 24 clock lines
• One feedback output
• Three reference clock inputs LVPECL or LVCMOS
• Phase-locked loop PLL bypass mode
• Spread Aware
• Output enable/disable
• Pin-compatible with MPC9773 and MPC973
• Industrial temperature range to +85°C
• 52-pin 1.0-mm TQFP package

The CY29773 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications.

The CY29773 features one LVPECL and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL A:C settings see Table Function Table Configuration Controls . These dividers allow output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and Each LVCMOS-compatible output can drive series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces, giving the device an effective fanout of

The PLL is ensured stable, given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies, from 8 MHz to 200 MHz. For normal operation, the external feedback input FB_IN is connected to the feedback output FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider see Table Frequency Table .

When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.

Block Diagram

Pin Configuration

PECL_CLK#

VCO_SEL PLL_EN

REF_SEL

TCLK0

TCLK1

TCLK_SEL

FB_IN

Phase Detector

FB_SEL2

MR#/OE

Power-On Reset

SELA 0,1

SELB 0,1

SELC 0,1

FB_SEL 0,1

SCLK SDATA

INV_CLK
/4, /6, /8, /12 /4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10 Sync Pulse

Data Generator
0 /2 1

Output Disable

Circuitry

Sync Frz

Sync Frz

Sync Frz

Sync Frz

Sync Frz

Sync Frz

SELB1 SELB0 SELA1 SELA0

QA3 VDDQA
Ordering Information

Part Number CY29773AI CY29773AIT Lead-free CY29773AXI CY29773AXIT

Package Type 52-pin TQFP 52-pin TQFP Tape and Reel
52-pin TQFP 52-pin TQFP Tape and Reel

Product Flow Industrial, to +85°C Industrial, to 85°C

Industrial, to +85°C Industrial, to 85°C

Page 11 of 13

Package Drawing and Dimension
52-Lead Thin Plastic Quad Flat Pack 10 x 10 x mm A52B

CY29773
51-85158-**

Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 12 of 13

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Document History Page

Document Title:CY29773 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Document Number 38-07573

Description of Change
129007 09/02/03

RGL New Data Sheet
404290 See ECN

Added pb-free devices added typical data for period jitter

CY29773

Page 13 of 13

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Datasheet ID: CY29773AXIT 507741