CY7C63221A-PXC

CY7C63221A-PXC Datasheet

enCoRe USB CY7C63221/31A

Part	Datasheet
CY7C63221A-PXC	CY7C63221A-PXC (pdf)

Related Parts	Information
CY7C63231A-SC	CY7C63231A-SC
CY7C63221A-PC	CY7C63221A-PC
CY7C63231A-SXCT	CY7C63231A-SXCT
CY7C63231A-SXC	CY7C63231A-SXC
CY7C63231A-PXC	CY7C63231A-PXC

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enCoRe USB CY7C63221/31A CY7C63221A/31A enCoRe USB Low-speed USB Peripheral Controller Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 [+] Feedback enCoRe USB CY7C63221/31A TABLE OF CONTENTS FEATURES 5 FUNCTIONAL OVERVIEW 6 enCoRe USB - The New USB Standard 6 LOGIC BLOCK DIAGRAM 7 PIN CONFIGURATIONS 7 PIN ASSIGNMENTS 7 PROGRAMMING MODEL 8 Program Counter PC 8-bit Accumulator A 8-bit Index Register X 8-bit Program Stack Pointer PSP 8-bit Data Stack Pointer DSP 9 Address Modes 9 Data 9 Direct 9 Indexed 9 INSTRUCTION SET SUMMARY 10 MEMORY ORGANIZATION 11 Program Memory Organization 11 Data Memory Organization 12 I/O Register Summary 13 CLOCKING 14 Internal/External Oscillator Operation 15 External Oscillator 15 RESET 16 Low-voltage Reset LVR 16 Brown-out Reset BOR 16 Watchdog Reset WDR 17 SUSPEND MODE 17 Clocking Mode on Wake-up from Suspend 18 Wake-up Timer 18 GENERAL PURPOSE I/O PORTS 19 Auxiliary Input Port 21 USB SERIAL INTERFACE ENGINE SIE 22 USB Enumeration 23 USB Port Status and Control 23 USB DEVICE 25 USB Address Register 25 USB Control Endpoint 25 USB Non-Control Endpoints 26 USB Endpoint Counter Registers Page 2 of 50 [+] Feedback enCoRe USB CY7C63221/31A USB REGULATOR OUTPUT 27 PS/2 OPERATION 28 12-BIT FREE-RUNNING TIMER 28 PROCESSOR STATUS AND CONTROL REGISTER 29 INTERRUPTS 31 Interrupt Vectors 31 Interrupt Latency 32 Interrupt Sources 32 USB MODE TABLES 36 REGISTER SUMMARY 41 ABSOLUTE MAXIMUM RATINGS 42 DC CHARACTERISTICS 42 SWITCHING CHARACTERISTICS 44 ORDERING INFORMATION 47 PACKAGE DIAGRAMS 47 Page 3 of 50 [+] Feedback enCoRe USB CY7C63221/31A LIST OF FIGURES Figure Program Memory Space with Interrupt Vector Table 11 Figure Clock Oscillator On-chip Circuit 14 Figure Clock Configuration Register Address 0xF8 14 Figure Watchdog Reset WDR, Address 0x26 17 Figure Block Diagram of GPIO Port one pin shown 19 Figure Port 0 Data Address 0x00 19 Figure Port 1 Data Address 0x01 20 Figure GPIO Port 0 Mode0 Register Address 0x0A 20 Figure GPIO Port 0 Mode1 Register Address 0x0B 20 Figure GPIO Port 1 Mode0 Register Address 0x0C 20 Figure GPIO Port 1 Mode1 Register Address 0x0D 21 Figure Port 2 Data Register Address 0x02 22 Figure USB Status and Control Register Address 0x1F 23 Figure USB Device Address Register Address 0x10 25 Figure Endpoint 0 Mode Register Address 0x12 25 Figure USB Endpoint EP1 Mode Registers Address 0x14 26 Figure Endpoint 0 and 1 Counter Registers Addresses 0x11 and 0x13 27 Figure Diagram of USB - PS/2 System Connections 28 Figure Timer LSB Register Address 0x24 29 Figure Timer MSB Register Address 0x25 29 Figure Timer Block Diagram 29 Figure Processor Status and Control Register Address 0xFF 29 Figure Global Interrupt Enable Register Address 0x20 32 Figure Endpoint Interrupt Enable Register Address 0x21 33 Figure Interrupt Controller Logic Block Diagram 34 Figure Port 0 Interrupt Enable Register Address 0x04 34 Figure Port 1 Interrupt Enable Register Address 0x05 34 Figure Port 0 Interrupt Polarity Register Address 0x06 35 Figure Port 1 Interrupt Polarity Register Address 0x07 35 Figure GPIO Interrupt Diagram 35 Figure Clock Timing 45 Figure USB Data Signal Timing 45 Figure Receiver Jitter Tolerance 45 Figure Differential to EOP Transition Skew and EOP Width 46 Figure Differential Data Jitter 46 LIST OF TABLES Table I/O Register Summary 13 Table Wake-up Timer Adjust Settings 18 Table Ports 0 and 1 Output Control Truth Table 21 Table Control Modes to Force Outputs 24 Table Interrupt Vector Assignments 31 Table USB Register Mode Encoding for Control and Non-Control Endpoint 36 Table Decode table for Table 20-3 “Details of Modes for Differing Traffic Conditions” 38 Table Details of Modes for Differing Traffic Conditions 39 Table CY7C63221A-XC Probe Pad Coordinates in microns 0,0 to bond pad centers 48 Page 4 of 50 [+] Feedback enCoRe USB CY7C63221/31A • enCoRe USB - enhanced Component Reduction Internal oscillator eliminates the need for an external crystal or resonator Interface can auto-configure to operate as PS/2 or USB without the need for external components to switch between modes no GPIO pins needed to manage dual mode capability Internal 3.3V regulator for USB pull-up resistor Configurable GPIO for real-world interface without external components • Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads, joysticks, and many others • USB Specification Compliance Conforms to USB Specification, Version Conforms to USB HID Specification, Version Supports 1 low-speed USB device address Supports 1 control endpoint and 1 data endpoint Integrated USB transceiver 3.3V regulated output for USB pull-up resistor • 8-bit RISC microcontroller Harvard architecture 6-MHz external ceramic resonator or internal clock mode 12-MHz internal CPU clock Internal memory 96 bytes of RAM 3 Kbytes of EPROM Interface can auto-configure to operate as PS/2 or USB No external components for switching between PS/2 and USB modes • I/O ports Up to 10 versatile General Purpose I/O GPIO pins, individually configurable High current drive on any GPIO pin 50 mA/pin current sink Each GPIO pin supports high-impedance inputs, internal pull-ups, open drain outputs, or traditional CMOS outputs Maskable interrupts on all I/O pins XTALIN, XTALOUT and VREG can be configured as additional input pins • Internal low-power wake-up timer during suspend mode Periodic wake-up with no external components • Optional 6-MHz internal oscillator mode Allows fast start-up from suspend mode • Watchdog timer WDT • Low-voltage Reset at 3.75V • Internal brown-out reset for suspend mode • Improved output drivers to reduce EMI • Operating voltage from 4.0V to 5.5VDC • Operating temperature from 0 to 70 degrees Celsius • available in DIE form or 16-pin PDIP • available in 18-pin SOIC, 18-pin PDIP • Industry-standard programmer support Page 5 of 50 [+] Feedback enCoRe USB CY7C63221/31A Functional Overview enCoRe USB - The New USB Standard Cypress has reinvented its leadership position in the low-speed USB market with a new family of innovative microcontrollers. Introducing...enCoRe Component Reduction.” Cypress has leveraged its design expertise in USB solutions to create a new family of low-speed USB microcontrollers that enables peripheral developers to design new products with a minimum number of components. At the heart of the Cypress enCoRe USB technology is the breakthrough design of a crystalless oscillator. By integrating the oscillator into the chip, an external crystal or resonator is no longer needed. We have also integrated other external components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a 3.3V regulator. All of this adds up to a lower system cost. The family is comprised of 8-bit RISC One Time Programmable OTP microcontrollers. The instruction set has been optimized specifically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications. The features up to 10 general-purpose I/O GPIO pins to support USB, PS/2 and other applications. The I/O pins are grouped into two ports Port 0 to 1 where each pin can be individually configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs with programmable drive strength of up to 50 mA output drive. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. The microcontrollers feature an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements 6 MHz This clock generator has been optimized to reduce clock-related noise emissions EMI , and provides the 6-MHz and 12-MHz clocks that remain internal to the microcontroller. When using the internal oscillator, XTALIN and XTALOUT can be configured as additional input pins that can be read on port Optionally, an external 6MHz ceramic resonator can be used to provide a higher precision reference if needed. The is offered with 3 Kbytes of EPROM to minimize cost, and has 96 bytes of data RAM for stack space, user variables, and USB endpoint FIFOs. The family includes low-voltage reset logic, a watchdog timer, a vectored interrupt controller, and a 12-bit free-running timer. The low-voltage reset LVR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000. LVR will also reset the part when VCC drops below the operating voltage range. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The microcontroller supports 7 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB BusReset, the 128-µs and 1.024-ms outputs from the free-running timer, two USB endpoints, an internal wake-up timer and the GPIO port. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after USB transactions complete on the bus. The GPIO port has a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be either rising or falling edge. The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above 128 µs and ms . The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event, and subtracting the two values. The CY7C63221/31A includes an integrated USB serial interface engine SIE . The hardware supports one USB device address with two endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. A 3.3V regulated output pin provides a pull-up source for the external USB resistor on the pin. When using an external voltage regulator VREG can be configured as an input pin that can be read on port 2 P2.0 . The USB D+ and USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and SDATA, the ability to disable the regulator output pin, and an interrupt to signal the start of PS/2 activity. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge rates operate in both modes to reduce EMI. Page 6 of 50 [+] Feedback Logic Block Diagram XTXATALLININ/P/P22..11 XXTTAALLOOUUT/TP2.2 Internal Oscillator EPROM 3 Kbytes Brown-Out Reset Watch Dog T im er Low Voltage Reset Xtal Oscillator 8-bit RISC Core W ake-U p Timer Ordering Information Ordering Code EPROM Size CY7C63221A-PXC CY7C63221A-PC CY7C63231A-SXC CY7C63231A-SC CY7C63231A-PXC CY7C63231A-PC CY7C63221A-XC CY7C63221A-XWC Package Diagrams Package Name P1 S1 P3 - Package Type 16-Pin 300-Mil PDIP Lead-free 16-Pin 300-Mil PDIP 18-Pin Small Outline Package Lead-free 18-Pin Small Outline Package 18-Pin 300-Mil PDIP Lead-free 18-Pin 300-Mil PDIP 18-Pad DIE Form 18-Pad DIE Form Lead-free Operating Range Commercial 16-Lead 300-Mil Molded DIP P1 51-85009-A Page 47 of 50 [+] Feedback 18-Lead 300-Mil Molded SOIC S1 enCoRe USB CY7C63221/31A 18-Lead 300-Mil Molded DIP P3 51-85023-A Die Step x microns Pad Size 80 x 80 microns DIE FORM Cypress Logo 17 16 4 5 Y 6 10 11 12 15 14 0,0 51-85010-A Page 48 of 50 [+] Feedback enCoRe USB CY7C63221/31A Table 26-1 below shows the die pad coordinates for the CY7C63221A-XC. The center location of each bond pad is relative to the center of the die which has coordinate 0,0 as shown above. Table CY7C63221A-XC Probe Pad Coordinates in microns 0,0 to bond pad centers Pad Number Pin Name X microns Y microns P0.0 P0.1 P0.2

PDF Datasheet Preview

enCoRe USB CY7C63221/31A

CY7C63221A/31A enCoRe USB Low-speed USB Peripheral Controller

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600
[+] Feedback
enCoRe USB CY7C63221/31A

TABLE OF CONTENTS

FEATURES 5

FUNCTIONAL OVERVIEW 6
enCoRe USB - The New USB Standard 6

LOGIC BLOCK DIAGRAM 7

PIN CONFIGURATIONS 7

PIN ASSIGNMENTS 7

PROGRAMMING MODEL 8

Program Counter PC 8-bit Accumulator A 8-bit Index Register X 8-bit Program Stack Pointer PSP 8-bit Data Stack Pointer DSP 9 Address Modes 9

Data 9 Direct 9 Indexed 9

INSTRUCTION SET SUMMARY 10

MEMORY ORGANIZATION 11

Program Memory Organization 11 Data Memory Organization 12 I/O Register Summary 13

CLOCKING 14

Internal/External Oscillator Operation 15 External Oscillator 15

RESET 16

Low-voltage Reset LVR 16 Brown-out Reset BOR 16 Watchdog Reset WDR 17

SUSPEND MODE 17

Clocking Mode on Wake-up from Suspend 18 Wake-up Timer 18

GENERAL PURPOSE I/O PORTS 19

Auxiliary Input Port 21

USB SERIAL INTERFACE ENGINE SIE 22

USB Enumeration 23 USB Port Status and Control 23

USB DEVICE 25

USB Address Register 25 USB Control Endpoint 25 USB Non-Control Endpoints 26 USB Endpoint Counter Registers

Page 2 of 50
[+] Feedback
enCoRe USB CY7C63221/31A

USB REGULATOR OUTPUT 27 PS/2 OPERATION 28 12-BIT FREE-RUNNING TIMER 28 PROCESSOR STATUS AND CONTROL REGISTER 29 INTERRUPTS 31
Interrupt Vectors 31 Interrupt Latency 32 Interrupt Sources 32 USB MODE TABLES 36 REGISTER SUMMARY 41 ABSOLUTE MAXIMUM RATINGS 42 DC CHARACTERISTICS 42 SWITCHING CHARACTERISTICS 44 ORDERING INFORMATION 47 PACKAGE DIAGRAMS 47

Page 3 of 50 [+] Feedback
enCoRe USB CY7C63221/31A

LIST OF FIGURES

Figure Program Memory Space with Interrupt Vector Table 11 Figure Clock Oscillator On-chip Circuit 14 Figure Clock Configuration Register Address 0xF8 14 Figure Watchdog Reset WDR, Address 0x26 17 Figure Block Diagram of GPIO Port one pin shown 19 Figure Port 0 Data Address 0x00 19 Figure Port 1 Data Address 0x01 20 Figure GPIO Port 0 Mode0 Register Address 0x0A 20 Figure GPIO Port 0 Mode1 Register Address 0x0B 20 Figure GPIO Port 1 Mode0 Register Address 0x0C 20 Figure GPIO Port 1 Mode1 Register Address 0x0D 21 Figure Port 2 Data Register Address 0x02 22 Figure USB Status and Control Register Address 0x1F 23 Figure USB Device Address Register Address 0x10 25 Figure Endpoint 0 Mode Register Address 0x12 25 Figure USB Endpoint EP1 Mode Registers Address 0x14 26 Figure Endpoint 0 and 1 Counter Registers Addresses 0x11 and 0x13 27 Figure Diagram of USB - PS/2 System Connections 28 Figure Timer LSB Register Address 0x24 29 Figure Timer MSB Register Address 0x25 29 Figure Timer Block Diagram 29 Figure Processor Status and Control Register Address 0xFF 29 Figure Global Interrupt Enable Register Address 0x20 32 Figure Endpoint Interrupt Enable Register Address 0x21 33 Figure Interrupt Controller Logic Block Diagram 34 Figure Port 0 Interrupt Enable Register Address 0x04 34 Figure Port 1 Interrupt Enable Register Address 0x05 34 Figure Port 0 Interrupt Polarity Register Address 0x06 35 Figure Port 1 Interrupt Polarity Register Address 0x07 35 Figure GPIO Interrupt Diagram 35 Figure Clock Timing 45 Figure USB Data Signal Timing 45 Figure Receiver Jitter Tolerance 45 Figure Differential to EOP Transition Skew and EOP Width 46 Figure Differential Data Jitter 46

LIST OF TABLES Table I/O Register Summary 13 Table Wake-up Timer Adjust Settings 18 Table Ports 0 and 1 Output Control Truth Table 21 Table Control Modes to Force Outputs 24 Table Interrupt Vector Assignments 31 Table USB Register Mode Encoding for Control and Non-Control Endpoint 36 Table Decode table for Table 20-3 “Details of Modes for Differing Traffic Conditions” 38 Table Details of Modes for Differing Traffic Conditions 39 Table CY7C63221A-XC Probe Pad Coordinates in microns 0,0 to bond pad centers 48

Page 4 of 50 [+] Feedback
enCoRe USB CY7C63221/31A
• enCoRe USB - enhanced Component Reduction Internal oscillator eliminates the need for an external crystal or resonator Interface can auto-configure to operate as PS/2 or USB without the need for external components to switch between modes no GPIO pins needed to manage dual mode capability Internal 3.3V regulator for USB pull-up resistor Configurable GPIO for real-world interface without external components
• Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads, joysticks, and many others
• USB Specification Compliance Conforms to USB Specification, Version Conforms to USB HID Specification, Version Supports 1 low-speed USB device address Supports 1 control endpoint and 1 data endpoint Integrated USB transceiver 3.3V regulated output for USB pull-up resistor
• 8-bit RISC microcontroller Harvard architecture 6-MHz external ceramic resonator or internal clock mode 12-MHz internal CPU clock Internal memory 96 bytes of RAM 3 Kbytes of EPROM Interface can auto-configure to operate as PS/2 or USB No external components for switching between PS/2 and USB modes
• I/O ports Up to 10 versatile General Purpose I/O GPIO pins, individually configurable High current drive on any GPIO pin 50 mA/pin current sink Each GPIO pin supports high-impedance inputs, internal pull-ups, open drain outputs, or traditional CMOS outputs Maskable interrupts on all I/O pins XTALIN, XTALOUT and VREG can be configured as additional input pins
• Internal low-power wake-up timer during suspend mode Periodic wake-up with no external components
• Optional 6-MHz internal oscillator mode Allows fast start-up from suspend mode
• Watchdog timer WDT
• Low-voltage Reset at 3.75V
• Internal brown-out reset for suspend mode
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.5VDC
• Operating temperature from 0 to 70 degrees Celsius
• available in DIE form or 16-pin PDIP
• available in 18-pin SOIC, 18-pin PDIP
• Industry-standard programmer support

Page 5 of 50 [+] Feedback
enCoRe USB CY7C63221/31A

Functional Overview
enCoRe USB - The New USB Standard

Cypress has reinvented its leadership position in the low-speed USB market with a new family of innovative microcontrollers. Introducing...enCoRe Component Reduction.” Cypress has leveraged its design expertise in USB solutions to create a new family of low-speed USB microcontrollers that enables peripheral developers to design new products with a minimum number of components. At the heart of the Cypress enCoRe USB technology is the breakthrough design of a crystalless oscillator. By integrating the oscillator into the chip, an external crystal or resonator is no longer needed. We have also integrated other external components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a 3.3V regulator. All of this adds up to a lower system cost.

The family is comprised of 8-bit RISC One Time Programmable OTP microcontrollers. The instruction set has been optimized specifically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications.

The features up to 10 general-purpose I/O GPIO pins to support USB, PS/2 and other applications. The I/O pins are grouped into two ports Port 0 to 1 where each pin can be individually configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs with programmable drive strength of up to 50 mA output drive. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller.

The microcontrollers feature an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements 6 MHz This clock generator has been optimized to reduce clock-related noise emissions EMI , and provides the 6-MHz and 12-MHz clocks that remain internal to the microcontroller. When using the internal oscillator, XTALIN and XTALOUT can be configured as additional input pins that can be read on port Optionally, an external 6MHz ceramic resonator can be used to provide a higher precision reference if needed.

The is offered with 3 Kbytes of EPROM to minimize cost, and has 96 bytes of data RAM for stack space, user variables, and USB endpoint FIFOs.

The family includes low-voltage reset logic, a watchdog timer, a vectored interrupt controller, and a 12-bit free-running timer. The low-voltage reset LVR logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000. LVR will also reset the part when VCC drops below the operating voltage range. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms.

The microcontroller supports 7 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB BusReset, the 128-µs and 1.024-ms outputs from the free-running timer, two USB endpoints, an internal wake-up timer and the GPIO port. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after USB transactions complete on the bus. The GPIO port has a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be either rising or falling edge.

The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above 128 µs and ms . The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event, and subtracting the two values.

The CY7C63221/31A includes an integrated USB serial interface engine SIE . The hardware supports one USB device address with two endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. A 3.3V regulated output pin provides a pull-up source for the external USB resistor on the pin. When using an external voltage regulator VREG can be configured as an input pin that can be read on port 2 P2.0 .

The USB D+ and USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and SDATA, the ability to disable the regulator output pin, and an interrupt to signal the start of PS/2 activity. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge rates operate in both modes to reduce EMI.

Page 6 of 50 [+] Feedback

Logic Block Diagram

XTXATALLININ/P/P22..11 XXTTAALLOOUUT/TP2.2

Internal Oscillator

EPROM 3 Kbytes

Brown-Out Reset

Watch Dog T im er

Low Voltage Reset

Xtal Oscillator
8-bit RISC Core

W ake-U p Timer
Ordering Information
Ordering Code

EPROM Size

CY7C63221A-PXC

CY7C63221A-PC

CY7C63231A-SXC

CY7C63231A-SC

CY7C63231A-PXC

CY7C63231A-PC

CY7C63221A-XC

CY7C63221A-XWC

Package Diagrams

Package Name P1 S1 P3 -

Package Type 16-Pin 300-Mil PDIP Lead-free 16-Pin 300-Mil PDIP 18-Pin Small Outline Package Lead-free 18-Pin Small Outline Package 18-Pin 300-Mil PDIP Lead-free 18-Pin 300-Mil PDIP 18-Pad DIE Form 18-Pad DIE Form Lead-free

Operating Range

Commercial
16-Lead 300-Mil Molded DIP P1
51-85009-A

Page 47 of 50 [+] Feedback
18-Lead 300-Mil Molded SOIC S1
enCoRe USB CY7C63221/31A
18-Lead 300-Mil Molded DIP P3
51-85023-A

Die Step x microns Pad Size 80 x 80 microns

DIE FORM

Cypress Logo
17 16
4 5 Y 6
10 11 12
15 14 0,0
51-85010-A

Page 48 of 50 [+] Feedback
enCoRe USB CY7C63221/31A

Table 26-1 below shows the die pad coordinates for the CY7C63221A-XC. The center location of each bond pad is relative to the center of the die which has coordinate 0,0 as shown above.

Table CY7C63221A-XC Probe Pad Coordinates in microns 0,0 to bond pad centers

Pad Number

Pin Name

X microns

Y microns

P0.0

P0.1

P0.2

More datasheets: M83731/10-321 | M83731/15-231 | M83731/15-261 | M83731/15-271 | M837319211 | M837319231 | M83731/16-311 | M83731/9-272 | M8373110232 | CY7C63231A-SC

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C63221A-PXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C63221A-PXC 508121