CY7C4285-10ASC

CY7C4285-10ASC Datasheet

CY7C4275 CY7C4285

Part	Datasheet
CY7C4285-10ASC	CY7C4285-10ASC (pdf)

Related Parts	Information
CY7C4275-10ASC	CY7C4275-10ASC
CY7C4275-15ASC	CY7C4275-15ASC

PDF Datasheet Preview
CY7C4275 CY7C4285 32K/64Kx18 Deep Sync FIFOs Functional Description • High-speed, low-power, first-in first-out FIFO memories • 32K x 18 CY7C4275 • 64K x 18 CY7C4285 • micron CMOS for optimum speed/power • High-speed 100-MHz operation 10-ns read/write cycle times • Low power ICC=50 mA ISB = 2 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags • TTL compatible • Retransmit function • Output Enable OE pin • Independent read and write enable pins • Center power and ground pins for reduced noise • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • 68-pin PLCC and 64-pin 10x10 TQFP • Pin-compatible density upgrade to CY7C42X5 families • Pin-compatible density upgrade to IDT72205/15/25/35/45 The CY7C4275/85 are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4275/85 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and a write enable pin WEN . When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and a read enable pin REN . In addition, the CY7C4275/85 have an output enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input WXI, RXI , cascade output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. Logic Block Diagram INPUT REGISTER WCLK WRITE CONTROL WRITE POINTER RAM ARRAY 32Kx18 64Kx18 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER FF EF PAF SMODE RESET LOGIC FL/RT WXI WXO/HF RXI RXO EXPANSION LOGIC OUTPUT REGISTER READ CONTROL RCLK REN Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Pin Configurations PLCC Top View Ordering Information 32Kx18 Deep Sync FIFO Speed ns Ordering Code 64Kx18 Deep Sync FIFO Speed ns Ordering Code Package Name A64 Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Package Name A64 Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack CY7C4275 CY7C4285 Operating Range Commercial Industrial Commercial Operating Range Commercial Industrial Commercial Page 19 of 21 Package Diagrams CY7C4275 CY7C4285 Page 20 of 21 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4275 CY7C4285 Document Title CY7C4275, CY7C4285 32K/64K X 18 Deep Sync FIFOs Document Number 38-06008 ECN NO. Issue Date Orig. of Change Description of Change 106469 07/12/01 SZV Change from Spec Number 38-00588 to 38-06008 122260 12/26/02 RBI Power up requirements added to Maximum Ratings Information Page 21 of 21

PDF Datasheet Preview

CY7C4275 CY7C4285
32K/64Kx18 Deep Sync FIFOs

Functional Description
• High-speed, low-power, first-in first-out FIFO memories
• 32K x 18 CY7C4275
• 64K x 18 CY7C4285
• micron CMOS for optimum speed/power
• High-speed 100-MHz operation 10-ns read/write cycle
times
• Low power

ICC=50 mA

ISB = 2 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Output Enable OE pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 68-pin PLCC and 64-pin 10x10 TQFP
• Pin-compatible density upgrade to CY7C42X5
families
• Pin-compatible density upgrade to

IDT72205/15/25/35/45

The CY7C4275/85 are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4275/85 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and a write enable pin WEN .

When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and a read enable pin REN . In addition, the CY7C4275/85 have an output enable pin OE . The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices.

Depth expansion is possible using the cascade input WXI, RXI , cascade output WXO, RXO , and First Load FL pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC.

Logic Block Diagram

INPUT REGISTER

WCLK

WRITE CONTROL

WRITE POINTER

RAM ARRAY
32Kx18 64Kx18

FLAG PROGRAM REGISTER

FLAG LOGIC

READ POINTER

FF EF

PAF SMODE

RESET

LOGIC

FL/RT

WXI WXO/HF

RXI RXO

EXPANSION LOGIC

OUTPUT REGISTER

READ CONTROL

RCLK REN

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600

Pin Configurations

PLCC Top View
Ordering Information
32Kx18 Deep Sync FIFO

Speed ns
Ordering Code
64Kx18 Deep Sync FIFO

Speed ns
Ordering Code

Package Name A64

Package Type
64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack

Package Name A64

Package Type
64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack

CY7C4275 CY7C4285

Operating Range

Commercial Industrial Commercial

Operating Range

Commercial Industrial Commercial

Page 19 of 21

Package Diagrams

CY7C4275 CY7C4285

Page 20 of 21

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C4275 CY7C4285

Document Title CY7C4275, CY7C4285 32K/64K X 18 Deep Sync FIFOs Document Number 38-06008

ECN NO.

Issue Date

Orig. of Change

Description of Change
106469 07/12/01

SZV Change from Spec Number 38-00588 to 38-06008
122260 12/26/02

RBI Power up requirements added to Maximum Ratings Information

Page 21 of 21

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C4285-10ASC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C4285-10ASC 508105