CY7C4201V-15AC

CY7C4201V-15AC Datasheet

CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V

Part	Datasheet
CY7C4201V-15AC	CY7C4201V-15AC (pdf)

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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Functional Description • High-speed, low-power, first-in, first-out FIFO memories • 64 x 9 CY7C4421V • 256 x 9 CY7C4201V • 512 x 9 CY7C4211V • 1K x 9 CY7C4221V • 2K x 9 CY7C4231V • 4K x 9 CY7C4241V • 8K x 9 CY7C4251V • High-speed 66-MHz operation 15-ns read/write cycle time • Low power ICC = 20 mA • 3.3V operation for low power consumption and easy integration into low-voltage systems • 5V-tolerant inputs VIH max= 5V • Fully asynchronous and simultaneous read and write operation • Empty, Full, and Programmable Almost Empty and Almost Full status flags • TTL compatible • Output Enable OE pin • Independent read and write enable pins • Center power and ground pins for reduced noise • Width expansion capability • Space saving 32-pin 7 mm x 7 mm TQFP • 32-pin PLCC The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock WCLK and two Write Enable pins WEN1, WEN2/LD . When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a Free-Running Read Clock RCLK and two Read Enable Pins REN1, REN2 . In addition, the CY7C42X1V has an Output Enable Pin OE . The Read RCLK and Write WCLK clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. Logic Block Diagram WCLK WEN1 WEN2/LD WRITE CONTROL WRITE POINTER D0 − 8 INPUT REGISTER Dual Port RAM Array 64 x 9 8Kx 9 Pin Configuration PLCC Top View D3 D4 D5 D6 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER Ordering Information 256 x 9 Low Voltage Synchronous FIFO Speed ns Ordering Code Package Name CY7C4201V-15AC CY7C4201V-25AC 512 x 9 Low Voltage Synchronous FIFO Speed ns Ordering Code Package Name CY7C4211V-15AC CY7C4211V-15JC Package Type 32-Lead Thin Quad Flatpack 32-Lead Thin Quad Flatpack Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier CY7C4211V-25AC CY7C4211V-25JC 1K x 9 Low Voltage Synchronous FIFO Speed ns Ordering Code Package Name CY7C4221V-15AC CY7C4221V-15JC CY7C4221V-25AC 2K x 9 Low Voltage Synchronous FIFO Speed ns Ordering Code Package Name 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack Package Type CY7C4231V-15AC CY7C4231V-15JC CY7C4231V-25AC CY7C4231V-25JC 4K x 9 Low Voltage Synchronous FIFO Speed ns Ordering Code Package Name CY7C4241V-15AC CY7C4241V-15JC CY7C4241V-25AC 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack CY7C4241V-25JC 32-Lead Plastic Leaded Chip Carrier Operating Range Commercial Operating Range Commercial Commercial Operating Range Commercial Commercial Operating Range Commercial Commercial Operating Range Commercial Commercial Page 15 of 17 CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Ordering Information continued 8K x 9 Low Voltage Synchronous FIFO Speed ns Ordering Code Package Name Package Type CY7C4251V-15AC 32-Lead Thin Quad Flatpack CY7C4251V-15JC 32-Lead Plastic Leaded Chip Carrier CY7C4251V-25AC 32-Lead Thin Quad Flatpack Package Diagrams 32-Lead Thin Plastic Quad Flatpack 7 x 7 x mm A32 Operating Range Commercial Commercial 32-Lead Plastic Leaded Chip Carrier J65 51-85063-B 51-85002-B All product and company names mentioned in this document are the trademarks of their respective holders. Page 16 of 17 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V Document History Page Document Title Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Document Number 38-06010 Orig. of ECN NO. Issue Date Change Description of Change 106471 09/10/01 SZV Change from Spec number 38-00622 to 38-06010 127857 08/25/03 FSG Fixed empty flag timing diagram Fixed switching waveform diagram typo Page 17 of 17

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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V

Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Functional Description
• High-speed, low-power, first-in, first-out FIFO memories
• 64 x 9 CY7C4421V
• 256 x 9 CY7C4201V
• 512 x 9 CY7C4211V
• 1K x 9 CY7C4221V
• 2K x 9 CY7C4231V
• 4K x 9 CY7C4241V
• 8K x 9 CY7C4251V
• High-speed 66-MHz operation 15-ns read/write cycle time
• Low power ICC = 20 mA
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• 5V-tolerant inputs VIH max= 5V
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and Almost Full status flags
• TTL compatible
• Output Enable OE pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Width expansion capability
• Space saving 32-pin 7 mm x 7 mm TQFP
• 32-pin PLCC

The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock WCLK and two Write Enable pins WEN1, WEN2/LD .

When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a Free-Running Read Clock RCLK and two Read Enable Pins REN1, REN2 . In addition, the CY7C42X1V has an Output Enable Pin OE . The Read RCLK and Write WCLK clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable.

Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.

Logic Block Diagram

WCLK WEN1 WEN2/LD WRITE

CONTROL

WRITE POINTER

D0 − 8 INPUT REGISTER

Dual Port RAM Array
64 x 9 8Kx 9

Pin Configuration

PLCC Top View

D3 D4 D5 D6

FLAG PROGRAM REGISTER

FLAG LOGIC

READ POINTER
Ordering Information
256 x 9 Low Voltage Synchronous FIFO

Speed ns
Ordering Code

Package Name

CY7C4201V-15AC

CY7C4201V-25AC
512 x 9 Low Voltage Synchronous FIFO

Speed ns
Ordering Code

Package Name

CY7C4211V-15AC

CY7C4211V-15JC

Package Type 32-Lead Thin Quad Flatpack 32-Lead Thin Quad Flatpack

Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier

CY7C4211V-25AC

CY7C4211V-25JC
1K x 9 Low Voltage Synchronous FIFO

Speed ns
Ordering Code

Package Name

CY7C4221V-15AC

CY7C4221V-15JC

CY7C4221V-25AC
2K x 9 Low Voltage Synchronous FIFO

Speed ns
Ordering Code

Package Name
32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier

Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack

Package Type

CY7C4231V-15AC

CY7C4231V-15JC

CY7C4231V-25AC

CY7C4231V-25JC
4K x 9 Low Voltage Synchronous FIFO

Speed ns
Ordering Code

Package Name

CY7C4241V-15AC

CY7C4241V-15JC

CY7C4241V-25AC
32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier

Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack

CY7C4241V-25JC
32-Lead Plastic Leaded Chip Carrier

Operating Range Commercial

Operating Range Commercial

Commercial

Operating Range Commercial

Commercial

Operating Range Commercial

Commercial

Operating Range Commercial

Commercial

Page 15 of 17

CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Ordering Information continued
8K x 9 Low Voltage Synchronous FIFO

Speed ns
Ordering Code

Package Name

Package Type

CY7C4251V-15AC
32-Lead Thin Quad Flatpack

CY7C4251V-15JC
32-Lead Plastic Leaded Chip Carrier

CY7C4251V-25AC
32-Lead Thin Quad Flatpack

Package Diagrams
32-Lead Thin Plastic Quad Flatpack 7 x 7 x mm A32

Operating Range Commercial

Commercial
32-Lead Plastic Leaded Chip Carrier J65
51-85063-*B
51-85002-*B

All product and company names mentioned in this document are the trademarks of their respective holders.

Page 16 of 17

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V

Document History Page

Document Title Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Document Number 38-06010

Orig. of ECN NO. Issue Date Change

Description of Change
106471 09/10/01 SZV

Change from Spec number 38-00622 to 38-06010
127857 08/25/03 FSG

Fixed empty flag timing diagram

Fixed switching waveform diagram typo

Page 17 of 17

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C4201V-15AC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C4201V-15AC 508098