CY7C341B-25JC

CY7C341B-25JC Datasheet

The CY7C341B is an Erasable Programmable Logic Device EPLD in which CMOS EPROM cells are used to configure logic functions within the device. The architecture is 100% user-configurable, allowing the devices to accommodate a variety of independent logic functions.

Part	Datasheet
CY7C341B-25JC	CY7C341B-25JC (pdf)

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341B • 192 macrocells in 12 logic array blocks LABs • Eight dedicated inputs, 64 bidirectional I/O pins • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and PGA packages Functional Description The CY7C341B is an Erasable Programmable Logic Device EPLD in which CMOS EPROM cells are used to configure logic functions within the device. The architecture is 100% user-configurable, allowing the devices to accommodate a variety of independent logic functions. The 192 macrocells in the CY7C341B are divided into 12 Logic Array Blocks LABs , 16 per LAB. There are 384 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C341B allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 37 times the functionality of 20-pin PLDs, the CY7C341B allows the replacement of over 75 TTL devices. By replacing large amounts of logic, the CY7C341B reduces board space, part count, and increases system reliability. Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8 macrocells are connected to I/O pins and eight are buried, while for LABs B, C, D, E, H, I, J, and K, four macrocells are connected to I/O pins and 12 are buried. Moreover, in addition to the I/O and buried macrocells, there are 32 single product term logic expanders in each LAB. Their use greatly enhances the capability of the macrocells without increasing the number of product terms in each macrocell. Logic Array Blocks There are 12 logic array blocks in the CY7C341B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Externally, the CY7C341B provides eight dedicated inputs, one of which may be used as a system clock. There are 64 I/O pins that ICC ACTIVE mA Typ. CY7C341B 192-Macrocell EPLD may be individually configured for input, output, or bidirectional data flow. VCC = 5.0V Room Temp. 0 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz MAXIMUM FREQUENCY Typical ICC vs. fMAX Programmable Interconnect Array The Programmable Interconnect Array PIA solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives. Design Recommendations For proper operation, input and output pins must be constrained to the range GND < VIN or VOUT < VCC. Unused inputs must always be tied to an appropriate logic level either VCC or GND . Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND, directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types. Selection Guide Maximum Access Time 7C341B-25 7C341B-35 Unit Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Design Security The CY7C341B contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the device. The CY7C341B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages. Logic Block Diagram 2 A5 41 K6 42 J6 INPUT/CLK INPUT 4 C5 5 A4 6 B4 7 A3 8 A2 9 B3 10 A1 11 B2 Ordering Information Speed ns 25 Ordering Code CY7C341B-25HC/HI CY7C341B-25JC/JI CY7C341B-25RC/RI CY7C341B-35HC/HI CY7C341B-35JC/JI CY7C341B-35RC/RI Package Name Package Type 84-lead Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 84-lead Windowed Pin Grid Array 84-lead Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 84-lead Windowed Pin Grid Array Operating Range Commercial/Industrial Commercial/Industrial Page 8 of 11 Package Diagrams 84-Leaded Windowed Leaded Chip Carrier H84 CY7C341B 51-80081 Page 9 of 11 Package Diagrams continued 84-Lead Plastic Leaded Chip Carrier J83 CY7C341B 84-Lead Windowed Pin Grid Array R84 51-85006-A 51-80026-*B MAX is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Page 10 of 11 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C341B Document Title CY7C341B 192-Macrocell EPLD Document Number 38-03016 ECN NO. Issue Date Orig. of Change Description of Change 106316 05/17/01 SZV Change from ecn # 38-00137 to 38-03016 113613 04/11/02 OOR PGA package diagram dimensions were updated Page 11 of 11

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341B
• 192 macrocells in 12 logic array blocks LABs
• Eight dedicated inputs, 64 bidirectional I/O pins
• Advanced 0.65-micron CMOS technology to increase performance
• Programmable interconnect array
• 384 expander product terms
• Available in 84-pin HLCC, PLCC, and PGA packages

Functional Description

The CY7C341B is an Erasable Programmable Logic Device EPLD in which CMOS EPROM cells are used to configure logic functions within the device. The architecture is 100% user-configurable, allowing the devices to accommodate a variety of independent logic functions.

The 192 macrocells in the CY7C341B are divided into 12 Logic Array Blocks LABs , 16 per LAB. There are 384 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip.

The speed and density of the CY7C341B allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 37 times the functionality of 20-pin PLDs, the CY7C341B allows the replacement of over 75 TTL devices. By replacing large amounts of logic, the CY7C341B reduces board space, part count, and increases system reliability.

Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8 macrocells are connected to I/O pins and eight are buried, while for LABs B, C, D, E, H, I, J, and K, four macrocells are connected to I/O pins and 12 are buried. Moreover, in addition to the I/O and buried macrocells, there are 32 single product term logic expanders in each LAB. Their use greatly enhances the capability of the macrocells without increasing the number of product terms in each macrocell.

Logic Array Blocks

There are 12 logic array blocks in the CY7C341B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated.

Externally, the CY7C341B provides eight dedicated inputs, one of which may be used as a system clock. There are 64 I/O pins that

ICC ACTIVE mA Typ.

CY7C341B
192-Macrocell EPLD
may be individually configured for input, output, or bidirectional data flow.

VCC = 5.0V Room Temp.
0 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz

MAXIMUM FREQUENCY

Typical ICC vs. fMAX Programmable Interconnect Array

The Programmable Interconnect Array PIA solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.

Design Recommendations

For proper operation, input and output pins must be constrained to the range GND < VIN or VOUT < VCC. Unused inputs must always be tied to an appropriate logic level either VCC or GND . Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND, directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types.

Selection Guide

Maximum Access Time
7C341B-25
7C341B-35

Unit

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600

Design Security

The CY7C341B contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the device.

The CY7C341B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield.

The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages.

Logic Block Diagram
2 A5 41 K6
42 J6

INPUT/CLK INPUT
4 C5 5 A4 6 B4 7 A3 8 A2 9 B3 10 A1 11 B2
Ordering Information

Speed ns 25
Ordering Code CY7C341B-25HC/HI CY7C341B-25JC/JI CY7C341B-25RC/RI CY7C341B-35HC/HI CY7C341B-35JC/JI CY7C341B-35RC/RI

Package Name

Package Type
84-lead Windowed Leaded Chip Carrier
84-lead Plastic Leaded Chip Carrier
84-lead Windowed Pin Grid Array
84-lead Windowed Leaded Chip Carrier
84-lead Plastic Leaded Chip Carrier
84-lead Windowed Pin Grid Array

Operating Range Commercial/Industrial

Commercial/Industrial

Page 8 of 11

Package Diagrams
84-Leaded Windowed Leaded Chip Carrier H84

CY7C341B
51-80081

Page 9 of 11

Package Diagrams continued
84-Lead Plastic Leaded Chip Carrier J83

CY7C341B
84-Lead Windowed Pin Grid Array R84
51-85006-A
51-80026-*B

MAX is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 10 of 11

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C341B

Document Title CY7C341B 192-Macrocell EPLD Document Number 38-03016

ECN NO.

Issue Date

Orig. of Change

Description of Change
106316 05/17/01

SZV Change from ecn # 38-00137 to 38-03016
113613 04/11/02 OOR PGA package diagram dimensions were updated

Page 11 of 11

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Datasheet ID: CY7C341B-25JC 508092