CY7C138-25JXI

CY7C138-25JXI Datasheet

CY7C138

Part	Datasheet
CY7C138-25JXI	CY7C138-25JXI (pdf)

Related Parts	Information
CY7C138-25JXC	CY7C138-25JXC

PDF Datasheet Preview
CY7C138 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy • True dual-ported memory cells that enable simultaneous reads of the same memory location • 4K x 8 organization CY7C138 • 0.65-micron complementary metal oxide semiconductor CMOS for optimum speed and power • High speed access 25 ns • Low operating power ICC = 160 mA max. • Fully asynchronous operation • Automatic power-down • Transistor logic TTL compatible • Expandable data bus to 32 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Available in 68-pin plastic leaded chip carrier PLCC • Pb-free packages available Logic Block Diagram R/WL CEL OEL Functional Description The CY7C138 is a high speed CMOS 4K x 8 dual-port static RAM. Various arbitration schemes are included on the CY7C138 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C138 can be used as a standalone 8-bit dual-port static RAM or multiple devices can be combined to function as a 16-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins chip enable CE , read or write enable R/W , and output enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip enable CE pin or SEM pin. R/WR CER OER I/O7L I/O0L BUSYL[1, 2] A11L I/O CONTROL I/O CONTROL ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER I/O7R I/O0R BUSYR[1, 2] A11R INSTELM[2L] CEL OEL R/WL INTERRUPT SEMAPHORE ARBITRATION CER OER R/WR SEMR INTR[2] Notes BUSY is an output in master mode and an input in slave mode. Interrupt push-pull output and requires no pull-up resistor. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C138 Contents Pin Configurations 3 Maximum Ratings 4 Operating Range 4 Electrical Characteristics 4 Capacitance 5 Switching 5 Architecture 14 Functional Description 14 Write Operation 14 Read Operation 14 Interrupts 14 Busy 14 Master/Slave 14 Semaphore Operation 14 Ordering Information 17 4K x8 Dual-Port SRAM 17 Ordering Code Definition 17 Package Diagram 18 Acronyms 19 Document Conventions 19 Units of Measure 19 Document History Page 20 Sales, Solutions, and Legal Information 21 Worldwide Sales and Design Support 21 Products 21 PSoC Solutions 21 Page 2 of 21 [+] Feedback Pin Configurations Figure 68-Pin PLCC Top View A9L A8L A7L A6L NC A11L A10L NC VCC SEM CEL R/W L I/O 1L I/O 0L I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 CY7C138 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R CY7C138 I/O7R NC OER R/WR SEMR CER NC GND NC A11R A10R A9R A8R A7R A6R A5R Table Pin Definitions Left Port CEL OEL R/WL SEML Right Port CER OER R/WR SEMR INTL BUSYL M/S VCC GND INTR BUSYR Description Data bus input/output Address lines Chip enable Output enable Read/Write enable Semaphore enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. Interrupt flag. INTL is set when right port writes location FFE and is cleared when left port reads location FFE. INTR is set when left port writes location FFF and is cleared when right port reads location FFF. Busy flag Master or slave select Power Ground Table Selection Guide Maximum access time ns Maximum operating current Maximum standby current for ISB1 Commercial 7C138-25 Unit Page 3 of 21 [+] Feedback Ordering Information 4K x8 Dual-Port SRAM Speed ns 25 Ordering Code CY7C138-25JXC CY7C138-25JXI Ordering Code Definition Package Diagram 51-85005 51-85005 Package Type 68-Pin Plastic Leaded Chip Carrier Pb-free 68-Pin Plastic Leaded Chip Carrier Pb-free CY7C XXX - XX X Temperature Range X = C or I C = Commercial I = Industrial Package J = PLCC X=X:Pb-free RoHS Compliant XX = Speed = 25 ns Density 138 = Part number identifier CY7C = Cypress Dual Port SRAMs CY7C138 Operating Range Commercial Industrial Page 17 of 21 [+] Feedback Package Diagram Figure 68-Pin Plastic Leaded Chip Carrier 51-85005 CY7C138 51-85005 *B Page 18 of 21 [+] Feedback CY7C138 Acronyms Acronym CMOS TQFP I/O SRAM PLCC TTL Description complementary metal oxide semiconductor thin quad plastic flatpack input/output static random access memory plastic leaded chip carrier transistor logic Document Conventions Units of Measure Symbol ns V µA mA mV MHz pF W °C Unit of Measure nano seconds Volts micro Amperes milli Amperes Ohms milli Volts Mega Hertz pico Farad Watts degree Celcius Page 19 of 21 [+] Feedback CY7C138 Document History Page Document Title CY7C138 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Document Number 38-06037 ECN No. Orig. of Change Submission Date Description of Change 110180 09/29/01 Change from Spec number 38-00536 to 38-06037 122287 12/27/02 power-up requirements added to Maximum Ratings Information 393403 See ECN Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C138-15JXC, CY7C138-25JXC, CY7C139-25JXC 2623658 VKN/PYRS 12/17/08 Added CY7C138-25JXI part Removed CY7C139 from the Ordering information table 2672737 GNKK 03/12/2009 Corrected title in the Document History table 2714768 VKN/AESA 06/04/2009 Corrected defective Logic Block diagram, Pinouts and Package diagrams 2898564 RAME 03/24/10 Removed inactive parts. Updated package diagram. 3099184 ADMU 12/02/2010 Removed information for CY7C139 parts. Removed speed bins Updated datasheet as per new template Added Acronyms and Units of Measure table Added Ordering Code Definition Updated all footnotes. Page 20 of 21 [+] Feedback CY7C138 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 21 of 21 [+] Feedback

PDF Datasheet Preview

CY7C138
4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
• True dual-ported memory cells that enable simultaneous reads of the same memory location
• 4K x 8 organization CY7C138
• 0.65-micron complementary metal oxide semiconductor

CMOS for optimum speed and power
• High speed access 25 ns
• Low operating power ICC = 160 mA max.
• Fully asynchronous operation
• Automatic power-down
• Transistor logic TTL compatible
• Expandable data bus to 32 bits or more using

Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port communication
• Available in 68-pin plastic leaded chip carrier PLCC
• Pb-free packages available

Logic Block Diagram

R/WL

CEL OEL

Functional Description

The CY7C138 is a high speed CMOS 4K x 8 dual-port static RAM. Various arbitration schemes are included on the CY7C138 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C138 can be used as a standalone 8-bit dual-port static RAM or multiple devices can be combined to function as a 16-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins chip enable CE , read or write enable R/W , and output enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip enable CE pin or SEM pin.

R/WR CER OER

I/O7L I/O0L BUSYL[1, 2]

A11L

I/O CONTROL

I/O CONTROL

ADDRESS DECODER

MEMORY ARRAY

ADDRESS DECODER

I/O7R I/O0R BUSYR[1, 2] A11R

INSTELM[2L]

CEL OEL R/WL

INTERRUPT SEMAPHORE ARBITRATION

CER OER R/WR

SEMR INTR[2]

Notes BUSY is an output in master mode and an input in slave mode. Interrupt push-pull output and requires no pull-up resistor.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C138

Contents

Pin Configurations 3 Maximum Ratings 4 Operating Range 4 Electrical Characteristics 4 Capacitance 5 Switching 5 Architecture 14 Functional Description 14

Write Operation 14 Read Operation 14 Interrupts 14 Busy 14 Master/Slave 14
Semaphore Operation 14 Ordering Information 17
4K x8 Dual-Port SRAM 17 Ordering Code Definition 17 Package Diagram 18 Acronyms 19 Document Conventions 19 Units of Measure 19 Document History Page 20 Sales, Solutions, and Legal Information 21 Worldwide Sales and Design Support 21 Products 21 PSoC Solutions 21

Page 2 of 21 [+] Feedback

Pin Configurations

Figure 68-Pin PLCC Top View

A9L A8L A7L A6L

NC A11L A10L

NC VCC

SEM CEL

R/W L

I/O 1L I/O 0L

I/O2L I/O3L I/O4L I/O5L GND

I/O6L I/O7L VCC GND

I/O0R I/O1R I/O2R

I/O3R I/O4R I/O5R I/O6R
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

CY7C138
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43

A5L A4L A3L A2L A1L A0L INTL BUSYL GND

M/S BUSYR

INTR A0R

A1R A2R

A3R A4R

CY7C138

I/O7R NC

OER R/WR SEMR

CER NC GND NC A11R A10R A9R A8R A7R A6R A5R

Table Pin Definitions

Left Port

CEL OEL R/WL SEML

Right Port

CER OER R/WR SEMR

INTL

BUSYL M/S VCC GND

INTR BUSYR

Description Data bus input/output Address lines Chip enable Output enable Read/Write enable Semaphore enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. Interrupt flag. INTL is set when right port writes location FFE and is cleared when left port reads location FFE. INTR is set when left port writes location FFF and is cleared when right port reads location FFF. Busy flag Master or slave select Power Ground

Table Selection Guide

Maximum access time ns Maximum operating current Maximum standby current for ISB1

Commercial
7C138-25

Unit

Page 3 of 21 [+] Feedback
Ordering Information
4K x8 Dual-Port SRAM

Speed ns 25
Ordering Code

CY7C138-25JXC CY7C138-25JXI
Ordering Code Definition

Package Diagram 51-85005 51-85005

Package Type
68-Pin Plastic Leaded Chip Carrier Pb-free 68-Pin Plastic Leaded Chip Carrier Pb-free

CY7C XXX - XX X

Temperature Range X = C or I C = Commercial I = Industrial Package J = PLCC X=X:Pb-free RoHS Compliant

XX = Speed = 25 ns Density 138 = Part number identifier CY7C = Cypress Dual Port SRAMs

CY7C138

Operating Range

Commercial Industrial

Page 17 of 21 [+] Feedback

Package Diagram

Figure 68-Pin Plastic Leaded Chip Carrier 51-85005

CY7C138
51-85005 *B

Page 18 of 21 [+] Feedback

CY7C138

Acronyms

Acronym CMOS TQFP I/O SRAM PLCC TTL

Description complementary metal oxide semiconductor thin quad plastic flatpack input/output static random access memory plastic leaded chip carrier transistor logic

Document Conventions

Units of Measure

Symbol ns V µA mA
mV MHz pF W °C

Unit of Measure nano seconds Volts micro Amperes milli Amperes Ohms milli Volts Mega Hertz pico Farad Watts degree Celcius

Page 19 of 21 [+] Feedback

CY7C138

Document History Page

Document Title CY7C138 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Document Number 38-06037

ECN No.

Orig. of Change

Submission Date

Description of Change
110180
09/29/01 Change from Spec number 38-00536 to 38-06037
122287
12/27/02 power-up requirements added to Maximum Ratings Information
393403

See ECN Added Pb-Free Logo
Added Pb-Free parts to ordering information:

CY7C138-15JXC, CY7C138-25JXC, CY7C139-25JXC
2623658 VKN/PYRS 12/17/08 Added CY7C138-25JXI part
Removed CY7C139 from the Ordering information table
2672737

GNKK
03/12/2009 Corrected title in the Document History table
2714768 VKN/AESA 06/04/2009 Corrected defective Logic Block diagram, Pinouts and Package diagrams
2898564

RAME
03/24/10 Removed inactive parts. Updated package diagram.
3099184

ADMU
12/02/2010 Removed information for CY7C139 parts.

Removed speed bins

Updated datasheet as per new template

Added Acronyms and Units of Measure table
Added Ordering Code Definition

Updated all footnotes.

Page 20 of 21 [+] Feedback

CY7C138

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 21 of 21
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C138-25JXI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C138-25JXI 508000