CY7C2565KV18-400BZC

CY7C2565KV18-400BZC Datasheet


CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Part Datasheet
CY7C2565KV18-400BZC CY7C2565KV18-400BZC CY7C2565KV18-400BZC (pdf)
Related Parts Information
CY7C2565KV18-500BZC CY7C2565KV18-500BZC CY7C2565KV18-500BZC
CY7C2563KV18-400BZXI CY7C2563KV18-400BZXI CY7C2563KV18-400BZXI
CY7C2563KV18-450BZXI CY7C2563KV18-450BZXI CY7C2563KV18-450BZXI
CY7C2565KV18-450BZXC CY7C2565KV18-450BZXC CY7C2565KV18-450BZXC
CY7C2563KV18-500BZXI CY7C2563KV18-500BZXI CY7C2563KV18-500BZXI
CY7C2565KV18-400BZXC CY7C2565KV18-400BZXC CY7C2565KV18-400BZXC
CY7C2565KV18-450BZC CY7C2565KV18-450BZC CY7C2565KV18-450BZC
CY7C2565KV18-500BZXC CY7C2565KV18-500BZXC CY7C2565KV18-500BZXC
CY7C2563KV18-400BZC CY7C2563KV18-400BZC CY7C2563KV18-400BZC
CY7C2563KV18-500BZC CY7C2563KV18-500BZC CY7C2563KV18-500BZC
CY7C2563KV18-450BZC CY7C2563KV18-450BZC CY7C2563KV18-450BZC
CY7C2565KV18-500BZI CY7C2565KV18-500BZI CY7C2565KV18-500BZI
CY7C2565KV18-400BZI CY7C2565KV18-400BZI CY7C2565KV18-400BZI
CY7C2565KV18-400BZXI CY7C2565KV18-400BZXI CY7C2565KV18-400BZXI
CY7C2565KV18-450BZI CY7C2565KV18-450BZI CY7C2565KV18-450BZI
PDF Datasheet Preview
CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18
72-Mbit SRAM 4-Word Burst Architecture Cycle Read Latency with ODT
72-Mbit SRAM 4-Word Burst Architecture Cycle Read Latency with ODT

Configurations
• Separate independent read and write data ports Supports concurrent transactions
• 550 MHz clock for high bandwidth

With Read Cycle Latency of cycles CY7C2561KV18 8M x 8 CY7C2576KV18 8M x 9
• 4-word burst for reducing address bus frequency
• Double Data Rate DDR interfaces on both read and write ports data transferred at 1100 MHz at 550 MHz
• Available in clock cycle latency
• Two input clocks K and K for precise DDR timing SRAM uses rising edges only
• Echo clocks CQ and CQ simplify data capture in high-speed systems
• Data valid pin QVLD to indicate valid data on the output
• On-Die Termination ODT feature Supported for D[x:0], BWS[x:0], and K/K inputs
• Single multiplexed address input bus latches address inputs for read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• operates with cycle read latency when DOFF is
asserted HIGH
• Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V± 0.1V I/O VDDQ = 1.4V to VDD [1]

Supports both 1.5V and 1.8V I/O supply
• HSTL inputs and variable drive HSTL output buffers
• Available in 165-ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• Phase-locked loop PLL for accurate data placement

CY7C2563KV18 4M x 18

CY7C2565KV18 2M x 36

Functional Description

The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words CY7C2561KV18 , 9-bit words CY7C2576KV18 , 18-bit words CY7C2563KV18 , or 36-bit words CY7C2565KV18 that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks K and K , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

These devices have an On-Die Termination feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Table Selection Guide

Description Maximum Operating Frequency Maximum Operating Current
550 MHz
1310
500 MHz 500 830 850 1210
450 MHz 450 760 780 1100
400 MHz 400 690 710 1000

Unit MHz mA
Test Data-Out TDO 14 Performing a TAP Reset 14 TAP Registers 14 TAP Instruction Set 14 TAP Electrical Characteristics 17 TAP AC Switching Characteristics 18 TAP Timing and Test Conditions 18 Power Up Sequence in QDR II+ SRAM 21 Power Up Sequence 21 PLL Constraints 21 Maximum Ratings 22 Operating Range 22 Neutron Soft Error Immunity 22 Electrical Characteristics 22 DC Electrical Characteristics 22 AC Electrical Characteristics 23 Capacitance 24 Thermal Resistance 24 Switching Characteristics 25 Switching Waveforms 26 Read/Write/Deselect Sequence 26 Ordering Information 27 Package Diagram 28 Document History Page 29 Sales, Solutions, and Legal Information 30 Worldwide Sales and Design Support 30 Products 30 PSoC Solutions 30

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CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Pin Configuration

The pin configuration for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follow.[2]
165-Ball FBGA 13 x 15 x mm Pinout

CY7C2561KV18 8M x 8

WPS NWS1

K NC/144M RPS

A NC/288M K

NWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

QVLD

CY7C2576KV18 8M x 9

K NC/144M RPS

A NC/288M K

BWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
500 CY7C2563KV18-500BZC

CY7C2565KV18-500BZC

CY7C2565KV18-500BZXC

CY7C2565KV18-500BZI

CY7C2563KV18-500BZXI
450 CY7C2563KV18-450BZC

CY7C2565KV18-450BZC

CY7C2565KV18-450BZXC

CY7C2565KV18-450BZI

CY7C2563KV18-450BZXI
400 CY7C2563KV18-400BZC

CY7C2565KV18-400BZC

CY7C2565KV18-400BZXC

CY7C2565KV18-400BZI

CY7C2563KV18-400BZXI

CY7C2565KV18-400BZXI

Package Diagram

Part and Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Operating Range

Commercial
165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial
165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial
165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial
165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial
165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm
165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

Industrial
Ordering Code Definitions CY 7 C 25XX K V18 XXX BZ X C, I

Temperature grades X = Pb-free C = Commercial I = Industrial

TSOP

Maximum operating frequency

V VDD Process technology 65-nm 72-Mbit QDR-II+ SRAM 4-Word Burst Architecture with ODT Technology CMOS Family SRAMs Company ID CY = Cypress

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CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B
165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES :

SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180-*C

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CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Document History Page

Document Title 72-Mbit SRAM 4-Word Burst Architecture Cycle Read Latency with ODT Document Number 001-15887

Orig. Of Change

Submission Date

Description Of Change
1120252 VKN

See ECN New datasheet
*A 1246904 VKN/AESA See ECN Added 550 and 500 MHz speed bins Removed 375, 333, and 300 MHz speed bins Made ODT applicable only for DDR inputs Added footnote # 2
*B 1739343 VKN/AESA See ECN Converted from Advance Information to Preliminary
*C 2088787 VKN/AESA See ECN Changed PLL lock time from 2048 cycles to 20 us Added footnote # 23 related to IDD Corrected typo in the footnote # 27
*D 2612244 VKN/AESA 11/25/08 Changed JTAG ID [31:29] from 001 to 000 Updated Power up sequence waveform and its description Included Thermal Resistance values Changed the package size from 15 x 17 x mm to 13 x 15 x mm
*E 2697841 VKN
04/24/09 Moved to external web
*F 2746858 VKN
07/31/09
Converted from preliminary to final For 550 MHz, 500 MHz and 450 MHz bins, changed tCO, tCCQO, tCHZ specs to 450 ps and tDOH, tCQOH, tCLZ to -450 ps Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information
*G 2794726 VKN
10/29/09
Updated Input and Output Capacitance Modified Ordering code disclaimer Included CY7C2565KV18-400BZXI in the Ordering Information table Updated 165-ball package diagram Added the page
*H 2896003 NJY
03/19/10
Removed inactive parts from Ordering Information. Updated package diagram. Updated links in Sales, Solutions, and Legal Information.
2931775 VKN
05/13/10
Included following parts in the Ordering information table CY7C2563KV18-550BZC, CY7C2565KV18-550BZC, CY7C2565KV18-550BZXC, CY7C2565KV18-550BZI, CY7C2563KV18-550BZXI.
*J 2972174 NJY
07/08/10 Corrected title in first page of the document.
*K 3055013 NJY
10/12/10
Removed the following parts from the Ordering Information table CY7C2563KV18-550BZC, CY7C2565KV18-550BZC, CY7C2565KV18-550BZXC, CY7C2563KV18-550BZXI, CY7C2565KV18-550BZI Added ordering code definitions.

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CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

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Datasheet ID: CY7C2565KV18-400BZC 508090