74ABT646CMSA

74ABT646CMSA Datasheet

74ABT646 Octal Transceivers and Registers with 3-STATE Outputs

Part	Datasheet
74ABT646CMSA	74ABT646CMSA (pdf)

Related Parts	Information
74ABT646CMTC	74ABT646CMTC
74ABT646CMTCX	74ABT646CMTCX
74ABT646CSC	74ABT646CSC
74ABT646CSCX	74ABT646CSCX
74ABT646CMSAX	74ABT646CMSAX

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74ABT646 Octal Transceivers and Registers with 3-STATE Outputs 74ABT646 Octal Transceivers and Registers with 3-STATE Outputs The ABT646 consists of bus transceiver circuits with 3STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time transparent mode data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode control OE HIGH , A data may be stored in the B register and/or B data may be stored in the A register. s Independent registers for A and B buses s Multiplexed real-time and stored data s A and B output sink capability of 64 mA, source capabil- ity of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Order Number Package Number Package Description 74ABT646CSC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-153, 4.4mm Wide 74ABT646CMSA MSA24 24-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide 74ABT646CMTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names CPAB, CPBA SAB, SBA OE DIR Description Data Register A Inputs/3-STATE Outputs Data Register B Inputs/3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Input Direction Control Input 1999 Fairchild Semiconductor Corporation DS010978 74ABT646 Truth Table Inputs Data I/O Note 1 DIR CPAB CPBA SAB SBA Function X H or L H or L X Isolation Input Clock An Data into A Register Clock Bn Data into B Register An to Time Transparent Mode Input Output Clock An Data into A Register H or L X A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn Bn to Time Transparent Mode L Output Input Clock Bn Data into B Register X H or L X B Register to An Stored Mode Clock Bn Data into B Register and Output to An H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Transition Note 1 The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Real Time Transfer A-Bus to B-Bus Storage from Bus to Register FIGURE Real Time Transfer B-Bus to A-Bus FIGURE FIGURE Transfer from Register to Bus FIGURE 74ABT646 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ABT646 Absolute Maximum Ratings Note 2 Storage Temperature −65°C to +150°C

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74ABT646 Octal Transceivers and Registers with 3-STATE Outputs
74ABT646 Octal Transceivers and Registers with 3-STATE Outputs

The ABT646 consists of bus transceiver circuits with 3STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time transparent mode data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode control OE HIGH , A data may be stored in the B register and/or B data may be stored in the A register.
s Independent registers for A and B buses s Multiplexed real-time and stored data s A and B output sink capability of 64 mA, source capabil-
ity of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF
loads s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire
power up and power down cycle s Nondestructive hot insertion capability
Ordering Code:

Order Number Package Number

Package Description
74ABT646CSC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-153, 4.4mm Wide
74ABT646CMSA

MSA24
24-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74ABT646CMTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names CPAB, CPBA SAB, SBA OE DIR

Description Data Register A Inputs/3-STATE Outputs Data Register B Inputs/3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Input Direction Control Input
1999 Fairchild Semiconductor Corporation DS010978
74ABT646

Truth Table

Inputs

Data I/O Note 1

DIR CPAB CPBA SAB SBA

Function

X H or L H or L X

Isolation

Input Clock An Data into A Register

Clock Bn Data into B Register

An to Time Transparent Mode

Input Output Clock An Data into A Register

H or L X

A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn

Bn to Time Transparent Mode

L Output Input Clock Bn Data into B Register

X H or L X

B Register to An Stored Mode Clock Bn Data into B Register and Output to An

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Transition

Note 1 The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.

Real Time Transfer A-Bus to B-Bus

Storage from Bus to Register

FIGURE Real Time Transfer

B-Bus to A-Bus

FIGURE

FIGURE Transfer from Register to Bus

FIGURE
74ABT646

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ABT646

Absolute Maximum Ratings Note 2

Storage Temperature
−65°C to +150°C

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Datasheet ID: 74ABT646CMSA 513064