CY7C2544KV18-300BZI

CY7C2544KV18-300BZI Datasheet

CY7C2540KV18, CY7C2555KV18

Part	Datasheet
CY7C2544KV18-300BZI	CY7C2544KV18-300BZI (pdf)

Related Parts	Information
CY7C2544KV18-333BZI	CY7C2544KV18-333BZI

PDF Datasheet Preview
CY7C2540KV18, CY7C2555KV18 CY7C2542KV18, CY7C2544KV18 72-Mbit SRAM 2-Word Burst Architecture Cycle Read Latency with ODT Configurations • Separate independent read and write data ports Supports concurrent transactions • 333 MHz clock for high bandwidth • 2-word burst for reducing address bus frequency • Double Data Rate DDR interfaces on both read and write ports data transferred at 666 MHz at 333 MHz • Available in clock cycle latency • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Echo clocks CQ and CQ simplify data capture in high-speed systems • Data valid pin QVLD to indicate valid data on the output • On-Die Termination ODT feature Supported for D[x:0], BWS[x:0], and K/K inputs • Single multiplexed address input bus latches address inputs for both read and write ports • Separate port selects for depth expansion • Synchronous internally self-timed writes • operates with cycle read latency when DOFF is asserted HIGH • Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW • Available in x8, x9, x18, and x36 configurations • Full data coherency, providing most current data • Core VDD = 1.8V± 0.1V IO VDDQ = 1.4V to VDD [1] Supports both 1.5V and 1.8V IO supply • HSTL inputs and variable drive HSTL output buffers • Available in 165-Ball FBGA package 13 x 15 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port • Phase Locked Loop PLL for accurate data placement Selection Guide With Read Cycle Latency of cycles: CY7C2540KV18 8M x 8 CY7C2555KV18 8M x 9 CY7C2542KV18 4M x 18 CY7C2544KV18 2M x 36 Functional Description The CY7C2540KV18, CY7C2555KV18, CY7C2542KV18, and CY7C2544KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common IO devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 8-bit words CY7C2540KV18 , 9-bit words CY7C2555KV18 , 18-bit words CY7C2542KV18 , or 36-bit words CY7C2544KV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”. These devices have an On-Die Termination feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Description Maximum Operating Frequency Maximum Operating Current 333 MHz 300 MHz 300 730 750 910 250 MHz 250 640 650 790 200 MHz 200 540 550 660 Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code 333 CY7C2544KV18-333BZI 300 CY7C2544KV18-300BZI Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Operating Range Industrial Industrial Package Diagram Figure 165-Pin FBGA 13 x 15 x mm TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B - 01.0665X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / DESIGN 4.6C PACKAGE CODE BB0AC 51-85180-A Page 25 of 26 [+] Feedback CY7C2540KV18, CY7C2555KV18 CY7C2542KV18, CY7C2544KV18 Document History Page Document Title 72-Mbit SRAM 2-Word Burst Architecture Cycle Read Latency with ODT Document Number 001-15885 Ecn No. Orig. Of Change Submission Date Description Of Change * 1121204 VKN See ECN New datasheet A 1252023 VKN/AESA See ECN Made ODT applicable only for DDR inputs Added footnote # 2 B 1739343 VKN/AESA See ECN Converted from Advance Information to Preliminary C 2088787 VKN/AESA See ECN Changed PLL lock time from 2048 cycles to 20 us Added footnote # 21 related to IDD Corrected typo in the footnote # 25 D 2612244 VKN/AESA 11/25/08 Changed JTAG ID [31:29] from 001 to 000 Updated Power up sequence waveform and its description Included Thermal Resistance values Changed the package size from 15 x 17 x mm to 13 x 15 x mm E 2746858 VKN 07/31/09 Converted from preliminary to final Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information F 2767155 VKN 09/23/2009 Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Modified Ordering code disclaimer Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 26 of 26 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C2540KV18, CY7C2555KV18

CY7C2542KV18, CY7C2544KV18
72-Mbit SRAM 2-Word Burst Architecture Cycle Read Latency with ODT

Configurations
• Separate independent read and write data ports Supports concurrent transactions
• 333 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double Data Rate DDR interfaces on both read and write ports data transferred at 666 MHz at 333 MHz
• Available in clock cycle latency
• Two input clocks K and K for precise DDR timing SRAM uses rising edges only
• Echo clocks CQ and CQ simplify data capture in high-speed systems
• Data valid pin QVLD to indicate valid data on the output
• On-Die Termination ODT feature Supported for D[x:0], BWS[x:0], and K/K inputs
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• operates with cycle read latency when DOFF is
asserted HIGH
• Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V± 0.1V IO VDDQ = 1.4V to VDD [1]

Supports both 1.5V and 1.8V IO supply
• HSTL inputs and variable drive HSTL output buffers
• Available in 165-Ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• Phase Locked Loop PLL for accurate data placement

Selection Guide

With Read Cycle Latency of cycles:

CY7C2540KV18 8M x 8

CY7C2555KV18 8M x 9

CY7C2542KV18 4M x 18

CY7C2544KV18 2M x 36

Functional Description

The CY7C2540KV18, CY7C2555KV18, CY7C2542KV18, and CY7C2544KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common IO devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 8-bit words CY7C2540KV18 , 9-bit words CY7C2555KV18 , 18-bit words CY7C2542KV18 , or 36-bit words CY7C2544KV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

These devices have an On-Die Termination feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Description Maximum Operating Frequency Maximum Operating Current
333 MHz
300 MHz 300 730 750 910
250 MHz 250 640 650 790
200 MHz 200 540 550 660
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
333 CY7C2544KV18-333BZI
300 CY7C2544KV18-300BZI

Package Diagram

Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Operating Range

Industrial

Industrial

Package Diagram

Figure 165-Pin FBGA 13 x 15 x mm

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B - 01.0665X
11 10 9 8 7 6 5 4 3 2 1

A B C D E F G H J K L M N P R
0.15 4X

NOTES SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / DESIGN 4.6C PACKAGE CODE BB0AC
51-85180-*A

Page 25 of 26 [+] Feedback

CY7C2540KV18, CY7C2555KV18 CY7C2542KV18, CY7C2544KV18

Document History Page

Document Title 72-Mbit SRAM 2-Word Burst Architecture Cycle Read Latency with ODT Document Number 001-15885

Ecn No.

Orig. Of Change

Submission Date

Description Of Change
** 1121204 VKN

See ECN New datasheet
*A 1252023 VKN/AESA See ECN Made ODT applicable only for DDR inputs Added footnote # 2
*B 1739343 VKN/AESA See ECN Converted from Advance Information to Preliminary
*C 2088787 VKN/AESA See ECN Changed PLL lock time from 2048 cycles to 20 us Added footnote # 21 related to IDD Corrected typo in the footnote # 25
*D 2612244 VKN/AESA 11/25/08 Changed JTAG ID [31:29] from 001 to 000 Updated Power up sequence waveform and its description Included Thermal Resistance values Changed the package size from 15 x 17 x mm to 13 x 15 x mm
*E 2746858 VKN
07/31/09
Converted from preliminary to final Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information
*F 2767155 VKN
09/23/2009 Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Modified Ordering code disclaimer

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 26 of 26

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

More datasheets: 855-10233 | 855-10238 | 855-10237 | 855-10232 | FQAF11N90 | SW6WC-50 | 18034 | TOY0063 | 96NIC-10G2P-IN1 | 770

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C2544KV18-300BZI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C2544KV18-300BZI 508089