CY7C185-15VIT

CY7C185-15VIT Datasheet

CY7C185

Part	Datasheet
CY7C185-15VIT	CY7C185-15VIT (pdf)

PDF Datasheet Preview
CY7C185 64-Kbit 8 K x 8 Static RAM • High speed 15 ns • Fast tDOE • Low active power 715 mW • Low standby power 85 mW • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2 and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • Available in non Pb-free 28-pin 300-Mil Molded SOJ, 28-pin 300-Mil Molded SOIC and Pb-free 28-pin 300-Mil Molded DIP Logic Block Diagram Functional Description The CY7C185[1] is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable CE1 , an active HIGH chip enable CE2 , and active LOW output enable OE and tri-state drivers. This device has an automatic power-down feature CE1 or CE2 , reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP, SOJ, or SOIC package. An active LOW write enable signal WE controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins I/O0 through I/O7 is written into the memory location addressed by the address present on the address pins A0 through A12 . Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input or output pins. The input or output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable WE is HIGH. A die coat is used to insure alpha immunity. For a complete list of related documentation, click here. ROW DECODER A0 A9 A10 A11 A12 SENSE AMPS I/O0 INPUT BUFFER I/O1 I/O2 8K x 8 I/O3 ARRAY I/O4 A7 A8 I/O5 CE1 CE2 POWER COLUMN DECODER DOWN I/O6 I/O7 Note For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at • San Jose, CA 95134-1709 • 408-943-2600 CY7C185 Contents Pin Configuration 3 Selection Guide 3 Maximum Ratings 4 Operating Range 4 Electrical Characteristics 4 Capacitance 5 AC Test Loads and Waveforms 5 Switching Characteristics 6 Switching Waveforms 7 Typical DC and AC Characteristics 10 Truth Table 11 Address Designators 11 Ordering Information 12 Ordering Code Definitions 12 Package Diagrams 13 Acronyms 16 Document Conventions 16 Units of Measure 16 Document History Page 17 Sales, Solutions, and Legal Information 18 Worldwide Sales and Design Support 18 Products 18 Solutions 18 Cypress Developer Community 18 Technical Support 18 Page 2 of 18 CY7C185 Pin Configuration Figure 28-pin DIP / SOJ pinout Top View DIP/SOJ Top View NC 1 A4 2 A5 3 A6 4 A7 5 A8 6 A9 7 A10 8 A11 9 A12 10 I/O0 11 I/O1 12 I/O2 13 GND 14 28 VCC 27 WE 26 CE2 25 A3 24 A2 23 A1 22 OE 21 A0 20 CE1 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 Selection Guide Description Maximum Access Time ns Maximum Operating Current mA Maximum CMOS Standby Current mA Page 3 of 18 CY7C185 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature C to +150 C Ambient temperature with power applied C to +125 C Supply voltage to ground potential V to V DC voltage applied to outputs in High Z State [2] V to V DC input voltage [2] V to V Output current into outputs LOW 20 mA Static discharge voltage per MIL-STD-883, Method 3015 >2001 V Latch-up current >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0 °C to +70 °C °C to +85 °C VCC 5 V  10% 5 V  10% Electrical Characteristics Over the Operating Range Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage [2] Input Leakage Current Output Leakage Current VCC Operating Supply Current ISB1 Automatic Power-down Current ISB2 Automatic Power-down Current Test Conditions Ordering Information Speed ns Ordering Code 15 CY7C185-15VI 20 CY7C185-20PXC Package Name Package Type 51-85031 28-pin SOJ 51-85014 28-pin PDIP Pb-free Ordering Code Definitions CY 7 C 1 85 - XX X Temperature Range X = C or I C = Commercial I = Industrial Pb-free Package Type X = V or P or S V = 28-pin SOJ P = 28-pin PDIP S = 28-pin SOIC Speed XX = 15 ns or 20 ns or 35 ns 85 = 64 Kbit density with data width x 8 bits Family Code 1 = Fast Asynchronous SRAM family Technology Code C = CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Operating Range Industrial Commercial Page 12 of 18 Package Diagrams Figure 28-pin PDIP 300 Mil Package Outline, 51-85014 CY7C185 51-85014 G Page 13 of 18 CY7C185 Package Diagrams continued Figure 28-pin SOIC x Inches Package Outline, 51-85026 51-85026 H Page 14 of 18 Package Diagrams continued Figure 28-pin SOJ 300 Mils Package Outline, 51-85031 CY7C185 51-85031 E Page 15 of 18 Acronyms Acronym Chip Enable CMOS Complementary Metal Oxide Semiconductor Input/Output Output Enable SRAM Static Random Access Memory Small Outline J-Lead TSOP Thin Small Outline Package VFBGA Very Fine-Pitch Ball Grid Array Write Enable CY7C185 Document Conventions Units of Measure Symbol °C MHz µA mA mV mW ns pF V W Unit of Measure degree Celsius megahertz microampere milliampere millivolt milliwatt nanosecond picofarad volt watt Page 16 of 18 CY7C185 Removed IOS parameter from DC Electrical Characteristics table Updated the Ordering Information table 2263686 See ECN VKN / Removed 25 ns speed bin AESA Updated the Ordering Information table as per the current product offerings 3105329 12/09/2010 AJU Added Ordering Code Definitions. Updated Package Diagrams. 3235800 04/20/2011 PRAS Updated package diagram spec 51-85026 to F. Added Acronyms and Units of Measure. Template changes. 4383597 05/19/2014 VINI Updated Switching Characteristics: Added Note 8 and referred the same note in “Write Cycle”. Updated Package Diagrams: Updated in new template. 4579569 11/26/2014 VINI Added related documentation hyperlink in page Removed the prune part number CY7C185-35SC in Ordering Information. Page 17 of 18 CY7C185 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Solutions Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/psoc psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP Cypress Developer Community \| Forums \| Blogs \| Video \| Training Technical Support cypress.com/go/support Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 18 of 18

PDF Datasheet Preview

CY7C185
64-Kbit 8 K x 8 Static RAM
• High speed 15 ns
• Fast tDOE
• Low active power
715 mW
• Low standby power
85 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2 and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in non Pb-free 28-pin 300-Mil Molded SOJ, 28-pin
300-Mil Molded SOIC and Pb-free 28-pin 300-Mil Molded DIP

Logic Block Diagram

Functional Description

The CY7C185[1] is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable CE1 , an active HIGH chip enable CE2 , and active LOW output enable OE and tri-state drivers. This device has an automatic power-down feature CE1 or CE2 , reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP, SOJ, or SOIC package. An active LOW write enable signal WE controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins I/O0 through I/O7 is written into the memory location addressed by the address present on the address pins A0 through A12 . Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input or output pins. The input or output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable WE is HIGH. A die coat is used to insure alpha immunity. For a complete list of related documentation, click here.

ROW DECODER A0 A9 A10 A11 A12

SENSE AMPS

I/O0 INPUT BUFFER

I/O1

I/O2
8K x 8

I/O3

ARRAY

I/O4

A7 A8

I/O5

CE1 CE2

POWER

COLUMN DECODER DOWN

I/O6 I/O7

Note For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at
• San Jose, CA 95134-1709
• 408-943-2600

CY7C185

Contents
Pin Configuration 3 Selection Guide 3 Maximum Ratings 4 Operating Range 4 Electrical Characteristics 4 Capacitance 5 AC Test Loads and Waveforms 5 Switching Characteristics 6 Switching Waveforms 7 Typical DC and AC Characteristics 10 Truth Table 11 Address Designators 11 Ordering Information 12
Ordering Code Definitions 12

Package Diagrams 13 Acronyms 16 Document Conventions 16

Units of Measure 16 Document History Page 17 Sales, Solutions, and Legal Information 18

Worldwide Sales and Design Support 18 Products 18 Solutions 18 Cypress Developer Community 18 Technical Support 18

Page 2 of 18

CY7C185

Pin Configuration

Figure 28-pin DIP / SOJ pinout Top View

DIP/SOJ Top View

NC 1 A4 2 A5 3 A6 4 A7 5 A8 6 A9 7 A10 8 A11 9 A12 10 I/O0 11 I/O1 12 I/O2 13 GND 14
28 VCC 27 WE 26 CE2 25 A3 24 A2 23 A1 22 OE 21 A0 20 CE1 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3

Selection Guide

Description Maximum Access Time ns Maximum Operating Current mA Maximum CMOS Standby Current mA

Page 3 of 18

CY7C185

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature C to +150 C Ambient temperature with power applied C to +125 C Supply voltage to ground potential V to V DC voltage applied to outputs in High Z State [2] V to V DC input voltage [2] V to V

Output current into outputs LOW 20 mA Static discharge voltage per MIL-STD-883, Method 3015 >2001 V Latch-up current >200 mA

Operating Range

Range Commercial Industrial

Ambient Temperature 0 °C to +70 °C
°C to +85 °C

VCC 5 V  10% 5 V  10%

Electrical Characteristics

Over the Operating Range

Parameter

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage [2]

Input Leakage Current

Output Leakage Current

VCC Operating Supply

Current

ISB1

Automatic Power-down

Current

ISB2

Automatic Power-down

Current

Test Conditions
Ordering Information

Speed ns
Ordering Code
15 CY7C185-15VI
20 CY7C185-20PXC

Package Name

Package Type
51-85031 28-pin SOJ
51-85014 28-pin PDIP Pb-free
Ordering Code Definitions CY 7 C 1 85 - XX X

Temperature Range X = C or I C = Commercial I = Industrial Pb-free Package Type X = V or P or S V = 28-pin SOJ P = 28-pin PDIP S = 28-pin SOIC Speed XX = 15 ns or 20 ns or 35 ns 85 = 64 Kbit density with data width x 8 bits Family Code 1 = Fast Asynchronous SRAM family Technology Code C = CMOS Marketing Code 7 = SRAM Company ID CY = Cypress

Operating Range Industrial

Commercial

Page 12 of 18

Package Diagrams

Figure 28-pin PDIP 300 Mil Package Outline, 51-85014

CY7C185
51-85014 *G

Page 13 of 18

CY7C185

Package Diagrams continued

Figure 28-pin SOIC x Inches Package Outline, 51-85026
51-85026 *H

Page 14 of 18

Package Diagrams continued

Figure 28-pin SOJ 300 Mils Package Outline, 51-85031

CY7C185
51-85031 *E

Page 15 of 18

Acronyms

Acronym

Chip Enable

CMOS

Complementary Metal Oxide Semiconductor

Input/Output

Output Enable

SRAM

Static Random Access Memory

Small Outline J-Lead

TSOP

Thin Small Outline Package

VFBGA Very Fine-Pitch Ball Grid Array

Write Enable

CY7C185

Document Conventions

Units of Measure

Symbol °C MHz µA mA mV mW ns pF V W

Unit of Measure degree Celsius megahertz microampere milliampere millivolt milliwatt nanosecond picofarad volt watt

Page 16 of 18

CY7C185
Removed IOS parameter from DC Electrical Characteristics table Updated the Ordering Information table
2263686 See ECN

VKN / Removed 25 ns speed bin
AESA Updated the Ordering Information table as per the current product offerings
3105329 12/09/2010
AJU Added Ordering Code Definitions.

Updated Package Diagrams.
3235800 04/20/2011 PRAS Updated package diagram spec 51-85026 to *F.

Added Acronyms and Units of Measure.

Template changes.
4383597 05/19/2014

VINI Updated Switching Characteristics:

Added Note 8 and referred the same note in “Write Cycle”.

Updated Package Diagrams:

Updated in new template.
4579569 11/26/2014

VINI Added related documentation hyperlink in page
Removed the prune part number CY7C185-35SC in Ordering Information.

Page 17 of 18

CY7C185

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products

Solutions

Automotive Clocks & Buffers Interface Lighting & Power Control

Memory PSoC
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/psoc
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community | Forums | Blogs | Video | Training

Technical Support cypress.com/go/support

Touch Sensing
cypress.com/go/touch

USB Controllers
cypress.com/go/USB

Wireless/RF
cypress.com/go/wireless

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 18 of 18

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C185-15VIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C185-15VIT 508073