CY7C1550V18-375BZC

CY7C1550V18-375BZC Datasheet

CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18

Part	Datasheet
CY7C1550V18-375BZC	CY7C1550V18-375BZC (pdf)

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CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture Cycle Read Latency • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300 MHz to 375 MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate DDR interfaces data transferred at 750 MHz at 375 MHz • Read latency of clock cycles • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Echo clocks CQ and CQ simplify data capture in high speed systems • Data valid pin QVLD to indicate valid data on the output • Synchronous internally self-timed writes • Core VDD = 1.8V ± 0.1V IO VDDQ = 1.4V to VDD[1] • HSTL inputs and Variable drive HSTL output buffers • Available in 165-Ball FBGA package 15 x 17 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement Configurations With Read Cycle Latency of cycles CY7C1546V18 8M x 8 CY7C1557V18 8M x 9 CY7C1548V18 4M x 18 CY7C1550V18 2M x 36 Functional Description The CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of both K and K. Each address location is associated with two 8-bit words CY7C1546V18 , 9-bit words CY7C1557V18 , 18-bit words CY7C1548V18 , or 36-bit words CY7C1550V18 that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input ZQ . Synchronous data outputs Q, that share the same physical pins with the data inputs, D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from individual DDR SRAMs in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Maximum Operating Frequency Maximum Operating Current 375 MHz 1300 1300 1300 1300 333 MHz 333 1200 300 MHz 300 1100 Unit MHz mA Note The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ = 1.4V to VDD. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1546V18 CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 A 21:0 22 K DOFF Address Register CLK Gen. VREF R/W NWS[1:0] Control Logic Write Add. Decode Read Add. Decode Write Reg Write Reg 4M x 8 Array 4M x 8 Array Read Data Reg. Output Logic Ordering Information Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 375 CY7C1546V18-375BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1557V18-375BZC CY7C1548V18-375BZC CY7C1550V18-375BZC CY7C1546V18-375BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1557V18-375BZXC CY7C1548V18-375BZXC CY7C1550V18-375BZXC CY7C1546V18-375BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1557V18-375BZI CY7C1548V18-375BZI CY7C1550V18-375BZI CY7C1546V18-375BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1557V18-375BZXI CY7C1548V18-375BZXI CY7C1550V18-375BZXI 333 CY7C1546V18-333BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1557V18-333BZC CY7C1548V18-333BZC CY7C1550V18-333BZC CY7C1546V18-333BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1557V18-333BZXC CY7C1548V18-333BZXC CY7C1550V18-333BZXC CY7C1546V18-333BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1557V18-333BZI Ordering Information continued Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 300 CY7C1546V18-300BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1557V18-300BZC CY7C1548V18-300BZC CY7C1550V18-300BZC CY7C1546V18-300BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1557V18-300BZXC CY7C1548V18-300BZXC CY7C1550V18-300BZXC CY7C1546V18-300BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1557V18-300BZI CY7C1548V18-300BZI CY7C1550V18-300BZI CY7C1546V18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1557V18-300BZXI CY7C1548V18-300BZXI CY7C1550V18-300BZXI Page 25 of 27 [+] Feedback CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 Package Diagram Figure 165-Ball FBGA 15 x 17 x mm ! " # % & ' * + , 0 2 ! " # % & ' * + , 0 2 51-85195-A Page 26 of 27 [+] Feedback CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 Document History Page Document Title 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture Cycle Read Latency Document Number 001-06550 Issue Date Orig. of Change Description of Change * 432718 See ECN NXR New datasheet *D 1351504 See ECN VKN/AESA Converted from preliminary to final Added x8 and x9 parts Updated logic block diagram for x18 and x36 parts Changed tCYC max spec to ns for all speed bins Updated footnote# 21 Updated Ordering Information table Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 27 of 27 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture Cycle Read Latency
• 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36
• 300 MHz to 375 MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate DDR interfaces
data transferred at 750 MHz at 375 MHz
• Read latency of clock cycles
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Echo clocks CQ and CQ simplify data capture in high speed
systems
• Data valid pin QVLD to indicate valid data on the output
• Synchronous internally self-timed writes
• Core VDD = 1.8V ± 0.1V IO VDDQ = 1.4V to VDD[1]
• HSTL inputs and Variable drive HSTL output buffers
• Available in 165-Ball FBGA package 15 x 17 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

With Read Cycle Latency of cycles CY7C1546V18 8M x 8 CY7C1557V18 8M x 9 CY7C1548V18 4M x 18 CY7C1550V18 2M x 36

Functional Description

The CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of both K and K. Each address location is associated with two 8-bit words CY7C1546V18 , 9-bit words CY7C1557V18 , 18-bit words CY7C1548V18 , or 36-bit words CY7C1550V18 that burst sequentially into or out of the device.

Asynchronous inputs include output impedance matching input ZQ . Synchronous data outputs Q, that share the same physical pins with the data inputs, D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from individual DDR SRAMs in the system design.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Maximum Operating Frequency Maximum Operating Current
375 MHz
1300
1300
1300
1300
333 MHz 333 1200
300 MHz 300 1100

Unit MHz mA

Note The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ
= 1.4V to VDD.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1546V18

CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18

A 21:0 22

K DOFF

Address Register

CLK Gen.

VREF R/W NWS[1:0]

Control Logic

Write Add. Decode Read Add. Decode

Write Reg

Write Reg
4M x 8 Array 4M x 8 Array

Read Data Reg.

Output

Logic
Ordering Information

Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
375 CY7C1546V18-375BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1557V18-375BZC

CY7C1548V18-375BZC

CY7C1550V18-375BZC

CY7C1546V18-375BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1557V18-375BZXC

CY7C1548V18-375BZXC

CY7C1550V18-375BZXC

CY7C1546V18-375BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1557V18-375BZI

CY7C1548V18-375BZI

CY7C1550V18-375BZI

CY7C1546V18-375BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1557V18-375BZXI

CY7C1548V18-375BZXI

CY7C1550V18-375BZXI
333 CY7C1546V18-333BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1557V18-333BZC

CY7C1548V18-333BZC

CY7C1550V18-333BZC

CY7C1546V18-333BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1557V18-333BZXC

CY7C1548V18-333BZXC

CY7C1550V18-333BZXC

CY7C1546V18-333BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1557V18-333BZI
Ordering Information continued

Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
300 CY7C1546V18-300BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1557V18-300BZC

CY7C1548V18-300BZC

CY7C1550V18-300BZC

CY7C1546V18-300BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1557V18-300BZXC

CY7C1548V18-300BZXC

CY7C1550V18-300BZXC

CY7C1546V18-300BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1557V18-300BZI

CY7C1548V18-300BZI

CY7C1550V18-300BZI

CY7C1546V18-300BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1557V18-300BZXI

CY7C1548V18-300BZXI

CY7C1550V18-300BZXI

Page 25 of 27 [+] Feedback

CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18

Package Diagram

Figure 165-Ball FBGA 15 x 17 x mm
! " # % & ' * + , 0 2
! " # % & ' * + , 0 2
51-85195-*A

Page 26 of 27 [+] Feedback

CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18

Document History Page

Document Title 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture Cycle Read Latency Document Number 001-06550

Issue Date

Orig. of Change

Description of Change
** 432718 See ECN NXR New datasheet
*D 1351504 See ECN VKN/AESA Converted from preliminary to final Added x8 and x9 parts Updated logic block diagram for x18 and x36 parts Changed tCYC max spec to ns for all speed bins Updated footnote# 21 Updated Ordering Information table

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 27 of 27

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

More datasheets: D6 C 40 | D6 C 60 | D6 C 90 | D6 C 00 | D6L90 | D6 R 00 | D6 R 60 | D6 R 90 | D6 R 40 | D6 R 10

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Datasheet ID: CY7C1550V18-375BZC 508069