CY7C1512V18-250BZC

CY7C1512V18-250BZC Datasheet


CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18

Part Datasheet
CY7C1512V18-250BZC CY7C1512V18-250BZC CY7C1512V18-250BZC (pdf)
Related Parts Information
CY7C1512V18-250BZI CY7C1512V18-250BZI CY7C1512V18-250BZI
CY7C1514V18-250BZI CY7C1514V18-250BZI CY7C1514V18-250BZI
CY7C1514V18-250BZC CY7C1514V18-250BZC CY7C1514V18-250BZC
CY7C1514V18-200BZXI CY7C1514V18-200BZXI CY7C1514V18-200BZXI
CY7C1525V18-200BZC CY7C1525V18-200BZC CY7C1525V18-200BZC
CY7C1514V18-200BZC CY7C1514V18-200BZC CY7C1514V18-200BZC
CY7C1512V18-250BZXI CY7C1512V18-250BZXI CY7C1512V18-250BZXI
CY7C1514V18-167BZI CY7C1514V18-167BZI CY7C1514V18-167BZI
CY7C1514V18-167BZC CY7C1514V18-167BZC CY7C1514V18-167BZC
CY7C1512V18-200BZXI CY7C1512V18-200BZXI CY7C1512V18-200BZXI
CY7C1512V18-250BZIT CY7C1512V18-250BZIT CY7C1512V18-250BZIT
CY7C1512V18-200BZC CY7C1512V18-200BZC CY7C1512V18-200BZC
CY7C1512V18-167BZC CY7C1512V18-167BZC CY7C1512V18-167BZC
CY7C1512V18-200BZI CY7C1512V18-200BZI CY7C1512V18-200BZI
CY7C1525V18-200BZXC CY7C1525V18-200BZXC CY7C1525V18-200BZXC
CY7C1525V18-250BZXC CY7C1525V18-250BZXC CY7C1525V18-250BZXC
CY7C1514V18-167BZXC CY7C1514V18-167BZXC CY7C1514V18-167BZXC
CY7C1512V18-250BZXC CY7C1512V18-250BZXC CY7C1512V18-250BZXC
CY7C1512V18-200BZXC CY7C1512V18-200BZXC CY7C1512V18-200BZXC
CY7C1512V18-167BZXI CY7C1512V18-167BZXI CY7C1512V18-167BZXI
CY7C1512V18-167BZXC CY7C1512V18-167BZXC CY7C1512V18-167BZXC
CY7C1514V18-200BZXC CY7C1514V18-200BZXC CY7C1514V18-200BZXC
PDF Datasheet Preview
CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18
72-Mbit QDR -II SRAM 2-Word Burst Architecture
• Separate independent read and write data ports Supports concurrent transactions
• 250 MHz clock for high bandwidth
• 2-word burst on all accesses
• Double Data Rate DDR interfaces on both read and write ports
data transferred at 500 MHz at 250 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock
skew and flight time mismatches
• Echo clocks CQ and CQ simplify data capture in high-speed
systems
• Single multiplexed address input bus latches address inputs
for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V ±0.1V IO VDDQ = 1.4V to VDD
• Available in 165-Ball FBGA package 15 x 17 x mm
• Offered in both Pb-free and non Pb-free packages
• Variable drive HSTL output buffers
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

CY7C1510V18 8M x 8 CY7C1525V18 8M x 9 CY7C1512V18 4M x 18 CY7C1514V18 2M x 36

Selection Guide

Maximum Operating Frequency

Maximum Operating Current
250 MHz 250 850 900 1100

Functional Description

The CY7C1510V18, CY7C1525V18, CY7C1512V18, and CY7C1514V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common IO devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 8-bit words CY7C1510V18 , 9-bit words CY7C1525V18 , 18-bit words CY7C1512V18 , or 36-bit words CY7C1514V18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
200 MHz 200 750 800 900
167 MHz 167 700 750 800

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
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Logic Block Diagram CY7C1510V18

CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18

D[7:0]

A 21:0 22

Address Register

K DOFF

VREF WPS NWS[1:0]

CLK Gen.

Control Logic

Write Add. Decode Read Add. Decode

Write Reg

Write Reg

Address Register

A 21:0
4M x 8 Array 4M x 8 Array

Read Data Reg. 16 8

Control Logic
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
250 CY7C1510V18-250BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1525V18-250BZC

CY7C1512V18-250BZC

CY7C1514V18-250BZC

CY7C1510V18-250BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1525V18-250BZXC

CY7C1512V18-250BZXC

CY7C1514V18-250BZXC

CY7C1510V18-250BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1525V18-250BZI

CY7C1512V18-250BZI

CY7C1514V18-250BZI

CY7C1510V18-250BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1525V18-250BZXI

CY7C1512V18-250BZXI

CY7C1514V18-250BZXI
200 CY7C1510V18-200BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1525V18-200BZC

CY7C1512V18-200BZC

CY7C1514V18-200BZC

CY7C1510V18-200BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1525V18-200BZXC

CY7C1512V18-200BZXC

CY7C1514V18-200BZXC

CY7C1510V18-200BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1525V18-200BZI
Ordering Information continued

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
167 CY7C1510V18-167BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1525V18-167BZC

CY7C1512V18-167BZC

CY7C1514V18-167BZC

CY7C1510V18-167BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1525V18-167BZXC

CY7C1512V18-167BZXC

CY7C1514V18-167BZXC

CY7C1510V18-167BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1525V18-167BZI

CY7C1512V18-167BZI

CY7C1514V18-167BZI

CY7C1510V18-167BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1525V18-167BZXI

CY7C1512V18-167BZXI

CY7C1514V18-167BZXI

Page 26 of 29 [+] Feedback

Package Diagram

CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18

Figure 165-Ball FBGA 15 x 17 x mm , 51-85195

PIN 1 CORNER

TOP VIEW
1 2 3 4 5 6 7 8 9 10 11

A B C D E F G H J K L M N P R

SEATING PLANE C

BOTTOM VIEW

M C A B
+- 010.60.1564X 11 10 9 8 7 6 5 4 3 2 1

PIN 1 CORNER

A B C D E F G H J K L M N P R
0.15 4X
*B 319496 See ECN SYT Removed CY7C1525V18 from the title Included 300-MHz Speed bin Added footnote #1 and accordingly edited the VSS/144M And VSS/288M on the Pin Definitions table. Added Industrial Temperature Grade Replaced TBDs for IDD and ISB1 for 300 MHz, 250 MHz, 200 MHz and 167 MHz speed grades Changed the CIN from 5 pF to pF and CO from 7 pF to 8 pF in the Capacitance Table Removed the capacitance value column for the x9 option from Capacitance Table Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS TRI-STATE on Page 18 Added lead-free product information Updated the Ordering Information by Shading and Unshading MPNs as per availability
*C 403231 See ECN NXR Converted from Preliminary to Final Added CY7C1525V18 to the title Removed 300-MHz Speed bin Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed C/C Pin Description in the features section and Pin Description Added power-up sequence details and waveforms Added foot notes # 14, 15, 16 on page# 19 Replaced Three-state with Tri-state Changed the description of IX from Input Load Current to Input Leakage Current on page# 20, Modified the IDD and ISB current values Modified test condition in Footnote # 21 on page# 20 from VDDQ < VDD to VDDQ < VDD Replaced Package Name column with Package Diagram in the Ordering Information table, Updated the Ordering Information

Page 28 of 29 [+] Feedback

CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18

Document History Page

Document Title 72-Mbit QDR -II SRAM 2-Word Burst Architecture Document Number 38-05489
*D 467290 See ECN NXR Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD to Alternately, this pin can be connected directly to VDDQ Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD Changed tTCYC from 100 ns to 50 ns, changed tTF from 10 MHz to 20 MHz, changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table .Modified Power-Up waveform Added additional notes in the AC parameter section Changed the tSC and tHC value from ns to ns for 250 MHz , from ns to ns for 200 MHz, and from ns to ns for 167 MHz. Modified AC Switching Waveform, Corrected the typo In the AC Switching Characteristics Table, Updated the Ordering Information Table
*E 2511080 See ECN VKN/AESA Updated Logic Block diagram , Updated Power-up sequence waveform and it’s description, Updated IDD/ISB specs, Added footnote #19 related to IDD, Changed DLL minimum operating frequency from 80MHz to 120MHz Changed tCYC max spec to 8.4ns for all speed bins, Modified footnotes 21 and 28, Changed ΘJA spec from to Changed ΘJC spec from to
*F 2549270 08/06/08 PYRS Publish in External Web

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

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Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 29 of 29

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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Datasheet ID: CY7C1512V18-250BZC 508058