CY7C1512AV18-200BZXC

CY7C1512AV18-200BZXC Datasheet


CY7C1512AV18

Part Datasheet
CY7C1512AV18-200BZXC CY7C1512AV18-200BZXC CY7C1512AV18-200BZXC (pdf)
Related Parts Information
CY7C1512AV18-167BZXI CY7C1512AV18-167BZXI CY7C1512AV18-167BZXI
CY7C1512AV18-167BZXC CY7C1512AV18-167BZXC CY7C1512AV18-167BZXC
CY7C1512AV18-167BZI CY7C1512AV18-167BZI CY7C1512AV18-167BZI
CY7C1512AV18-167BZC CY7C1512AV18-167BZC CY7C1512AV18-167BZC
CY7C1512AV18-250BZXI CY7C1512AV18-250BZXI CY7C1512AV18-250BZXI
CY7C1512AV18-200BZXI CY7C1512AV18-200BZXI CY7C1512AV18-200BZXI
CY7C1512AV18-250BZC CY7C1512AV18-250BZC CY7C1512AV18-250BZC
CY7C1512AV18-200BZC CY7C1512AV18-200BZC CY7C1512AV18-200BZC
CY7C1512AV18-250BZI CY7C1512AV18-250BZI CY7C1512AV18-250BZI
CY7C1512AV18-250BZIT CY7C1512AV18-250BZIT CY7C1512AV18-250BZIT
CY7C1512AV18-200BZI CY7C1512AV18-200BZI CY7C1512AV18-200BZI
CY7C1514AV18-167BZC CY7C1514AV18-167BZC CY7C1514AV18-167BZC
CY7C1512AV18-250BZXIT CY7C1512AV18-250BZXIT CY7C1512AV18-250BZXIT
CY7C1514AV18-250BZC CY7C1514AV18-250BZC CY7C1514AV18-250BZC
CY7C1514AV18-200BZXI CY7C1514AV18-200BZXI CY7C1514AV18-200BZXI
CY7C1514AV18-200BZI CY7C1514AV18-200BZI CY7C1514AV18-200BZI
CY7C1514AV18-200BZC CY7C1514AV18-200BZC CY7C1514AV18-200BZC
CY7C1514AV18-167BZXC CY7C1514AV18-167BZXC CY7C1514AV18-167BZXC
CY7C1512AV18-250BZXC CY7C1512AV18-250BZXC CY7C1512AV18-250BZXC
CY7C1514AV18-250BZI CY7C1514AV18-250BZI CY7C1514AV18-250BZI
PDF Datasheet Preview
CY7C1512AV18

CY7C1514AV18
72-Mbit II SRAM 2-Word Burst Architecture
• Separate independent Read and Write Data Ports Supports concurrent transactions
• 250 MHz Clock for high Bandwidth
• 2-word Burst on all Accesses
• Double Data Rate DDR Interfaces on both Read and Write Ports data transferred at 500 MHz at 250 MHz
• Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only
• Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches
• Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems
• Single Multiplexed Address Input Bus latches Address Inputs for both Read and Write Ports
• Separate Port Selects for Depth Expansion
• Synchronous Internally Self-timed Writes
• II operates with Cycle Read Latency when Delay

Lock Loop DLL is enabled
• Operates as a QDR I device with one Cycle Read Latency in DLL Off Mode
• Available in x 18, and x 36 Configurations
• Full Data Coherency, providing Most Current Data
• Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD
• Available in 165-Ball FBGA Package 15 x 17 x mm
• Offered in both Pb-free and non Pb-free Packages
• Variable Drive HSTL Output Buffers
• JTAG compatible Test Access Port
• Delay Lock Loop DLL for Accurate Data Placement

Selection Guide

Maximum Operating Frequency

Maximum Operating Current
250 MHz 250 900 1100

Configurations

CY7C1512AV18 4M x 18

CY7C1514AV18 2M x 36

Functional Description

The CY7C1512AV18, and CY7C1514AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit words CY7C1512AV18 , or 36-bit words CY7C1514AV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
200 MHz 200 800 900
167 MHz 167 750 800

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1512AV18

CY7C1512AV18 CY7C1514AV18

D[17:0]
Ordering Information

The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
250 CY7C1512AV18-250BZC

CY7C1514AV18-250BZC

CY7C1512AV18-250BZXC

CY7C1512AV18-250BZI

CY7C1514AV18-250BZI

CY7C1512AV18-250BZXI
200 CY7C1512AV18-200BZC

CY7C1514AV18-200BZC

CY7C1512AV18-200BZXC

CY7C1512AV18-200BZI

CY7C1514AV18-200BZI

CY7C1512AV18-200BZXI

CY7C1514AV18-200BZXI
167 CY7C1512AV18-167BZC

CY7C1514AV18-167BZC

CY7C1512AV18-167BZXC

CY7C1514AV18-167BZXC

CY7C1512AV18-167BZI

CY7C1512AV18-167BZXI

Package Diagram

Package Type
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Operating Range

Commercial
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free
*E 2755831 08/25/2009 VKN/AESA Removed x8 and x9 part number details Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 24 of 24

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback
More datasheets: ECS-67.458-CDX-0068-TR | ECS-64.983-CDX-0067-TR | ECS-48.97-CDX-0065-TR | 760 | DFR0182 | CY7C1512AV18-167BZXI | CY7C1512AV18-167BZXC | CY7C1512AV18-167BZI | CY7C1512AV18-167BZC | CY7C1512AV18-250BZXI


Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1512AV18-200BZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1512AV18-200BZXC 508055